JP2718376B2 - Semiconductor integrated circuit and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit and a method of manufacturing the same, and more particularly to an analog / digital hybrid semiconductor integrated circuit including an IIL gate in a digital circuit and a method of manufacturing the same.

[0002]

2. Description of the Related Art FIG. 4 is a circuit diagram of an IIL gate, FIG. 5 is a plan view schematically showing a conventional example, and FIGS.
1 shows a cross-sectional view taken along line XX and a line YY of FIG.

[0003] IIL switching transistor Q _N is N-type epitaxial layer 2-1 emitter region of a semiconductor substrate having deposited N-type epitaxial layer (2-1, 2-2) to the P-type silicon substrate 1 of the gate, a P-type This is a reverse NPN transistor having the diffusion layer 6-1 as a base region and the N ⁺ type diffusion layers 7-11 and 7-12 as collector regions. That is, a vertical NPN transistor (N ⁺ type diffusion layer 7-2 is an emitter region, P type diffusion layer 6
2 as a base region and an N-type epitaxial layer 2-2 as a collector region. ) The emitter and collector are reversed.

[0004]

As described above,
Conventional IIL gate switching transistor Q _N
Has a structure in which the vertical NPN transistor is operated in the reverse direction, so that the emitter region becomes a low-concentration N-type epitaxial layer, the efficiency of electron injection into the base region is poor, and the current amplification factor β does not increase. there were.

The base region (P) of a vertical NPN transistor
The type diffusion layer 6-2) is formed on the lower concentration of the base region (P-type diffusion layer 6-1) of the switching transistor Q _N in a separate process, so that to increase the current amplification factor β even a little .

In particular, a vertical NPN of a mixed analog circuit
If the breakdown voltage of the transistor needs to be increased, the transistor layer breakdown voltage is increased by setting the concentration of the epitaxial layer 2-2 low and improving the base-collector junction breakdown voltage. 2-1 and 2-2 had a problem that it is difficult to increase the current amplification factor β of Q _N because more and more reduced concentrations when) formed in the same step. Furthermore, lowering the base concentration of Q _N of IIL gate emitter - for current leakage failure due to decrease of breakdown voltage and surface inversion by punch-through between the collector is likely to occur, the guard ring for surface inversion preventing (P ⁺ -type diffusion layer 1
1) needs to be inserted between the emitter and the collector, and I
There is also a problem that the area occupied by the IL gate becomes large and it is difficult to achieve high integration.

SUMMARY OF THE INVENTION An object of the present invention is to provide an analog / digital hybrid semiconductor integrated circuit which can increase the current amplification factor of an IIL gate switching transistor, further reduce the occupied area, and is not affected by an increase in the withstand voltage of an analog circuit. To provide.

[0008]

According to the present invention, there is provided a semiconductor integrated circuit comprising: a first P-type base region formed in a first N-type semiconductor layer on a surface of a semiconductor substrate; the first N-type collector region and the first P-type each said contact with the base region a first N plurality formed in a surface portion of the
A first N + -type emitter region formed on the surface of the first N-type semiconductor layer at a certain distance from the first N + -type collector region, wherein each of the first N -type collector region and the first N +
The distance from the emitter region is set smaller than the thickness of the first P-type base region immediately below the first N-type collector region.
The current amplification factor is the first N + type emitter region, the first P +
Dominated by the mold base region and the first N-type collector region
An IIL gate having the multi-collector type first NPN transistor as a switching transistor, and a second N-type semiconductor layer formed at the same time as the first N-type semiconductor layer on the surface of the semiconductor substrate and electrically insulated therefrom. N
A second N-type collector region including a type semiconductor layer, a second P-type base region formed simultaneously with the first base region on a surface portion of the second N-type semiconductor layer, and the second N-type collector region. 2 on the surface of the P-type base region and the same as the first N-type collector region.
And a second NPN transistor having a second N + type emitter region that is sometimes formed.

Furthermore, the first P-type base region right under the first N-type semiconductor layer on the first N ⁺ -type buried layer is provided first N ⁺
A second N ⁺ -type buried layer provided in the second N-type semiconductor layer immediately below the second P-type base region and connected to the second N-type semiconductor layer from the surface of the second N-type semiconductor layer. A high-concentration collector extraction region that reaches the mold buried layer can be provided.

Further, the method of manufacturing a semiconductor integrated circuit according to the present invention comprises the steps of: providing a P-type semiconductor substrate and an N-type epitaxial layer formed on the surface of the substrate; an interface between the P-type semiconductor substrate and the N-type epitaxial layer; Providing a semiconductor substrate having a first N + type buried layer and a second N + type buried layer selectively formed, respectively; Forming an element isolation region surrounding each of the N + type buried layers to partition a digital circuit formation region and a bipolar transistor formation region for an analog circuit; and forming the N-type epitaxial layer in the digital circuit formation region. The first N + -type semiconductor layer and the second N-type semiconductor layer serving as the N-type epitaxial layer in the bipolar transistor forming region are respectively provided from the respective surfaces thereof with the first N + -type semiconductor layer. Forming a first N + type diffusion layer and a second N + type diffusion layer reaching the buried layer and the second N + type buried layer, respectively, forming the first N type semiconductor layer into at least one IIL gate; Forming as a first N + type emitter region of a multi-collector type switching transistor of an ILL gate and a collector extraction region of a bipolar transistor;
Forming a P-type diffusion layer as a first P-type base region of the switching transistor and a second P-type base region of the bipolar transistor in the type semiconductor layer and the second N-type semiconductor layer, respectively; The first P-type base region and the second P-type base region are respectively located at predetermined distances from the first base contact region and the second base contact region of P + type and the first base contact region. IIL gate injector
Forming a P @ + -type emitter region of the transistor; and providing N-type diffusion layers in the first P-type base region and the second P-type base region, respectively, in the multi-collector switching transistor. Forming a plurality of first N-type collector regions and a second N-type emitter region of the bipolar transistor.

Further, a high-concentration N-type diffusion layer may be formed at the same time as the first N-type collector region in the surface portion of the first N-type emitter region in the vicinity of the first N-type collector region. it can.

[0012]

The switching transistor of the IIL gate has a high-concentration first N-type emitter region.
The first P-type base region sandwiched between the N-type emitter region and the first N-type collector region functions as an active base region, and the base width can be freely set within a range that is lithographically possible. Therefore, the current amplification factor β can be increased irrespective of the concentration of the first N-type semiconductor layer. Further, the first and second P-type base regions can be formed in the same process, and the guard ring need not be provided.

[0013]

1 is a plan view of a semiconductor chip showing a first embodiment of the present invention, and FIGS. 2A and 2B are FIGS.
3 is a sectional view taken along line XX and YY of FIG.

In this embodiment, an N-type epitaxial layer (2-1, 2-5) having a thickness of 3 to 5 μm is formed on the surface of a P-type silicon substrate 1.
-2) formed on the first N-type semiconductor layer (N-type epitaxial layer 2-1) on the surface of the semiconductor substrate formed with
P-type base region (P-type diffusion layer 6-1) and two first N-type collector regions (N ⁺ -type diffusion layer 7) formed on the surface of the first P-type base region (6-1). -11, 7-12)
And a first N-type semiconductor layer formed on the surface of the first N-type semiconductor layer (2-1) in contact with the first P-type base region (6-1).
⁺ Emitter region (N ⁺ diffusion layer 8-1)
Distance of N-type collector region and (7-11,12) and the first N ⁺ -type emitter region (8-1) L ₂ (e.g. 0.5μ
m) is set to be smaller than the thickness B ₂ (for example, 0.8 μm) of the first P-type base region (6-1) immediately below the first N-type collector region (7-11, 12). the NPN transistor and the switching transistor Q _N, the first first base contact region (P ⁺ -type diffusion layer 10) the collector region, a surface portion of the N-type epitaxial layer 2-1
P ⁺ -type diffusion layer 9 provided at a predetermined distance (for example, 1.5 μm) from base contact region (10) of FIG. 1 is located between base region 9 and 10 of emitter region and N-type epitaxial layer 2-1. Horizontal injector
And IIL gate having by the transistor Q _P, the first N-type semiconductor layer on the surface of the aforementioned semiconductor substrate (2-1)
A second N-type collector region including a second N-type semiconductor layer (N-type epitaxial layer 2-2) electrically insulated from the second N-type semiconductor layer, formed on the surface of the second N-type semiconductor layer (2-2) The second
P-type base region (P-type diffusion layer 6-2) and second P-type region
And a second NPN transistor having a high-concentration second N ⁺ -type emitter region (N ⁺ -type diffusion layer 7-2) formed on the surface of the mold base region (6-2). And a circuit.

Next, the manufacturing method of this embodiment will be described. P-type silicon substrate 1 and N-type epitaxial layer formed on the surface thereof (concentration 1 × 10 ^{15 to} 5 × 10 ¹⁵ c
m ⁻³ ), a first N ⁺ -type buried layer 3-1 and a second N-type buried layer selectively formed at and near the interface between the P-type silicon substrate 1 and the aforementioned N-type epitaxial layer. Three layers
2 is prepared. Next, an element isolation region (field oxide film 4 and P ⁺ -type diffusion layer 5) surrounding each of first N ⁺ -type buried layer 3-1 and second N ⁺ -type buried layer 3-2. To form a digital circuit formation region A and a bipolar transistor formation region B for analog circuits. Next, the digital circuit formation area A
The first N-type semiconductor layer 2-1 as the above-mentioned N-type epitaxial layer and the second N-type semiconductor layer 2-1 as the above-mentioned N-type epitaxial layer in the bipolar transistor formation region B have respective surfaces. To the first N ⁺ type buried layer 3-
First N reaching the first and second N ⁺ -type buried layer 3-2 ⁺
Type diffusion layer and the second N ⁺ type diffusion layer, and the first N type semiconductor layer 3-1 respectively in two IIL gate formation regions A.
a, formed as a collector extraction region 8-2 of the first N ⁺ -type emitter region 8-1 and bipolar transistors of the switching transistor Q _N of ILL gate partitioning the Ab. Next, boron ion implantation is performed for 30 to 5 times.
0 keV, 1 × 10 ^{13 to} 5 × 10 ¹⁴ cm ⁻² , and a P-type diffusion layer is respectively switched on the first N-type semiconductor layer 2-1 and the second N-type semiconductor layer 2-2. It formed as a second P-type base region 6-2 of the first P-type base region 6-1 and the aforementioned bipolar transistor of the transistor Q _N. Next, the first P-type base region 6-1 and the second P-type base region 6-2 are respectively provided with a P ⁺ -type first base contact region 10 and a second P-type base region 6-2.
Base contact region 12 and the first base
A predetermined distance (1.5 μm) from contact region 10
Of the P injector transistor Q _P of IL gate ⁺
A mold emitter region 9 is formed. Next, arsenic ion implantation is performed at 50 to 70 keV, 5 × 10 ¹⁵ to 1 × 10 ¹⁶ cm ^−2.
The first N-type collector region 7-1 of the first carried out at conditions of P-type base region 10 and the second P-type N-type diffusion layer, respectively the base region 12 switching transistor Q _N
1, 7-12 and the second N-type emitter region 7-2 of the aforementioned bipolar transistor. Forming an interlayer insulating film 13, forming contact holes H1 to H8,
Electrodes 14I, 14BI, 14C11, 14C12, and 14C are formed by depositing and patterning an aluminum-based alloy film.
2, 14E2 and 14B2 are formed. Reference numeral 4 denotes a field oxide film.

The N ⁺ type diffusion layers 8-1 and 8-2 are formed in the same step and have an impurity concentration of at least 1 × 10 ¹⁹ cm ^−3.
It is possible to do. Thus, the emitter region of the switching transistor Q _N of IIL gate (8-
1) high concentration (Figure 5, the impurity concentration of the emitter region of the conventional example Q _N of Figure 6 can be a ^{1 × 10 15 ~5 × 10 15} cm -3), the mask base width L ₂ is the time of ion implantation It can be set as small as about 0.5 μm under the limitations of the precision of formation and heat treatment. Therefore, the current amplification factor can be made larger than before, so that the speed of the IIL gate can be improved. Note that Q
The _N as backward but NPN transistor is parasitic its base width B ₂ to the emitter of the N-type epitaxial layer 2-1 (about 0.8 [mu] m) is larger than L ₂ to the current amplification of Q _N Can be made negligible.

Since the N-type epitaxial layers 2-1 and 2-2 can be formed in a single epitaxial growth step and can be made to have a high concentration to the extent that there is no fear of surface inversion, there is no need to provide a card ring and an IIL gate. Occupied area can be reduced. Further, it is possible to coexist with high-voltage vertical NPN in so the current amplification factor Q of the switching transistor Q _N can be increased regardless of the concentration of the N-type epitaxial layer.

FIG. 3A is a plan view of a semiconductor chip showing an IIL gate portion according to a second embodiment of the present invention.
FIG. 3B is a sectional view taken along line XX of FIG.

In this embodiment, the first N-type collector region (7-
11) An N ⁺ -type diffusion layer 7-3 formed simultaneously with this is formed on the surface of the N ⁺ -type diffusion layer 8-1.

Since the N ⁺ -type diffusion layers 7-3 and the like can be formed by ion implantation and activation heat treatment, the N ⁺ -type diffusion layers 7-3 and the like can be easily made to have a high concentration compared to the N ⁺ -type diffusion layers 8-1 and the like that require indentation diffusion. also an advantage of increasing the accuracy of the base width L _2.

[0021]

As described above, according to the present invention, I
Since the emitter region of the switching transistor of the IL gate can be made highly concentrated and the base width can be set by lithography, the current amplification factor β can be increased. In addition, since the base region can be formed in the same process as the base region of the vertical NPN transistor of the analog circuit, the process can be simplified, the surface concentration can be increased, there is no need to worry about surface inversion, and there is no need for a guard ring. There is an advantage that can be made. Further, since the current amplification factor β of the switching transistor of the IIL gate can be increased regardless of the epitaxial layer concentration, it can coexist with a high breakdown voltage vertical NPN transistor.

[Brief description of the drawings]

FIG. 1 is a plan view showing a first embodiment of the present invention.

FIG. 2 is a sectional view taken along line XX of FIG. 1 (FIG. 2A) and FIG.
FIG. 3 is a sectional view taken along line -Y (FIG. 2B).

FIG. 3 is a plan view (FIG. 3) showing a second embodiment of the present invention;
(A)) and a sectional view taken along line YY in FIG.
(B)).

FIG. 4 is a circuit diagram of an IIL gate.

FIG. 5 is a plan view showing a conventional example.

6 is a sectional view taken along the line XX of FIG. 5 (FIG. 6A) and FIG.
FIG. 6 is a sectional view taken along line -Y (FIG. 6B).

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 P-type silicon substrate 2-1 and 2-2 N-type epitaxial layer 3-1 and 3-2 N ⁺ type buried layer 4 Field oxide film 5 P ⁺ type diffusion layer 6-1 and 6-2 P type diffusion layer 7-11, 7-12, 7-2, 7-3 N ⁺ type diffusion layer 8-1, 8-2 N ⁺ type diffusion layer 9, 10, 11, 12 P ⁺ type diffusion layer 13 Interlayer insulating film H1, H2, ..., H8 Contact holes 14B1, 14B2, 14C11, 14C12, 14E
1,14E2,14I electrode

Claims (4)

(57) [Claims] 1. A first surface of a semiconductor substrate of a first P-type base region formed in the N-type semiconductor layer, the first P-type base region a plurality of first formed on the surface portion of the Each in contact with the N-type collector region and the first P-type base region;
The first N-type collector region is separated from the first N-type collector region by a certain distance .
A first N + -type emitter region formed on the surface of the N-type semiconductor layer, and a distance between each of the first N-type collector regions and the first N + -type emitter region is the first N + -type emitter region. The current amplification factor is set to be smaller than the thickness of the first P-type base region immediately below the N-type collector region so that the current amplification factor is smaller than that of the first N + -type emitter region.
Region, first P-type base region and first N-type collector region
Multi-collector type first NP controlled by
An IIL gate having an N transistor as a switching transistor;
A second N-type collector region including a second N-type semiconductor layer formed at the same time as the N-type semiconductor layer and electrically insulated from the second N-type semiconductor layer ; Be
Said first N-type co on the surface of the second P-type base region and the second P-type base region formed simultaneously with the source region
A second NPN transistor having a second N + type emitter region formed simultaneously with the rectifier region . 2. A first N ⁺ -type buried layer is provided in a first N-type semiconductor layer immediately below a first P-type base region, is connected to a first N ⁺ -type emitter region, and is connected to a second N ⁺ -type emitter region. A second N ⁺ -type buried layer is provided in the second N-type semiconductor layer immediately below the mold base region, and the second N ⁺ -type buried layer has a high concentration reaching from the surface of the second N-type semiconductor layer to the second N ⁺ -type buried layer. 2. The device according to claim 1, further comprising a collector extraction region.
A semiconductor integrated circuit as described in the above. 3. A P-type semiconductor substrate and an N-type epitaxial layer formed on the surface thereof, and an interface between the P-type semiconductor substrate and the N-type epitaxial layer and a first N-type layer selectively formed near the interface. Providing a semiconductor substrate having a + type buried layer and a second N + type buried layer; and surrounding the periphery of the first N + type buried layer and the second N + type buried layer, respectively. Forming an element isolation region to partition a digital circuit formation region and a bipolar transistor formation region for an analog circuit; and a first N-type semiconductor layer, which is the N-type epitaxial layer in the digital circuit formation region, and The N in the bipolar transistor forming region
The first N + -type buried layer and the second N-type buried layer
A first N + type diffusion layer and a second N
The + type diffusion layer, each of which divides the first N type semiconductor layer into at least one IIL gate formation region;
Forming a first N + -type emitter region of a multi-collector switching transistor with a gate and a collector extraction region of a bipolar transistor; and forming the first N-type semiconductor layer and the second N-type semiconductor layer in the first and second N-type semiconductor layers, respectively. Forming a P-type diffusion layer as a first P-type base region of the switching transistor and a second P-type base region of the bipolar transistor;
A P + type first base contact region, a second base contact region, and a second base contact region, respectively, and the IIL at a predetermined distance from the first base contact region. Forming a P @ + -type emitter region of the gate injector transistor; and forming the first P-type base region and the second P-type emitter region.
Wherein the N-type diffusion layer, respectively -type base region multi collector
The method of manufacturing a semiconductor integrated circuit, characterized in that a step of forming a second N-type emitter region of the plurality of first N-type collector region and the bipolar transistor of the data type of the switching transistor. 4. A high-concentration N-type diffusion layer is formed in the surface of the first N-type emitter region in the vicinity of the first N-type collector region simultaneously with the first N-type collector region. 4. The method for manufacturing a semiconductor integrated circuit according to 3.