JP4815754B2 - Semiconductor device - Google Patents

Description

The present invention relates to a semiconductor device in which a plurality of IIL device is formed in the semiconductor substrate.

  A semiconductor device in which a plurality of IIL (Integrated Injection Logic) elements and bipolar transistors are formed on the same semiconductor substrate is disclosed in, for example, Japanese Patent Laid-Open No. 9-289256 (Patent Document 1).

  FIG. 5 shows an equivalent circuit of the IIL element 1. As shown in FIG. 5, the IIL element 1 is configured by using the pnp transistor 2 as a switching transistor, the npn transistor 3 as a current injection source, and connecting the collector of the pnp transistor 2 and the base of the npn transistor 3. . In the IIL element 1, as shown in FIG. 5, the base 2B of the pnp transistor 2 and the emitter 3E of the npn transistor 3 are normally grounded.

  FIG. 6 shows a plan view when the IIL element 1 shown in FIG. 5 is configured on a semiconductor substrate. The IIL element 1 shares the collector 2C of the horizontal pnp transistor 2 and the base 3B of the vertical npn transistor 3 in the p-type region 4, and is connected to the base 2B of the horizontal pnp transistor 2 that is used while being grounded. In this structure, the n-type region 5 having a high concentration shares the emitter 3E of the npn transistor 3. As the IIL element 1, the emitter 2E of the pnp transistor 2 is referred to as an injector I, and the base 3B, emitter 3E, and collector 3C of the npn transistor 3 are referred to as base B, emitter E, and collector C, respectively.

  When a large number of IIL elements are formed on a semiconductor substrate, the n-type region 5 can be shared between the IIL elements to achieve high integration. In addition, the IIL element uses the pnp transistor 2 instead of the load resistance, and thus has a feature of low power consumption, and is used when configuring a logic circuit that requires high speed.

  7A and 7B are diagrams showing a semiconductor device 10 in which a plurality of IIL elements and high-breakdown-voltage bipolar transistors are formed on the same semiconductor substrate, as disclosed in Patent Document 1. .

  FIG. 7A is a plan view showing a part of the semiconductor device 10. Three IIL elements 11 to 13 are arranged on a semiconductor substrate to constitute a part of the logic circuit unit 14. On the right side of the logic circuit unit 14, the npn type vertical type is shown. A high breakdown voltage bipolar transistor 15 is disposed on the same semiconductor substrate. FIG. 2B is a schematic cross-sectional view showing the XX ′ cross section (the cross section of the IIL elements 11 and 12) in FIG. In the following, the injector (I), base (B), collector (C), and emitter (E) of each element are shown with I, B, C, and E attached to the reference numerals of each element. .

In FIG. 7B, the three IIL elements 11 to 13 are formed on a p-type silicon substrate (semiconductor substrate) 16. On the p-type silicon substrate 16, antimony (Sb) having a concentration of 10 ¹⁸ per unit area is diffused to a depth of about 7 μm to form a high-concentration n-type buried diffusion layer 17. A low-concentration n-type epitaxial layer (common emitter E) 18 having a surface concentration of about 10 ¹⁵ is formed.

In FIG. 7A, the three IIL elements 11 arranged in the middle of the three diffused boron (B) having a concentration of about 10 ¹⁸ to the epitaxial layer 18 to a depth of about 3 μm, resulting in a high concentration of 10 × 20 μm. A p-type injector region 19 (11I) is formed, and boron (B) is diffused in the epitaxial layer 18 to form a p-type base region 20 (11B). Further, a concentration of 10 ²⁰ is formed in the base region ^20. After implanting a certain amount of phosphorus (P) by ion implantation, thermal diffusion is performed to form high concentration n-type collector regions 21a, 21b and 21c (11Ca, 11Cb and 11Cc) having an area of 10 × 14 μm. It is. The other elements 12 and 13 are formed in the same manner as the IIL element 11. The configuration of the high breakdown voltage bipolar transistor 15 is well known and will not be described.

In addition, phosphorus (P) and arsenic (As) having a concentration of about 10 ²⁰ are implanted deep into the epitaxial layer 18 by ion implantation, and then thermal diffusion is performed to form a high concentration n-type region 22 (E). The tip end portion of the buried diffusion layer 17 overlaps a part thereof. The high-concentration n-type region 22 is formed between the elements 11 to 13 (separation region) as shown by the hatched mesh in FIG. 7A, and each of the IIL elements 11 to 13 is electrically connected. Separated.

Actually, each region is provided with a contact portion, and the contact portion is provided with aluminum wiring by sputtering or the like. However, the illustration is omitted in FIG. The semiconductor device 10 configured as described above provides an output signal obtained as a result of the logical operation in the logic circuit unit 14 to the high breakdown voltage bipolar transistor 15, and the high breakdown voltage bipolar transistor 15 In response to this, a load (not shown) is driven.
Japanese Patent Laid-Open No. 9-289256

In the semiconductor device 10 of FIG. 7A, the concentration of the p-type impurity is different between the bases 11B to 13B of the vertical npn transistors in the IIL elements 11 to 13 and the base of the npn-type high breakdown voltage bipolar transistor 15. There is a need to. Specifically, in order to increase the reverse current amplification factor βup of the npn transistors constituting the IIL elements 11 to 13 and to secure the driving ability D _eff of the IIL elements 11 to 13, the bases 11B to 11B of the IIL elements 11 to 13 are secured. 13B makes the impurity concentration about 1/3 as compared with the base region in the high breakdown voltage bipolar transistor 15. Therefore, in manufacturing the semiconductor device 10 of FIG. 7A, the ion implantation of the bases 11B to 13B in the IIL elements 11 to 13 and the ion implantation of the base in the high breakdown voltage bipolar transistor 15 are performed in separate steps. . For this reason, this is a factor for increasing the manufacturing cost of the semiconductor device 10.

On the other hand, a method of performing ion implantation of the bases 11B to 13B of the IIL elements 11 to 13 and the base of the high breakdown voltage bipolar transistor 15 in a single process and securing the driving capability D _eff of the IIL elements 11 to 13 The following method can be considered. That is, the interval between the injectors 11I to 13I and the bases 11B to 13B in the IIL elements 11 to 13 is widened to lower the reverse current amplification factor α _r of the pnp transistors constituting the IIL elements 11 to 13, and the IIL elements 11 to 13 This is a method of ensuring the driving capability D _eff . However, in this case, the element sizes of the IIL elements 11 to 13 are increased by 30% or more. Further, the number of collectors 11Ca to 11Cc, 12Ca to 12Cc, and 13Ca to 13Cc arranged on the bases 11B to 13B can be reduced to widen the intervals between the injectors 11I to 13I and the bases 11B to 13B. This reduces the degree of freedom in logic circuit design.

The present invention includes a plurality of IIL device is a semiconductor device formed by forming a semi-conductor substrate, a small type, it is an object of the flexibility of the logic circuit design to provide a semiconductor device that does not decrease .

The invention according to claim 1 is a semiconductor device in which a plurality of IIL elements are formed on a semiconductor substrate, and the IIL element is connected to a collector of a horizontal pnp transistor and a base of a vertical npn transistor. The base of the pnp transistor and the emitter of the npn transistor are grounded, and the semiconductor substrate is formed on the buried diffusion layer containing a high concentration n-conductivity type impurity and the buried diffusion layer. And two p-conductivity type impurity diffusions, wherein the pnp transistor is formed based on the epitaxial layer and spaced apart from the surface layer of the epitaxial layer. The region is an emitter and a collector, and the npn transistor is the collector of the pnp transistor. A substrate surface of the semiconductor substrate having a p conductivity type impurity diffusion region as a base, the epitaxial layer as an emitter, and an n conductivity type impurity diffusion region formed in a surface layer of the p conductivity type impurity diffusion region as a base as a collector. in inner, a pnp transistor p conductivity type in between the impurity diffusion regions is the collector of the pnp transistor p conductivity type impurity diffusion region is placed to the I IL elements is an emitter of is being made more structure, Each of the plurality of IIL elements is surrounded by an n + diffusion region containing high-concentration n-conductivity type impurities reaching the buried diffusion layer from the surface of the semiconductor substrate within the substrate surface of the semiconductor substrate, in the substrate surface of the semiconductor substrate, interposed in the emitter and collector of said pnp transistor of said IIL device其s The base region, the n + diffusion region is characterized by comprising protrudes.

According to this, in the substrate surface of the semiconductor substrate, p conductivity type impurities in between the diffusion region is a collector of the pnp transistor p conductivity type impurity diffusion region is placed to the I IL elements is an emitter of the pnp transistor the form multiple structure,其's multiple IIL elements, so as to be surrounded by the n + diffusion region containing n-type conductivity impurity of high concentration to reach the buried diffusion layer, Oite the IIL device其people, the By forming the n + diffusion region in a base region sandwiched between the emitter and collector of the pnp transistor, holes that are carriers are captured in the n + diffusion region. Thus, without increasing the emitter and the collector distance in pnp transistor (injector and based intervals in IIL element), can be lowered reverse current amplification factor alpha _r of the pnp transistor, whereby the effective driving capability of the IIL element D _eff can be ensured. Further, it is not necessary to reduce the number of collectors arranged at the base of each IIL element. Therefore, the semiconductor device can be a small semiconductor device that does not reduce the degree of freedom in logic circuit design.

  According to a second aspect of the present invention, the bipolar transistor is formed at a position different from the IIL element on the semiconductor substrate, the bipolar transistor is an npn transistor, and the base of the bipolar transistor is a surface layer of the epitaxial layer. A p-type impurity diffusion region formed in a portion, wherein the base of the bipolar transistor and the base of the npn transistor in the IIL element are formed with the same impurity concentration.

In the semiconductor device in which the n + diffusion region protrudes from the base region of the pnp transistor, instead of increasing the reverse current amplification factor β _up of the npn transistor, the reverse current amplification factor α _r of the pnp transistor is decreased to reduce the IIL element The effective driving capability D _eff is ensured. Therefore, when the bipolar transistor to be formed in another position of the semi-conductor substrate of the npn transistor and a base of the npn transistor the base and IIL element of the bipolar transistor, for example, it can be formed simultaneously by the same ion implantation process. In this case, since the ion implantation process for the base of the IIL element and the bipolar transistor is made common, the manufacturing cost can be reduced and an inexpensive semiconductor device can be obtained.

The invention according to claim 3 is a semiconductor device in which a plurality of IIL elements are formed on a semiconductor substrate, wherein the IIL element is connected to a collector of a horizontal pnp transistor and a base of a vertical npn transistor. The base of the pnp transistor and the emitter of the npn transistor are grounded, and the semiconductor substrate is formed on the buried diffusion layer containing a high concentration n-conductivity type impurity and the buried diffusion layer. And two p-conductivity type impurity diffusions, wherein the pnp transistor is formed based on the epitaxial layer and spaced apart from the surface layer of the epitaxial layer. The region is an emitter and a collector, and the npn transistor is the collector of the pnp transistor. A substrate surface of the semiconductor substrate having a p conductivity type impurity diffusion region as a base, the epitaxial layer as an emitter, and an n conductivity type impurity diffusion region formed in a surface layer of the p conductivity type impurity diffusion region as a base as a collector. in inner, a pnp transistor p conductivity type in between the impurity diffusion regions is the collector of the pnp transistor p conductivity type impurity diffusion region is placed to the I IL elements is an emitter of is being made more structure, Each of the plurality of IIL elements is surrounded by an n + diffusion region containing high-concentration n-conductivity type impurities reaching the buried diffusion layer from the surface of the semiconductor substrate within the substrate surface of the semiconductor substrate,其s Oite said IIL device, the impurity concentration of the p conductivity type impurity diffusion region is a base of the npn transistor, the n In n the substrate surface sandwiched emitter and collector of the transistor, it is characterized by having a repeating pattern distribution of the high density and low density.

In addition, as described in claims 4 and 5 , the repetitive pattern distribution can be a stripe shape or a lattice shape.

Also in the semiconductor device according to any one of claims 3 to 5, in the substrate surface of the semiconductor substrate, the p conductivity type impurity diffusion that is the collector of the pnp transistor with the p conductivity type impurity diffusion region that is the emitter of the pnp transistor interposed therebetween. the I IL element region are placed form a plurality structure,其's multiple IIL elements have to be surrounded by the n + diffusion region containing n-type conductivity impurity of high concentration to reach the buried diffusion layer.
On the other hand, in the semiconductor device according to claim 1 and 2, by forming projecting the n + diffusion region to the base region of the pnp transistor constituting the IIL device, lower the reverse current amplification factor alpha _r of the pnp transistor, IIL element The effective driving ability D _eff is ensured. In contrast, in the semiconductor device according to any one of claims 3 to 5, the impurity concentration of the p-conductivity type impurity diffusion region which is the base of the npn transistor constituting the IIL element is within the substrate plane sandwiched between the emitter and the collector. In FIG. 4, the pattern has a high density and low density repetitive pattern distribution. For this reason, in the base region sandwiched between the emitter and collector of the npn transistor, there is a region with a low impurity concentration consisting of a repetitive pattern, and substantially the same effect is obtained as when the impurity concentration of the base of the npn transistor is lowered. . Therefore, the reverse current amplification factor βup of the npn transistor can be increased, thereby ensuring the effective driving capability D _eff of the IIL element. Further, it is not necessary to reduce the number of collectors arranged at the base of each IIL element. Therefore, the semiconductor device can be a small semiconductor device that does not reduce the degree of freedom in logic circuit design.

A plurality of IIL elements and bipolar transistors are formed on the same semiconductor substrate, the bipolar transistor is an npn transistor, and a base of the bipolar transistor is formed on a surface layer portion of the epitaxial layer. In the case of the diffusion region, an ion implantation mask having a repetitive pattern is arranged in the base region of the npn transistor in the IIL element so that the base of the bipolar transistor and the base of the npn transistor in the IIL element are the same. They can be formed simultaneously by an ion implantation process.

  Thus, by making the ion implantation process of the base of the IIL element and the bipolar transistor in common, the manufacturing cost of the semiconductor device can be reduced and an inexpensive semiconductor device can be obtained.

  The best mode for carrying out the present invention will be described below with reference to the drawings.

First, the effective drive capability D _eff of the IIL element 11 will be briefly described using the IIL element 11 in the semiconductor device 10 shown in FIGS. Note that the calculation and evaluation method of the effective driving ability Deff of the IIL element 11 is disclosed in detail in Patent Document 1, and the description thereof is omitted.

The effective driving capability D _eff of the IIL element 11 shown in FIGS. 7A and 7B is expressed as I _b , the load current (base current) flowing into the base of the IIL element 11, and the collector saturation current of the IIL element 11 as I _c . In this case, it is expressed by the following formula.
(Equation 1) D _eff = I _c / I _b = β _up (1−α _r ) / (1 + 2α _sb )
Here, α _r is the reverse current amplification factor of the pnp transistor of the IIL element 11. β _up is the reverse current amplification factor of the npn transistor in the IIL element 11. These are set by setting the area ratio between the collector region 21 and the base region 20 of the IIL element 11 shown in FIGS. 7A and 7B and the interval between the injector region 19 and the base region 20. For example, when the area ratio between the collector region 21 and the base region 20 is set to 10% and the distance between the injector region 19 and the base region 20 is set to 11 μm, the reverse current gain β _up is approximately 20, The directional current gain α _r is about 0.7. Α _sb is the forward current amplification factor of the two parasitic pnp transistors existing between the base 11B of the IIL element 11 and the bases 12B and 13B of the IIL elements 12 and 13.

The effective drive capability D _eff of the IIL element 11 shown in the above formula 1 represents the drive capability in consideration of the influence of the parasitic pnp transistor existing between the other IIL elements 12 and 13. In evaluating the effective driving capability D _eff of the IIL element 11, the noise margin needs to be positive in order to maintain the logic high level of the IIL element 11, and D _eff > 1 is the condition. As described above, the effective driving capability D _eff is theoretically only required to exceed 1. However, in actuality, the semiconductor device 10 is used in consideration of process variations up to ± 4σ (σ is a standard deviation). For example, it is set to 5 by taking into account the fluctuation of the ambient temperature in the environment in which it is performed. In order to achieve this effective driving capability D _eff , when β _up = 20 and α _r = 0.7, the forward current amplification factor α _{sb of the} parasitic pnp transistor must be 0.1 (note that this In order to achieve the forward current amplification factor α _sb of the parasitic pnp transistor, the overlap thickness between the buried diffusion layer 17 and the high-concentration n-type region 22 needs to be about 5.5 μm based on actually measured data). Therefore, for example, when the thickness of the epitaxial layer 18 is 5.5 μm, the surface (epitaxial layer) of the semiconductor device 10 in the high-concentration n-type region 22 which is the minimum necessary for electrically separating the IIL elements from each other. 18), the diffusion depth _Xj is about 11 μm.
(First embodiment)
1A and 1B show a semiconductor device 30 of the present invention in the first embodiment. The semiconductor device 30 is a semiconductor device in which a plurality of IIL elements and high breakdown voltage bipolar transistors are formed on the same semiconductor substrate. FIG. 1A is a perspective view showing one IIL element 31 constituting the semiconductor device 30 cut in half in the Y direction. The plurality of IIL elements constituting the semiconductor device 30 are such that the IIL elements 31 having the structure shown in FIG. 1A are repeatedly arranged adjacent to each other in the X direction and the Y direction within the substrate surface. Thus, the logic circuit portion of the semiconductor device 30 is formed. The high breakdown voltage bipolar transistor constituting the semiconductor device 30 has a well-known structure and is formed at a position different from the plurality of IIL elements on the same semiconductor substrate 40 (not shown). As in the case of FIGS. 5 to 8, in the following, to represent the injector (I), base (B), collector (C) and emitter (E) of each element, , B, C and E. The thin lines in the injector (I), the base (B), the collector (C), and the emitter (E) are isoconcentration lines indicating the impurity concentration distribution.

  The IIL element 31 in FIG. 1A includes a horizontal pnp transistor 32 and a vertical npn transistor 33. In the IIL element 31, as in the equivalent circuit of the IIL element 1 shown in FIG. 5, the collector 32C of the pnp transistor 32 and the base 33B of the npn transistor 33 are connected, and the base 32B of the pnp transistor 32 and the emitter of the npn transistor 33 are connected. 33E is grounded together.

The IIL element 31 is formed on a p-type silicon (Si) substrate 40. On the p-type silicon substrate 40, an antimony (Sb) having a concentration of 10 ¹⁸ per unit area is diffused to a depth of about 7 μm to form a buried diffusion layer 41 containing a high concentration of n-conductivity type impurities. Yes. Further, on the buried diffusion layer 41, epitaxial layer 42 containing an n conductivity type impurity of a low concentration of about surface concentration 10 ¹⁵ are formed. The thickness of the low-concentration epitaxial layer 42 is set according to the lower limit of the breakdown voltage required for the high breakdown voltage bipolar transistor (not shown). For example, when the lower limit of the breakdown voltage is set to 25 V, the thickness of the epitaxial layer 18 necessary for obtaining the breakdown voltage is set to 5.5 μm.

  The lateral pnp transistor 32 that constitutes the IIL element 31 has two p-conductivity type impurity diffusion regions 43 and 44 formed separately from the surface layer portion of the epitaxial layer 42 by using the epitaxial layer 42 as a base 32B, and an emitter 32E. And collector 32C. The vertical npn transistor 33 constituting the IIL element 31 is based on the p conductivity type impurity diffusion region 44 that is the collector 32C of the horizontal pnp transistor 32. The vertical npn transistor 33 has three n-conductivity type impurity diffusion regions formed in the surface layer portion of the p-conduction type impurity diffusion region 44 with the epitaxial layer 42 that is also the base 32B of the horizontal pnp transistor 32 as the emitter 33E. 45 is the collectors 33Ca to 33Cc. As described above, in the IIL element 31, the collector 32C of the pnp transistor 32 and the base 33B of the npn transistor 33 are connected to each other by sharing the p conductivity type impurity diffusion region 44. Further, the base 32B of the pnp transistor 32 and the emitter 33E of the npn transistor 33 are connected to each other by sharing the epitaxial layer 42 and are grounded.

  In the semiconductor device 30, as in the IIL element 31 shown in FIG. 1A, each of the plurality of IIL elements is a semiconductor substrate including a silicon (Si) substrate 40, a buried diffusion layer 41, and an epitaxial layer 42. In the plane, it is surrounded by an n + diffusion region 50 containing high-concentration n-conductivity type impurities reaching the buried diffusion layer 41 from the surface. In each IIL element, as shown in FIG. 1A, in the substrate surface of the semiconductor substrate, in the region of the base 32B sandwiched between the emitter 32E and the collector 32C of the lateral pnp transistor 32, The n + diffusion region 50 is protruded to form an n + diffusion region protrusion 50t.

FIG. 1B is an enlarged plan view showing a portion A surrounded by a one-dot chain line in FIG. If the n + does not form a diffusion region protrusion 50t is the width of the base 32B in the lateral pnp transistor 32 is _{W 0} in the figure by forming the n + diffusion region protrusion 50t, lateral pnp transistor 32 The width of the base 32B (the interval between the n + diffusion region protrusions 50t) becomes narrower as W _{b in} the figure.

In the IIL element 31 shown in FIG. 1A, the n + diffusion region 50 protrudes from the region of the base 32B sandwiched between the emitter 32E and the collector 32C of the pnp transistor 32, so that the carrier at the n + diffusion region protrusion 50t is formed. The hole that is can be captured. Thus, without increasing the distance between the emitter 32E and collector 32C in the pnp transistor 32 (distance between the injectors 31I and the base 31B of the IIL element 31), it is possible to reduce the reverse current amplification factor alpha _r of the pnp transistor 32. Therefore, as shown in Equation 1, the effective driving capability D _eff of the IIL element 31 can be increased, and the necessary effective driving capability D _eff can be ensured.

FIG. 2 shows the result of evaluating the effective driving ability D _eff by changing the width W _b in FIG. The width W ₀ of the base 32B in FIG. 1B is 32 μm. As shown in the result of FIG. 2, the effective drive capability D _eff increases as the interval (width of the base 32B) W _b between the n + diffusion region protrusions 50t decreases, and the effective drive capability D _eff = 5 when W _b = 15 μm. A value is obtained.

In the semiconductor device 30 of FIG. 1A in which the n + diffusion region 50 protrudes from the region of the base 32B of the pnp transistor 32, instead of increasing the reverse current amplification factor β _up of the npn transistor 33, the reverse of the pnp transistor 32 The directional current amplification factor α _r is lowered to ensure the effective driving capability D _eff of the IIL element 31. Therefore, it is not necessary to reduce the number of collectors 31Ca to 31Cc arranged on the base 31B of the IIL element 31. For this reason, the semiconductor device 30 illustrated in FIG. 1A can be a small-sized semiconductor device that does not reduce the degree of freedom in logic circuit design.

In the semiconductor device 30 shown in FIG. 1A, when the high breakdown voltage bipolar transistor (not shown) is an npn transistor, the cost of the semiconductor device 30 can be reduced as follows. That is, when the high breakdown voltage bipolar transistor is an npn transistor and the base is a p-conductivity type impurity diffusion region formed in the surface layer portion of the epitaxial layer 42 similar to FIG. The base of the npn transistor in the IIL element is simultaneously formed by the same ion implantation process. Therefore, the base of the high breakdown voltage bipolar transistor (not shown) and the base 33B of the npn transistor 33 in the IIL element 31 are formed with the same impurity concentration. In this case, since the ion implantation process of the base of the high breakdown voltage bipolar transistor (not shown) is made common with the IIL element 31, the manufacturing cost can be reduced and the inexpensive semiconductor device 30 can be obtained.
(Second Embodiment)
The semiconductor device according to the first embodiment is a semiconductor device in which an n + diffusion region that separates elements is formed so as to protrude from a base region of a pnp transistor in an IIL element to ensure a necessary effective drive capability D _eff . In the semiconductor device of the present embodiment, the necessary effective drive capability D _eff is ensured by controlling the impurity concentration in the base region of the npn transistor in the IIL element to have a predetermined repetitive pattern distribution.

  3A and 3B show a semiconductor device 60 in this embodiment. In the semiconductor device 60 shown in FIGS. 3A and 3B, the same reference numerals are given to the same parts as those of the semiconductor device 30 shown in FIGS. 1A and 1B. Similarly to the case of FIGS. 1A and 1B, each element will be described below to represent the injector (I), base (B), collector (C) and emitter (E) of each element. I, B, C and E are attached to the reference numerals. The thin lines in the injector (I), the base (B), the collector (C), and the emitter (E) are isoconcentration lines indicating the impurity concentration distribution.

  The semiconductor device 60 shown in FIG. 3A is also a semiconductor device in which a plurality of IIL elements and a high voltage bipolar transistor are formed on the same semiconductor substrate. FIG. 3A is a perspective view showing one IIL element 61 constituting the semiconductor device 60 cut in half in the Y direction. The plurality of IIL elements constituting the semiconductor device 60 are such that the IIL elements 61 having the structure shown in FIG. 3A are repeatedly arranged adjacent to each other in the X direction and the Y direction within the substrate surface. Thus, the logic circuit portion of the semiconductor device 60 is formed. The high breakdown voltage bipolar transistor constituting the semiconductor device 60 has a well-known structure and is formed at a position different from the plurality of IIL elements on the same semiconductor substrate 40 (not shown).

  Similarly to the IIL element 31 in FIG. 1A, the IIL element 61 in FIG. 3A also includes a horizontal pnp transistor 62 and a vertical npn transistor 63. Also in the IIL element 31, as in the equivalent circuit of the IIL element 1 shown in FIG. 5, the collector 62C of the pnp transistor 62 and the base 63B of the npn transistor 63 are connected, and the base 62B of the pnp transistor 62 and the npn transistor are connected. The emitter 63E of 63 is grounded together.

  The lateral pnp transistor 62 constituting the IIL element 61 includes two p-conductivity type impurity diffusion regions 43 and 70 formed with the epitaxial layer 42 as a base 62B and spaced apart from the surface layer portion of the epitaxial layer 42, respectively. And collector 62C. The vertical npn transistor 63 constituting the IIL element 61 is based on a p-conductivity type impurity diffusion region 70 which is the collector 62C of the horizontal pnp transistor 62. The p conductivity type impurity diffusion region 70 is controlled so that the impurity concentration has a predetermined repetitive pattern distribution, as will be described later in detail with reference to FIG. The vertical npn transistor 63 has three n-conductivity type impurity diffusion regions formed in the surface layer portion of the p-conduction type impurity diffusion region 70 using the epitaxial layer 42 which is also the base 62B of the horizontal pnp transistor 62 as the emitter 63E. Reference numeral 45 denotes collectors 63Ca to 63Cc. As described above, in the IIL element 61, the collector 62C of the pnp transistor 62 and the base 63B of the npn transistor 63 are connected to each other by sharing the p-conductivity type impurity diffusion region 70. Further, the base 62B of the pnp transistor 62 and the emitter 63E of the npn transistor 63 are connected to each other by sharing the epitaxial layer 42 and are grounded.

  In the semiconductor device 60 as well, as in the semiconductor device 30 shown in FIG. 1A, each of a plurality of IIL elements, such as the IIL element 61 shown in FIG. In the substrate surface of the semiconductor substrate composed of the buried diffusion layer 41 and the epitaxial layer 42, the semiconductor substrate is surrounded by an n + diffusion region 50 containing a high concentration n-conductivity type impurity reaching the buried diffusion layer 41 from the surface. On the other hand, each IIL element of the semiconductor device 60 is different from the IIL element of the semiconductor device 30 shown in FIG. 1A in the region of the base 62B sandwiched between the emitter 62E and the collector 62C of the horizontal pnp transistor 62. , N + diffusion region 50 is not protruded.

  FIG. 3B is an enlarged cross-sectional view of a portion B surrounded by a one-dot chain line in FIG.

  In the semiconductor device 60 of FIG. 3A, the impurity concentration of the p conductivity type impurity diffusion region 70 is sandwiched between the emitter 63E and the collectors 63Ca to 63Cc in the vertical npn transistor 63 as shown in FIG. 3B. The region of the base 63B (pinch region) has a repeated pattern distribution of high density and low density. The repeated pattern distribution of the impurity concentration can be a stripe shape or a lattice shape within the substrate surface. This repeated pattern distribution of the impurity concentration is formed by ion-implanting impurities using the ion implantation mask M70 having the repeated pattern shown in FIG. 3B and thermally diffusing the implanted impurities.

In the semiconductor device 30 of FIGS. 1A and 1B according to the first embodiment, the n + diffusion region 50 is protruded and formed in the base 32B region of the pnp transistor 32 that constitutes the IIL element 31, thereby reversing the pnp transistor 32. The directional current amplification factor α _r was lowered, and the effective driving capability D _eff of the IIL element 31 was ensured. On the other hand, in the semiconductor device 60 of FIGS. 3A and 3B of this embodiment, the impurity concentration of the p-conduction type impurity diffusion region 70 that is the base 63B of the npn transistor 63 constituting the IIL element 61 is The pinch region has a high density and low density repetitive pattern distribution. In other words, in the pinch region of the npn transistor 63, as shown in FIG. 3B, there is a region 63Bt having a low impurity concentration made of a repetitive pattern. Therefore, substantially the same effect as when the impurity concentration of the base 63B of the npn transistor 63 is lowered can be obtained, and the reverse current gain β _up of the npn transistor 63 can be increased. Therefore, as shown in Equation 1, the effective driving capability D _eff of the IIL element 61 can be increased, and the necessary effective driving capability D _eff can be ensured.

FIG. 4 shows the results of evaluating the effective drive capability D _eff and the withstand voltage V _ceo by changing the line and space widths W _L & W _S of the ion implantation mask M70 in FIG. As shown in the result of FIG. 4, the effective driving capability D _eff increases as the line and space width W _L & W _S increases. In the range where the evaluated W _L & W _S is 0.8 μm or more, the effective drive capability D _eff has the above value. On the other hand, the breakdown voltage _{V ceo} is, line-and-space width _W L & _{W S} is reduced as increases. As shown by the outlined arrow in FIG. _4, in the W L & _{W S} is the range of 1.0 .mu.m, it can be secured breakdown voltage _V ceo 1.9V or more necessary IIL element 61. Incidentally, in the evaluation of Figure 4 has been set the line width W _L and space width W _S to the same value, the line width W _L and space width W _S can independently set to any value, which Thus, a repetitive pattern distribution with a desired impurity concentration can be obtained.

In the semiconductor device 60 of FIG. 3A having a low impurity concentration region 63Bt having a repetitive pattern in the pinch region of the npn transistor 63, the reverse current amplification of the npn transistor 63 is achieved by substantially reducing the impurity concentration of the base 63B. The rate β _up is increased, thereby ensuring the effective driving capability D _eff of the IIL element 61. Therefore, it is not necessary to reduce the number of collectors 61Ca to 61Cc arranged on the base 61B of the IIL element 61. Therefore, the semiconductor device 60 illustrated in FIG. 3A can be a small semiconductor device that does not reduce the degree of freedom in logic circuit design.

  In the semiconductor device 60 shown in FIG. 3A, when the high breakdown voltage bipolar transistor (not shown) is an npn transistor, the cost of the semiconductor device 60 can be reduced as follows. That is, when the high breakdown voltage bipolar transistor is an npn transistor and the base is a p-conductivity type impurity diffusion region formed in the surface layer portion of the epitaxial layer 42 similar to FIG. 3A, the npn transistor 63 in the IIL element 61. In the base region, an ion implantation mask M70 having a repetitive pattern is arranged, and the base of the high breakdown voltage bipolar transistor and the base of the npn transistor in the IIL element are simultaneously formed by the same ion implantation process. In this case, since the ion implantation process of the base of the high breakdown voltage bipolar transistor (not shown) is shared with the IIL element 61, the manufacturing cost can be reduced and the inexpensive semiconductor device 60 can be obtained.

In the semiconductor device of the present invention in the first embodiment, (a) is a perspective view showing one IIL element constituting the semiconductor device cut in half in the Y direction. (B) is the top view which expanded and showed the A section enclosed with the dashed-dotted line of (a). It is the result of changing the width W _b in FIG. 1B and evaluating the effective driving ability D _eff . In the semiconductor device of the present invention in the second embodiment, (a) is a perspective view showing one IIL element constituting the semiconductor device cut in half in the Y direction. (B) is sectional drawing which expanded and showed the B section enclosed with the dashed-dotted line of (a). This is a result of evaluating the effective drive capability D _eff and the withstand voltage V _ceo by changing the line and space widths W _L & W _S of the ion implantation mask in FIG. It is a figure which shows the equivalent circuit of an IIL element. It is a top view at the time of comprising the IIL element shown in FIG. 5 on a semiconductor substrate. FIG. 2A is a plan view showing a part of a semiconductor device in a conventional semiconductor device. (B) is a typical sectional view showing an XX 'section in (a).

Explanation of symbols

10, 30, 60 Semiconductor device 1, 11-13, 31, 61 IIL element 2, 32, 62 (horizontal) pnp transistor 3, 33, 63 (vertical) npn transistor 16, 40 Silicon (Si) substrate 17 , 41 Embedded diffusion layer 18, 42 Epitaxial layer 43, 44, 70 p-conduction type impurity diffusion region 45 n-conduction type impurity diffusion region 22, 50 n + diffusion region (high-concentration n-type region)
50t n + diffusion region protruding portion 63Bt Low impurity concentration region M70 Ion implantation mask

Claims (5)

A semiconductor device in which a plurality of IIL elements are formed on a semiconductor substrate,
The IIL element is
The collector of the horizontal pnp transistor and the base of the vertical npn transistor are connected,
The base of the pnp transistor and the emitter of the npn transistor are grounded;
The semiconductor substrate is
A buried diffusion layer containing a high concentration of n-conductivity type impurities;
An epitaxial layer formed on the buried diffusion layer and containing a low-concentration n-conductivity type impurity;
The pnp transistor is based on the epitaxial layer, and two p-conductivity type impurity diffusion regions formed separately from the surface layer portion of the epitaxial layer as an emitter and a collector,
The npn transistor has a p conductivity type impurity diffusion region as a collector of the pnp transistor as a base, the epitaxial layer as an emitter, and an n conductivity type impurity formed in a surface layer portion of the p conductivity type impurity diffusion region as the base. Using the diffusion region as a collector,
Wherein in the substrate surface of the semiconductor substrate, I IL element p conductivity type impurity diffusion region is a collector of the pnp transistor in between the p-conductivity type impurity diffusion region serving as an emitter is placed in the pnp transistor is more structure made are made by,
Each of the plurality of IIL elements is surrounded by an n + diffusion region containing high-concentration n-conductivity type impurities reaching the buried diffusion layer from the surface of the semiconductor substrate within the substrate surface of the semiconductor substrate,
The semiconductor substrate substrate surface of a semiconductor device, characterized in that the base region between the emitter and the collector of the pnp transistor of said IIL device其s, comprising the n + and diffusion region is protruded. A bipolar transistor is formed at a position different from the IIL element on the semiconductor substrate;
The bipolar transistor is an npn transistor;
A base of the bipolar transistor is a p-conductivity type impurity diffusion region formed in a surface layer portion of the epitaxial layer;
The semiconductor device according to claim 1, wherein the base of the bipolar transistor and the base of the npn transistor in the IIL element are formed with the same impurity concentration. A semiconductor device in which a plurality of IIL elements are formed on a semiconductor substrate,
The IIL element is
The collector of the horizontal pnp transistor and the base of the vertical npn transistor are connected,
The base of the pnp transistor and the emitter of the npn transistor are grounded;
The semiconductor substrate is
A buried diffusion layer containing a high concentration of n-conductivity type impurities;
An epitaxial layer formed on the buried diffusion layer and containing a low-concentration n-conductivity type impurity;
The pnp transistor is based on the epitaxial layer, and two p-conductivity type impurity diffusion regions formed separately from the surface layer portion of the epitaxial layer as an emitter and a collector,
The npn transistor has a p conductivity type impurity diffusion region as a collector of the pnp transistor as a base, the epitaxial layer as an emitter, and an n conductivity type impurity formed in a surface layer portion of the p conductivity type impurity diffusion region as a base. Using the diffusion region as a collector,
Wherein in the substrate surface of the semiconductor substrate, I IL element p conductivity type impurity diffusion region is a collector of the pnp transistor in between the p-conductivity type impurity diffusion region serving as an emitter is placed in the pnp transistor is more structure made are made by,
Each of the plurality of IIL elements is surrounded by an n + diffusion region containing high-concentration n-conductivity type impurities reaching the buried diffusion layer from the surface of the semiconductor substrate within the substrate surface of the semiconductor substrate,
其s Oite said IIL device, the impurity concentration of the p conductivity type impurity diffusion region is a base of the npn transistor, in the substrate plane sandwiched emitter and collector of the npn transistor, high concentration and low concentration A semiconductor device having a repeated pattern distribution.   The semiconductor device according to claim 3, wherein the repetitive pattern distribution is a stripe shape.   The semiconductor device according to claim 3, wherein the repetitive pattern distribution has a lattice shape.