JP2723935B2 - Memory expansion device for electronic equipment - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a memory expansion device for electronic equipment.

2. Description of the Related Art As shown in FIG. 2, there is a memory expansion device in which a plurality of memory boards 102, 103, 104 having different memory capacities are selectively connected to a connector 101 formed on a motherboard 100 of an electronic device.

Problems to be Solved by the Invention Conventionally, the memory capacity is increased by additionally inserting a memory board prepared by the manufacturer, but if the memory capacity is to be further increased at a later date, the memory board is inserted beforehand. And a new memory board.

Means for Solving the Problems An electronic device is provided with a main body connector having a number of signal line terminals, a plurality of board designation terminals connected to the board designation means, and a board selection signal terminal to which a selection signal is supplied. A plurality of memory boards each having a memory, a first connector having a signal line terminal connected to the main body connector, a board designation terminal, and a board selection signal terminal connected to the memory boards; and the same connection portion as the main body connector A second connector provided with a board designating signal path line between the first connector and the second connector and a signal path line connected to the memory formed by a resistor sequentially connected in series. And a board identification means for generating an identification signal of the memory board.
Detecting means connected to the memory having a signal discriminating unit for discriminating a signal between the board identifying means and the board specifying signal path line for each board specifying signal line is provided.

The memory board connected to the electronic device by the connection between the main body connector and the first connector can be sequentially connected to another memory board by the connection between the first connector and the second connector. A plurality of memory boards can be connected to the electronic circuit of the electronic device at one time. Also, by identifying each memory board by board identification means formed by resistors connected in series, and by designating a desired memory board by board designation means, the outputs of the board designation means and board identification means are output. The memory of the memory board selected and detected by the detecting means can be enabled.

Embodiment An embodiment of the present invention will be described with reference to FIG. Reference numeral 1 denotes a motherboard that forms a part of an electronic device, and the motherboard 1 is provided with a main body connector 2. 3 to 6
Is a memory board having memories 7 having different memory capacities. These memory boards 3 to 6 are provided with a first connector 8 and a second connector 9. Then, the motherboard 1 has a low active signal ▲
Board designation means 15 for outputting ▼, ▲ ▼, ▲ ▼, ▲ ▼ from the board designation terminals 11, 12, 13, 14;
A signal supply unit 18 having a ground unit 16 and a power supply unit 17 is provided. Further, the main body connector 2 has a plurality of signal line terminals 10, the board designation terminals 11 to 14, a board selection signal terminal 19 connected to the grounding section 16 to output an L signal, and a connection to the power supply section 17. And the selected board selection signal terminals 20.

Next, the first connector 8 of each of the memory boards 3 to 6 has a signal line terminal 10 connected to the signal line terminal 10 of the main body connector 2 and the board designation terminal 1.
Board designation terminals 23,2 connected to each of 1,12,13,14
4, 25, 26, and board selection signal terminals 27, 28 connected to the board selection signal terminals 19, 20 are arranged. The second connector 9 has a signal line terminal 10, board setting terminals 11 to 14, and board selection signal terminals 19 and 20, similarly to the main connector 2.

Next, each of the memory boards 3 to 6 is provided with a board identification unit 53. The board identification means 53 connects the resistors 54 of the memory boards 3 to 6 connected to the board selection signal terminals 20 and 28 arranged in the first and second connectors 8 and 9 in series. Power supply unit 17 in 3 to 6
Is used to identify each of the memory boards 3 to 6 based on a change in the supply voltage from the memory board. That is, the voltage detection unit 55 is provided between the board selection signal terminal 28 of the first connector 8 and the resistor 54.
Is connected. The voltage detector 55 determines the output of the A / D converter and the output of the A / D converter, and determines the output lines a, b,
The signal of L is output from any of c and d.

Further, each of the memory boards 3 to 6 has a plurality of board designation paths in which each of the board designation terminals 23 to 26 of the first connector 8 and each of the board designation terminals 11 to 14 of the second connector 9 are connected. Lines e to h and signal path lines in which the signal line terminals 10 of the first and second connectors 8 and 9 are connected are provided. A detection means 32 is provided for inputting each of the board designation path lines e to h and the output of the board identification means 53 for each line.
Further, the detecting means 32 includes the board designating pass line e,
f, g, h and negative logic AND circuits 33, 34, 35, 36, which are a plurality of signal discriminating units for inputting the output of each of the lines a, b, c, d of the board discriminating means 53, It comprises an OR circuit 37 of negative logic which inputs the outputs of the AND circuits 33, 34, 35, 36. That is, the input side of the AND circuit 33 is connected to the board signal input terminal 23 and the line a of the voltage detection unit 55, and the input side of the AND circuit 34 is connected to the board designation terminal 24 and the line b of the voltage detection unit 55. The input side of the AND circuit 35 is connected to the board designation terminal 25 and the line c of the voltage detection unit 55, and the input side of the AND circuit 36 is connected to the board designation terminal 26 and the line d of the voltage detection unit 55. The output side of the OR circuit 37 is connected to the memory 7. The memory 7 includes the signal path lines i to n.
It is connected to the.

In such a configuration, in a state where the memory boards 3, 4, 5, and 6 are sequentially connected to the motherboard 1 and the board selection signal terminals 19 and 20 of the second connector 9 of the last memory board 6 are connected, Three to six resistors 54 are connected in series and connected to the power supply unit 17. Therefore, the signal supply unit 18
From the power supply section 17 of each of the memory boards 3, 4, 5, and 6
, The voltage detection unit 55 of the first memory board 3 outputs an L signal from the first output line a. Voltage detector 55 of second memory board 4
Outputs an L signal from the second output line b. The voltage detection unit 55 of the third memory board 5 outputs an L signal from the third output line c. The voltage detection unit 55 of the fourth memory board 6 outputs an L signal from the fourth output line d.

In this state, one of the memory boards 3 to 6 to be used is designated by the board designating means 15. That is, when the low active signal ▲ ▼ is output, the memory board 3
Since the LL signal is input to the first AND circuit 33, the detecting means 32 outputs L to enable the memory 7. When the low active signal ▲ ▼ is output,
The detecting means 32 of the memory board 4 is the second AND circuit
Since the LL signal is input to 34, L is output and the memory 7 is enabled. Low active signal ▲ ▼
Is output, the detection means 32 of the memory board 5 outputs L since the LL signal is input to the third AND circuit 35, thereby enabling the memory 7. When the low active signal ▲ is output, the detecting means 32 of the memory board 6 outputs L since the LL signal is inputted to the fourth AND circuit 36, and makes the memory 7 enabled.

Accordingly, by specifying the output line of the board designating means 15 to be set to the low active state, the detecting means 32 of the designated memory boards 3 to 6 outputs an enable signal to the memory 7. Therefore, when the memory capacity is insufficient, the memory boards may be sequentially inserted as necessary regardless of the presence or absence of the memory boards on the motherboard 1. 4,5,6 can be specified.

As described above, the present invention relates to a main body connector having a number of signal line terminals, a plurality of board designation terminals connected to a board designation means, and a board selection signal terminal to which a selection signal is supplied. A plurality of memory boards each having a memory, a first connector having a signal line terminal connected to the main body connector, a board designation terminal, and a board selection signal terminal on these memory boards, and the main body connector A second connector provided with the same connection portion as described above, between the first connector and the second connector are sequentially connected in series with a board designated signal path line and a signal path line connected to the memory. And a board identification means for generating an identification signal for the memory board. A signal discriminating unit for discriminating a signal with a signal path line for each of the board designating signal lines, and a detection unit connected to the memory is provided, so that the electronic device is connected to the main body connector and the first connector. Another memory board can be sequentially connected to the connected memory board by connecting the first connector and the second connector, thereby connecting a plurality of memory boards to the electronic circuit of the electronic device at one time. be able to. Also, by identifying each memory board by board identification means formed by resistors connected in series, and by designating a desired memory board by board designation means, the outputs of the board designation means and board identification means are output. The memory of the memory board selected and detected by the detecting means can be enabled;
Therefore, when the memory capacity is insufficient, the memory boards can be sequentially inserted as necessary regardless of the presence or absence of the memory boards in the electronic device. This has the effect that can be specified.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a plan view showing a conventional connection state between a motherboard and a memory board. 2 ... connector, 3-6 ... memory board, 7 ... memory, 8 ... first connector, 9 ... second connector, 10
…… Signal line terminals, 11-14 …… Board designation terminals, 15…
… Board designation means, 19-20 …… Board selection signal terminal, 23
26 to board designation terminal 27 to 28 board selection signal terminal 32 detection means 33 to 36 signal discriminating section 53 board identification means 54 resistance e to h Board designation path line, i to n ... Signal path line

Claims (1)

(57) [Claims] An electronic apparatus includes a main body connector having a plurality of signal line terminals, a plurality of board specification terminals connected to a board specification means, and a board selection signal terminal to which a selection signal is supplied. A plurality of memory boards having a first connector having a signal line terminal connected to the main body connector, a board designation terminal, and a board selection signal terminal, and the same connection portion as the main body connector. And a second connector,
A board designation signal path line between the first connector and the second connector and a signal path line connected to the memory sequentially formed of a resistor connected in series to generate an identification signal of the memory board. A board discriminating means, a signal discriminating section for discriminating a signal between the board discriminating means and the board designating signal path line for each board designating signal line, and a detecting means connected to the memory. A memory expansion device for electronic equipment, characterized in that: