JP2724066B2 - Associative memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an associative memory device, and more particularly, to a CAM (Content Addressable Memory) comprising a cell having a new structure based on a nonvolatile memory element.
y: content access memory), ie, associative memory device.

[0002]

2. Description of the Related Art Conventionally, an associative memory, that is, a fully parallel CAM (CAM) has been used as a semiconductor memory circuit having a function of detecting the coincidence of search data and stored data in parallel with all bits and outputting a storage address or data of the matched data. Content Accessable Memory is well known (edited by Takuo Sugano, Tetsuya Iizuka, "CMO
S Ultra LSI Design, "Baifukan, p. 176-p. 177).

However, a configuration example per bit of a conventional CAM is composed of an SRAM cell and an exclusive NOR circuit, and it is impossible to configure a CAM having a large cell size and a practical level of capacity. Met.

[0004] In recent years, as personal databases that have been commercialized in large numbers, IC cards and the like use the above-mentioned CA.
Not the configuration of M, but the RO
M (read only memory) data is sequentially searched one by one to search for desired data. For this reason, as the amount of data increases, such as a Japanese dictionary or English-Japanese dictionary, more time is required for search, and there is no one having a high-speed and flexible search function yet.

[0005] Considering the above conventional technology, the search for data stored in a conventional ROM or the like is performed by software.
Rather than being performed sequentially on each piece of data, C
If it becomes possible to search all data at once like AM, it will be possible to make data search of an IC card or the like equipped with a large-capacity memory in the future faster and more flexible.

For this reason, US Pat. No. 3,701,980 (US Pat. No. 3,701,980, Oct. 1972) or Japanese Unexamined Patent Publication No.
And the invention described in JP-A-194196. First, the former U.S. Pat.
It has a CAM cell structure with one set of bit memory. The latter is based on EPROM non-volatile memory.
A CAM is configured as a set. Therefore, any of them can achieve higher integration than the SRAM-based CAM.

[0007]

By the way, the DRAM-based one disclosed in U.S. Pat. No. 3,701,980 still has a problem in area. On the other hand, Japanese Patent Application Laid-Open
The EPROM nonvolatile memory-based memory disclosed in Japanese Unexamined Patent Application Publication No.
There is a problem that the PROM memory is used and the common ground line is merely used as the match search line, but the details of the operation at the time of the match search are not sufficiently considered, and flexible writing and reading cannot be performed.

SUMMARY OF THE INVENTION In view of the above, the present invention allows a large number of memory cells to be searched at high speed without mutual interference, thereby enabling a faster and larger-capacity database to be constructed. The purpose is to provide.

[0009]

Means for Solving the Problems To achieve the above object, the present inventor has conducted extensive studies on an associative memory using a non-volatile memory as a set of 2 bits. It was found that there was a point.

That is, (1) Japanese Patent Application Laid-Open No. 1-1941
In the CAM structure disclosed in Japanese Patent Application Laid-Open No. 96-96, when a match cell and a non-match cell are mixed at the time of a match search, the potential of the low “0” data and the potential of the high “1” data are changed via the shared match search line. Collision occurs and operation cannot be guaranteed.

In addition, (2) the higher the degree of integration, the more the number of memory cells becomes enormous, and a large number of coincident cells and unmatched cells exist. I will.

The present inventors have reached the present invention based on the above findings. That is, the present invention provides a first nonvolatile memory cell that defines an electrical connection or disconnection from a first data line to a match search line, and a second nonvolatile memory cell that defines an electrical connection from the second data line to the match search line. An associative memory device in which a second nonvolatile memory cell defining electrical connection or non-connection and a control word line for controlling the first and second nonvolatile memory cells are a set of search memory word blocks. Wherein the voltage of each signal line and the threshold voltage of the nonvolatile memory cell at the time of data retrieval are adjusted so as to simultaneously satisfy the following expressions (I) and (II). An apparatus is provided. _{V W -V H <V tL <} V W -V L <V tH (I) V W -V S <V tL (II) , however, V _tL: low threshold voltage V _tH of the nonvolatile memory cells: High threshold voltage of the nonvolatile memory cell V _W : voltage of the control word line V _H : voltage indicating “1” data of the data line _VL : voltage V _S indicating “0” data of the data line : Voltage of the match search line at the time of the data search .

Here, it is preferable that the nonvolatile memory cell is constituted by a nonvolatile transistor having a threshold voltage satisfying the above formulas (I) and (II). The above-mentioned associative memory device, further comprising:
It is preferable to have means for setting the voltage at the time of data search so as to simultaneously satisfy the above expressions (I) and (II).

[0014]

The associative memory device of the present invention defines first and second electric connections or disconnections between the first and second data lines and the coincidence search lines in a set of search memory word blocks. Are controlled by a control word line. On the other hand, a voltage applied to signal lines such as the first and second data lines, the match search line, and the control word line, and a low threshold voltage of the first and second nonvolatile memory cells Is adjusted so as to satisfy the above expressions (I) and (II). Therefore, even when a large number of search memory word blocks are connected to one control word line, the search data added from the first and second data lines and the memory data of the search memory word block are In the blocks in which the first and second nonvolatile memory cells are connected, the first and second nonvolatile memory cells are controlled irrespective of the connection definition state of the first and second nonvolatile memory cells.
None of the data lines is connected to the match search line, and only the blocks where the search data and the memory data do not match are connected by the control word line to the first and second nonvolatile memory cells. According to the definition state, the first data line and the second data line can be connected or disconnected from the match search line, respectively.

The potential of the match search line is detected by a sense amplifier connected to the match search line, so that the first data of each block based on search data applied to the first and second data lines. And a match search result with the second nonvolatile memory cell can be obtained. Therefore,
Even if a search memory word block that does not match the search data and a search memory word block that matches both exist in a large number of sets of search memory word blocks controlled by the same control word line, the search memory Can be eliminated, a match search result can be obtained with extremely high accuracy, and an extremely high degree of freedom in selecting a memory cell can be obtained.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an associative memory device according to the present invention will be described in detail with reference to the preferred embodiments shown in the accompanying drawings.

First, before describing the present invention, it should be noted that the same problems as those occurring in a conventional CAM structure using a nonvolatile memory exist when a nonvolatile memory cell is applied to a highly integrated CAM. The description will be made using the newly considered 2-bit CAM Flash EEPROM memory structure of a set of two bits shown in FIG. 3, a new idea is added, and the main point of the present invention is clarified.

In FIG. 1, a memory pair 31 having one set of memory cells 31a and 31b and a memory pair 32 having one set of memory cells 32a and 32b are each one CAM cell. The structure described in this example is called a stack cell structure, in which a control gate 34 is stacked immediately above a floating gate 33 for storing electric charges, and has a structure suitable for high integration. .

FIG. 4 shows the variation of the threshold voltage Vt depending on the charge accumulation state of the floating gate 33 of each memory cell. The low threshold voltage V _tL of the memory cell having the normal stack structure is about 0.5 to 3.5 V, and has a variation of about 3 V. However, in the case of a CAM structure, this variation is fatal. This is one of the issues, and the following description is continued.

Electrons are injected into the floating gate 33 of the memory cell 31a, and a high threshold voltage V _tH (defined as data “0” L (low)) is applied to the memory cell 3a.
1b is the inverted low threshold voltage _VtL (this is defined as data "1" H (high)), the memory cell 32a has the low threshold voltage _VtL , and the memory cell 32b has the high threshold voltage. The voltage V _tH is defined. That is, it is assumed that "0" L (low) data is defined in the CAM cell constituted by the memory pair 31 and "1" H (high) data is defined in the CAM of the memory pair 32. In this state, "0" L (low) of the match search data 39 is stored in each CAM cell,
Consider a case in which “0” L (row) is detected as coincident.

First, the ground transistor 38 is turned off,
The match search sense amplifier 37 is activated. The match search amplifier 37 is a current drive type amplifier and has its own drive capability. Therefore, the match search line 36 is composed of:
The potential is set to about 5 to 2.0 V. This set potential is desirably a small value so as not to affect the charge stored in the floating gate 33, and it is generally considered that 2V or less is good.

Here, as a general CAM operation, the charge on the match search line precharged to a high potential
It is discharged by the "0" L (low) of the data line of the AM cell and changes to a low potential. A match search line that has caused this change indicates a mismatch, and a match search line that maintains a high potential without a potential change indicates a match. In this example, the data “1” H (high) of the CAM cell of the memory pair 32 and the search data “0” L (low) are different, and the match search line 36 is connected by the data line 2 a (“0” L (low)). Discharge occurs and becomes low potential.

As a specific search operation, the data line 1a
0V of the "0" L (low) potential of the match search data is applied, and the opposite "1" H (high) potential of 1.5 to 2.0 V is applied to the data line 1b. Similarly, the data line 2a is supplied with 0V of the "0" L (low) potential of the match search data.
, And the opposite "1" H (high) potential of 1.5 to 2.0 V is applied to the data line 2b. At this time,
For the above reason, the potential in the high state is set as low as about 1.5 to 2.0V.

In this state, when the select word line 35 becomes active, the threshold voltage Vt becomes V _tH (> 6.5).
V: see FIG. 4), the memory cells 31a and 32b remain off. However, the memory cells 31b and 32a
In the case of, a different operation is performed.

First, attention is paid to the memory cell 32a. This memory cell 32a must be turned on in order to detect the mismatch by extracting the charge from the match search line 36. However, the threshold voltage Vt of this transistor
Takes a value of 0.5 to 3.5 V (see FIG. 4). Also,
At this time, the source electrode side becomes the data line 2a, and 0 V is applied. Therefore, the voltage _{V W} for selective word line 35 must be 3.5V or more, usually deemed appropriate than about 1V higher 4.5V about it.

That is, the voltage V _W of the select word line 35
Only when ≧ 4.5 V, the potential of the match search line 36 is dropped by the 0 V potential of the data line 2a. On the other hand, the match search sense amplifier 37 is a current drive type and has a drive capability. Therefore, the potential of the match search line 36 finally drops to about 1.0 to 1.5 V, and a mismatch is detected by the voltage drop of about 0.5 V. Of course, a mismatch is detected based on this potential drop, and the memory cell 31 of the CAM cell storing the match data is thereby detected.
Inconvenience will occur in b.

Considering the potential of each of the three electrodes (drain, gate, source) of the memory cell 31b, first, the gate is at least 4.5 V of the select word line 35, and the source is 1. 0 to 1.5 V, and the drain is 1.5 to 2.0 V of the data line. That is,
The gate-source potential difference V _GS of this transistor is 3.
0 to 3.5 (4.5 (1.0 to 1.5)) V or more.

By the way the threshold voltage V _t of the memory cell 31b is the lowest 0.5V (see FIG. 4). That is, V _GS (= 3.0 to 3.5)> V _t (= 0.5), and the memory cell 3 due to the substrate bias effect at this time is obtained.
Even if the rise of the threshold voltage of 1b is considered, the transistor of the memory cell 31b is turned on. For this reason,
A through current flows from the high potential of the data line 1b to the low potential of the data line 2a.

Generally, in the case of an associative memory, a match search operation is performed simultaneously over a plurality of select word lines. Therefore, the through current in each select word line becomes an extremely large value in the entire chip, which is a fatal problem that operation is impossible. Further, the potential of the data match search line 35 rises due to the high potential of the data line 1b, which causes a problem that it becomes difficult to detect the potential difference by the match search sense amplifier 37.

Based on such new considerations, the associative memory device according to the present invention will be specifically described with reference to the accompanying drawings. FIG. 1 shows an embodiment of the content addressable memory device according to the present invention. The CAM memory shown in FIG. 1 has a 2-bit EE set, which is a constituent unit of the CAM, as described above.
It is constituted by PROM memory cells. CAM
The memory cell 11 is, for example, a stack type FlashEEP.
It is composed of ROM cells 11a and 11b, and the EEPROM cells 11a and 11b are written so as to have mutually opposite storage states. Here, the EEPROM cell 1
Data "0" L (low) is written in 1a and data "1" H (high) is written in 11b.
It is assumed that data “1” H (high) is written in a, and data “0” L (low) is written in 12b. These E
EPROM memory cells 11a, 11b and memory cell 12
a and 12b each form a memory pair and have a 2-bit CA
M memory cells 11 and 12 are obtained.

The EEPROM memory cells 11a, 11b,
Each of the memory cells 12a and 12b includes an EEPROM memory cell 20 having a specific structure as shown in FIG. EEPR
The OM memory cell 20 includes an n source 22 on a P substrate 21,
A drain 23 is formed, a tunnel oxide film 24 is formed on a P substrate 21 therebetween, a floating gate 25 is formed thereon, and a control gate 26 is formed thereon. Writing is performed by applying a high voltage pulse 27 to the control gate 26 so that the floating gate 2
Performs injection of hot electrons into 5, defining the data state of "0" L (low) by raising the threshold voltage V _t to V _W or more predetermined voltages. Also,
Writing "1" H (high) is performed by extracting electrons from the floating gate to the source 22 or drain 23 side. In the present application, data “0” L
The threshold voltage of the EEPROM memory cell in which (low) is written is a high threshold voltage V _tH , and the threshold voltage of the EEPROM memory cell in which data “1” H (high) is written is a low threshold voltage V _tL is assumed.

Therefore, the symbol "H" written on the floating gate 13 of the EEPROM cells 11a and 12b in FIG. 1 indicates that electrons have been injected, and the transistors of these cells have a high threshold voltage V _tH . Indicates that data “0” L (row) is stored. on the other hand,
The symbol "L" written in the floating gates 13 of the EEPROM cells 11b and 12a indicates that electrons have been extracted, the transistors of these cells have a low threshold voltage _VtL , and the data "1" H ( High) is stored.

In the CAM memory cell 11, the EEPR
The drain of the OM memory cell 11a is connected to the data line (bit line) 1a, the drain of the EEPROM memory cell 11b is connected to the data line (bit bar line) 1b, and the control gates 14 of both memory cells 11a and 11b are connected to the same select word line. 15 and both memory cells 11a,
The source of 11 b is connected to the match search line 16. CAM
As for the memory cell 12, the data contents of the EEPROM memory cells 12a and 12b and the connection of the drains of both memory cells 12a and 12b are connected to the data line 2 respectively.
a and the data line 2b are exactly the same. Further, the match search line 16 is provided with a match search sense amplifier 17 including a precharge transistor 17a and a ground transistor 18. A plurality of such CAM memory cells are arranged so that the match search line 16 and the select word line 15 are shared.

First, the data read operation of the CAM memory cell will be briefly described. The normal read operation is performed using the selection circuit 5 and the sense amplifier 6 provided at the ends of the data lines 1a, 1b, 2a, 2b. The selection circuit 5 connects, for example, the sense amplifier 6 to the data line 1b. This amplifier is of a current detection type, and the data line 1b is kept at, for example, 1.5 to 2.0 V during non-reading. Next, when V _W , for example, 5 V, is applied to the select word line 15, the memory cell 11b between the data line 1b and the match search line 16 is turned on because V _w > V _tL is set. On the other hand, at this time, the match search line 16 is fixed to the ground potential by the ground transistor 18, so that the potential of the data line 1b drops to about 1.0 to 1.5V. This change is detected by the sense amplifier 6, and the result is output.

On the other hand, the sense amplifier 6 is connected to the data line 1a by the selection circuit 5, and the data line is similarly maintained at 1.5 to 2.0V. Next, a voltage of V _W (5 V) is similarly applied to the word line 15, but the data line 1a
The EEPROM memory cell 11a between and the match search line has a high threshold voltage V _tH and is not turned on because V _W <V _tH is set. Therefore, the potential of the data line 1a does not change. This is detected by the sense amplifier 6, and the result is output. Thus, the reading of the data stored in each memory cell is performed. Here, the data lines 1a,
The reason why the potential of 1b is set to 2 V or less is to suppress the influence of the charge stored in the memory cell when data is read.

Next, a description will be given below of the fact that the CAM memory having the above-described configuration can be searched for a match with the input data without causing the above-described problems such as potential interference between memory cells. I do.

In the present invention, the voltage V _W applied to the select word line at the time of a match search, the voltage V _L applied to the data line to which data “0” L (row) is input, and the data “1” H
(High) applied voltage V _H of the data line to which data is input, applied voltage V _S of the match search line, and low threshold voltage of the EEPROM cell storing the data “1” of the 2-bit set CAM memory The relationship with V _tL is adjusted so as to satisfy the following expression. _{V W -V H <V tL <} V W -V L (I) V W -V S <V tL (II) of course, conventionally, stores data "0" of 2 bits set of CAM memory It goes without saying that the EEPROM cell has a high threshold voltage V _tH and is set so as not to be turned on even when the applied voltage V _W to the select word line is applied (in a high state). That is,
It is set here as _{V tH> V W -V L>} V W -V H and _{V tH> V W -V S (} III) as.

Next, the coincidence detecting operation will be described. First, data is written into the memory cells 11a, 11b, 12a, and 12b as one memory pair of two cells. This set does not necessarily have to be adjacent memory cells, but in this example, contradictory data is written in adjacent cells for ease of explanation.

CAM cell 1 composed of a memory pair
1 is "0" L (low), CAM cell 1 which is a memory pair
2 is "1" H (high). The match search data 19 is
"0" is set for each of these CAM memory cells 11 and 12.
L (low), "0" L (low) is detected.
Therefore, the data of the CAM cells of the memory pair 11 match the search data, but the data of the CAM cells of the memory pair 12 do not match.

First, "0" L (low) is applied to the data line 1a.
A voltage _VL (normally OV), a "1" H (high) voltage _VH is applied to the data line 1b, and a "0" L is applied to the data line 2a.
(Low) voltage V _L , “1” H (high) on data line 2 b
Voltage V _H is applied. The ground transistor 18 is off, and the match search line 16 is the precharge transistor 17
"a" is set to the "1" H (high) state. Here, the voltage of the match search line 16 is represented as V _S.

In this state, the select word line 15 becomes "1".
When the voltage becomes H (high), the voltage V _W is applied, and the memory pair 1
Each of the memory cells 11a, 11b,
"1" H is applied to the control gates 14a and 12b.
The (high) voltage V _W is applied.

In the memory cells 11a and 11b, electrons are injected into the floating gate 13, and the high threshold voltage V _tH which does not turn on at the H (high) voltage V _W of the select word line as shown in the above formula (III) is applied. And maintain the off state in the same manner as the above-described data reading (this is done by using an EEPROM memory cell with V _tH > 6.5 V as shown in FIG. 4 and V _W = 5 V, V _H = 1.5 to 2). 0.0 V, V _L = 0
V, V _S = 1.5 to 2.0 V). Therefore, the “0” L (low) state of the data line 1 a and the “1” H (high) state of the data line 2 b match the search line 16.
Does not affect However, the low threshold voltage V
The case of the memory cell 11b and the case of the memory cell 12a having _tL are different. The low threshold value V _tL and the voltage V of each signal line
_W, V _H, V _L, no relationship between V _S becomes important problem to satisfy the above formula (I) and (II).

The details will be described below. First, in the case of the memory cell 12a, the stored data “1” H (high) and the search data “0” L (low) are different. Therefore, data line 2
It is necessary to extract the charge in the “1” H (high) state of the match search line 16 depending on the “0” L (low) state of a.

Here, the potential of the data line is set to V _L (L state), the potential of the match search line 16 is set to V _S (H state), and V _W (H state) is applied to the select word line. Suppose it was done. Then the gates of the memory cell 12a, source potential difference _{V GS} becomes _V W -V _L. That is, V _GS = (H voltage of select word line 15) − (L voltage of data line 2a) = V _W = _VL The threshold voltage Vt of the EEPROM memory cell 12a is the low threshold voltage V _tL .

Here, in the present invention, the above formula (I)
Since it is adjusted so as to satisfy _the, V W -V _L> low threshold voltage _{V tL,} and the memory cell 12a is turned on,
The potential of the match search line 16 precharged by the precharge transistor 17a is lowered. This potential drop is detected by the match search sense amplifier 17, and a mismatch signal is output.

On the other hand, in order to prevent potential interference between the memory cells of the memory pair connected to the same select word line, in the case of the memory pair 11, the stored data "0" L (low) and the search data "0" L (row) matches, the memory cell 11b must be kept off, and the data line 1b and the match search line 16 must be kept disconnected.

Here, the gate and drain of the memory cell 11b are
IN potential difference V_GDIs V_W-V_HAnd gate and source voltage
Difference V_GSIs V_W-V_SBecomes That is, V_GD= (H voltage of select word line 15) − (H voltage of data line 1b) = V_W-V_H  V_GS= (H voltage of select word line 15) − (voltage of match search line) = V_W-V_S On the other hand, the threshold voltage of this EEPROM memory cell 11b is
The voltage Vt is equal to the low threshold voltage V_tLIt is. In the present invention
In order to satisfy the above formulas (I) and (II),
V_GD= V_W-V_H<V_tLAnd V
_GS= V_W-V_S<V_tLTherefore, the EEPROM memory
The molycell 11b does not turn on. Therefore, the data line 1b and
The match search line 1b remains disconnected.

That is, the voltages V _W , V _H , V _L , V _S and EEPR of the signal lines (word line 15, data lines 1a, 1b, 2a, 2b and match search line 16) during the match search operation.
Since the relationship between the threshold voltages of the OM memory cells 11a, 11b, 12a, and 12b, particularly the low threshold voltage V _tL of the cells 11b and 12a is adjusted, the memory cells 12a
Only one can be turned on and the memory cell 11b can be turned off. As a result, a through current from the “1” H (high) potential V _H of the data line 1 b to the “0” L (low) potential V _{L of the} data line 2 a can be prevented or controlled.

Therefore, even if a large number of CAM cells 11, 12,... Controlled by the same select word line 15 include a cell in which the search data does not match the storage data and a cell in which the search data does not match, Since both of the EEPROM memory cells are not turned on and only one of the mismatched cells is turned on, the potential of the match search line 16 can be reliably reduced without causing potential interference. The mismatch can be detected by the detection by the sense amplifier 17.

On the other hand, when all the CAM cells 11, 12,... Controlled by the same select word line 15 match the search data and the stored data, all the EEPROM memory cells of all the CAM cells are replaced. Since it does not turn on and the data line and the match search line 16 are not electrically connected, the potential of the match search line 16 does not change from the precharge voltage V _S by the precharge transistor 17a. Therefore, coincidence can be detected by detecting this voltage with the sense amplifier 17.

As described above, it is possible to always perform the match search operation without causing potential interference between the memory cells. This is because the threshold voltage of the conventional memory and the voltage of each signal line are not adjusted. Is not possible with the associative memory. The adjustment of the threshold voltage of the non-volatile memory and the voltage of each signal line is performed by (1) changing the low threshold voltage of the EEPROM according to the above equations (I) and (II) according to the voltage of each signal line. Or (2) if the threshold voltage of the nonvolatile memory to be used, particularly the low threshold voltage, is determined, the voltage of each signal line, especially This can be performed by adjusting or setting the voltages of the control word line, the first and second data lines, and the match search line so as to satisfy the above equations (I) and (II).

The adjustment or setting of the low threshold voltage _VtL of the EEPROM (1) can be performed by the high voltage pulse applying means 27 shown in FIG. For example,
As is conventional, the voltage _V W = 5V control word line, data "0" input data line voltage _{V L,} the input data line voltage _{V H} of the data "1", the voltage of the match line _V S = 1.5 for ~ 2.
When the voltage is set to 0 V, the high threshold voltage of the EEPROM is set to V _tH
> 5V, and the low threshold voltage may be set to 3.0V < _VtL <5V. The threshold voltage Vt is adjusted or set by changing the magnitude of the high voltage pulse applied to the control gate 14 and the number of times of application by the high voltage pulse applying means 27 as in the EEPROM 20 shown in FIG. 13 may be performed by adjusting or setting the amount of hot electrons to be injected, or may be performed by extracting electrons from the floating gate 13, or by adjusting or setting the amount of electrons to be extracted. Good.

When adjusting or setting the voltage of each signal line in the above (2), as shown in FIG. 1, the voltage _VH and data "1" of the data "1" of the first and second data lines are used. The voltage _{VL of} 0 ″ is changed by each voltage control means 3.
The voltage control means 4 a driving voltage V _W of the control word line 15, the voltage of the match line 16 can be performed by adjusting or setting the precharge transistor 17a. Here, the voltage control means 3 and 4 are not particularly limited, and conventionally known means can be used. For example, when an EEPROM as shown in FIG. 4 is used, that is, when V _tH > 6.5 V and V _tL = 0.5 to 3.5 V, for example, V _W = 4.0 V, V _H = 4.0 V, V _L =
0 V and V _S may be set to 4.0 V. Instead of the dynamic type match search sense amplifier 17 in the illustrated example, a current drive (detection) type sense amplifier similar to the sense amplifier 6 at the time of data reading may be used as the match search sense amplifier. Rather, a current drive type sense amplifier is preferable because it does not have a steady drive current and is easier to adjust or set the potential of the match search line 16 than a dynamic type match search sense amplifier 17 consuming less power.

As described above, the CAM cell in which the EEPROM memory cell is a set of two bits is described as a representative example in the above-described example. However, the present invention is not limited to this, and the normal nonvolatile memory cell ( Mask ROM, EPROM, etc.)
Needless to say, it can also be applied to.

Further, the associative memory device of the present invention uses a match search line and a sense amplifier (S.
A. ), A structure in which a first data line (bit line) and a second data line (bit bar line) are shared (Japanese Patent Application No. 3-232).
073).

Further, although all the NOR type memory cells have been described so far, the present invention can be applied to a NAND type CAM cell (for this NAND type structure, Japanese Patent Application No. 3-239890). See specification).

[0057]

According to the present invention, it is possible to prevent or control a through current between memory cells at the time of a match search in a CAM structure in which a non-volatile memory is a set of 2 bits, thereby performing a match search of a large number of memory cells. It can be performed at high speed without mutual interference. Even if the voltage of each signal line cannot be largely changed, the low threshold voltage of the memory cell is set to a required value, and each of the CAs is different from the conventional memory cell.
By adjusting the voltage of each signal line, it is possible to eliminate the electrical collision between the CAM cells at the time of a match search even if the memory cells constituting the M cell have large variations such as the threshold voltage. And has an extremely high degree of freedom in selecting a memory cell.

Further, by using the CAM as a database memory which has been regarded as important in recent years, a large-capacity database system having an extremely high-speed arbitrary keyword search function can be realized.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an embodiment of an associative memory device according to the present invention.

FIG. 2 shows an E used in the content addressable memory device according to the present invention.
FIG. 3 is a configuration diagram of an embodiment of an EPROM memory cell.

FIG. 3 is a configuration diagram of a stack type memory for explaining an associative memory device according to the present invention.

4 is a distribution diagram of threshold voltages of stacked memory cells used in the content addressable memory device shown in FIG. 3;

[Explanation of symbols]

 1a, 1b, 2a, 2b Data line 3, 4 Voltage control means 5 Selection circuit 6 Sense amplifier 11a, 11b, 12a, 12b EEPROM cell 11, 12 CAM memory cell 13 Floating gate 14 Control gate 15 Select word line 16 Match search line Reference Signs List 17 Match search sense amplifier 17a Precharge transistor 18 Ground transistor 19 Match search data 20 EEPROM memory cell 21 P substrate 22 Source electrode 23 Drain electrode 24 Tunnel oxide film 25 Floating gate 26 Control gate 27 High voltage pulse applying means

Claims (3)

(57) [Claims] 1. A first nonvolatile memory cell defining an electrical connection or disconnection from a first data line to a match search line, and an electrical connection from a second data line to the match search line. And a control word line for controlling the first and second nonvolatile memory cells as a set of search memory word blocks. Wherein the voltage of each signal line and the threshold voltage of the nonvolatile memory cell at the time of data search are adjusted so as to simultaneously satisfy the following expressions (I) and (II). . _{V W -V H <V tL <} V W -V L <V tH (I) V W -V S <V tL (II) , however, V _tL: low threshold voltage V _tH of the nonvolatile memory cells: High threshold voltage of the nonvolatile memory cell V _W : voltage of the control word line V _H : voltage indicating “1” data of the data line _VL : voltage V _S indicating “0” data of the data line : Voltage of the match search line at the time of the data search . 2. The nonvolatile memory cell according to claim 1, wherein
2. The associative memory device according to claim 1, comprising a nonvolatile transistor having a threshold voltage satisfying (II) and (II). 3. The associative memory device according to claim 1, further comprising means for setting the voltage at the time of the data search so as to simultaneously satisfy the expressions (I) and (II). Associative memory device.