JP2728021B2 - Parity check method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention is applied to a computer device. In particular, the present invention relates to a parity check technique in a device in which the data order is switched between the input side and the output side.

[0002]

2. Description of the Related Art FIG. 4 shows a parity check system in a conventional apparatus. FIG. 4 is a diagram showing a conventional in-device parity check method. Conventionally, a parity generation unit 22 that generates a parity bit from a bit on the same time slot of a parallel signal input to the monitored circuit 21 and a parity bit from a bit on the same time slot of the parallel signal output from the monitored circuit 21 Parity generation unit 2 that generates
3 and a parity check unit 24 that compares the parity generated by the parity generation unit 22 and the parity generation unit 23. The parity check unit 24 generates parity bits from bits on the same time slot before and after the monitored circuit 21 and compares By doing so, a parity check was performed.

[0003]

FIG. 5 shows a problem of the conventional example.
This will be described with reference to FIG. FIG. 5 is a diagram illustrating a parity generation method of the output-side parity generation unit 5. FIG. 6 is a diagram showing a data sorting method. In this conventional parity check method in a device, as shown in FIG. 5, a parity bit is generated from the same time slot of a signal.
Even if the signals are rearranged before and after the monitored circuit 21 as in the frame synchronization detection, and the parity bits are generated from the bits on the same time slot of the output signal of the monitored circuit, the parity bits before and after the monitored circuit are not generated. There is a disadvantage that monitoring cannot be performed at a part that may not match.

[0006] As shown in FIG. 6, when the second input data includes the first bit of the frame synchronization pattern F,
The data is rearranged by placing the first of the input data at the end of the output data and the second of the input data at the beginning of the output data. Therefore, even if the parity bit is generated from the bit on the same time slot of the output signal of the monitored circuit 21, it does not match the parity bit before the input of the monitored circuit 21.

As a technique for making the parity bits before input coincide on the output side, Japanese Patent Application Laid-Open No. 2-246445 discloses a technique.
Is disclosed in Japanese Patent Application Laid-Open Publication No. HEI 9-203 (1995). This is so that when the monitored signal passes through the serial / parallel conversion circuit, the parity bit generated before input to the serial / parallel conversion circuit matches after passing through the serial / parallel conversion circuit. A RAM is provided to execute processing of a parity bit corresponding to a serial-parallel conversion circuit in the RAM, and the apparatus is inevitably complicated and expensive.

The present invention has been made in view of such a background, and an object of the present invention is to provide a parity check method capable of correctly performing a parity check even in a device in which the data order is switched between the input side and the output side. And SUMMARY OF THE INVENTION It is an object of the present invention to provide a parity check system having a simple device configuration capable of performing a parity check on all bits of a frame.

[0007]

The present invention SUMMARY OF] is monitored circuit including a serial-parallel converter for converting an input serial signal into parallel signals, and a signal selection unit for force out and rearrange the parallel signals This is a parity check method.

The present invention is characterized in that an input-side parity generation section for generating a parity signal for each of the parallel signals, and an output-side parity generation section for generating a parity signal from an output signal of the signal selection section. A parity selection unit that selects the output of the input-side parity generation unit with the same logic as the signal selection unit, and a parity check unit that compares the output of the parity selection unit with the output of the output-side parity generation unit. It is located with.

It is preferable that the signal selector and the parity selector are controlled in synchronization by a common frame synchronization signal.

[0010]

The order of data propagating in a computer device may be changed. This is because, for example, data including the first bit of the frame synchronization pattern is brought first.

In the present invention, the parity signal generated on the input side is rearranged in the same manner as the data signal and output, and the parity check is performed by comparing the parity signal with the data signal. The parity bits always match on the output side.

Thus, the parity check can be correctly performed even in a device in which the data order is switched between the input side and the output side. Therefore, a parity check can be performed on all bits of the frame.

According to the method of the present invention, the serial-to-parallel converter on the input side cannot be monitored substantially. But in general,
In such a monitored circuit, when rearranging signals,
In most cases, errors occur when synchronization is lost, and almost no errors occur in a circuit that converts an input serial signal into a parallel signal once. Therefore, the method of the present invention is practically sufficient. However, it is possible to monitor the malfunction of the monitored circuit. That is, in the method of the present invention, complicated control by the RAM is unnecessary, and the apparatus can be configured at low cost.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to FIG. FIG. 1 is a block diagram of an apparatus according to an embodiment of the present invention.

[0015] The present invention includes a serial-parallel converter 1 for converting an input serial signal into parallel signals, the row physician sorting of the parallel signal
A parity check method of the monitored circuit 21 and a signal selection unit 3 for output force.

Here, the feature of the present invention is that the parity signals are generated from the output signals of the input side parity generators 4 ₁ to 4 _n for generating the parity signals for each of the parallel signals and the signal selector 3. an output-side parity generator 5, a parity selection unit 6 for selecting an output of the input-side parity generation unit 4 ₁ to 4 _n by the signal selecting portion 3 and the same logic, the output-side parity generation and output of the parity selector 6 And a parity check unit 7 for checking the output of the unit 5.

The signal selector 3 and the parity selector 6 are controlled in synchronization by a common frame synchronization signal.

Next, the operation of the embodiment of the present invention will be described with reference to FIGS. Figure 2 is a diagram showing an input-side parity generation unit 4 ₁ to 4 _n method of parity generation in the embodiment of the present invention. FIG. 3 is a diagram showing a parity generation method of the output side parity generation unit 5 according to the embodiment of the present invention. In FIG. 1, an input serial signal is serial-to-parallel converted by a serial-to-parallel conversion unit 1 into n signals, and a frame synchronization pattern detection unit 2 and a signal selection unit 3
Is input to The frame synchronization pattern detection unit 2 detects the frame synchronization pattern and detects a leading bit indicating which of the n pieces of data includes the leading bit of the frame synchronization pattern based on the detected frame synchronization pattern. The information is output to the signal selection unit 3 and the parity selection unit 6. The signal selection unit 3 rearranges the n pieces of data input from the serial-parallel conversion unit 1 based on the frame synchronization pattern head bit detection information, as already shown in FIG. As shown in FIG. 2, the input-side parity generator 4 ₁
In 4 _n , n kinds of parity signals considered as an output of the signal selection unit 3 are generated from n pieces of input data of the signal selection unit 3. The parity selection unit 6 selects the parity bits corresponding to the same arrangement order as the output of the signal selection unit 3 from the n kinds of parity signals based on the frame synchronization pattern head bit detection information input from the frame synchronization pattern detection unit 2. .

As shown in FIG. 3, in the output side parity generation section 5, parity bits are collectively generated from all bits in the same time slot of each signal from n output signals of the signal selection section 3, By comparing the parity check unit 7 with the parity bit selected by the parity selection unit 6, it is possible to perform a parity check on all bits in the frame.

[0020]

As described above, according to the present invention,
Parity check can be correctly performed even in a device in which the data order is switched between the input side and the output side. Therefore, a parity check can be performed on all bits of the frame.

[Brief description of the drawings]

FIG. 1 is a block diagram of an apparatus according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating a parity generation method of an input-side parity generation unit according to the embodiment of the present invention.

FIG. 3 is a diagram illustrating a parity generation method of an output-side parity generation unit according to the embodiment of the present invention.

FIG. 4 is a diagram showing a conventional in-device parity check method.

FIG. 5 is a diagram illustrating a parity generation method of an output-side parity generation unit.

FIG. 6 is a diagram showing a data sorting method.

[Explanation of symbols]

Reference Signs List 1 serial-parallel conversion unit 2 frame synchronization pattern detection unit 3 signal selection unit 4 ₁ to 4 _n input-side parity generation unit 5 output-side parity generation unit 6 parity selection unit 7 parity check unit 21 monitored circuits 22, 23 parity generation unit 24 Parity check section

Claims (2)

(57) [Claims] 1. A and serial-parallel converter for converting an input serial signal into parallel signals of n bits, the row physician sorting of the parallel signal
In the parity check method of the monitored circuit and a signal selection unit for output power, shifted by one bit for parallel signals of n bits
An input-side parity generation unit that generates a parity signal for each of the n combinations , an output-side parity generation unit that generates a parity signal from an output signal of the signal selection unit, and an output of the input-side parity generation unit. A parity check method comprising: a parity selection unit that selects with the same logic as a signal selection unit; and a parity check unit that checks the output of the parity selection unit and the output of the output side parity generation unit. 2. The parity check method according to claim 1, wherein said signal selection section and said parity selection section are controlled synchronously by a common frame synchronization signal.