JP2746054B2 - Automatic layout design method for LSI - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an automatic layout design method of an LSI, and more particularly, to a method of automatically designing a cell arrangement and a wiring layout of a cell column in an LSI such as a cell-based system by CAD.

[0002]

2. Description of the Related Art In a cell-based LSI, a power supply terminal and a ground terminal of a cell have a structure in which power can be supplied within the same cell row by adjoining each cell. For this reason, when laying out the power supply wiring, the power supply wiring from the bus is connected to the cell arranged at one end of each cell column, so that the power supply wiring is sequentially connected to the power supply terminal and the ground of the adjacent cell. Connect to terminal. That is, connecting a power supply line to a cell arranged at an end of a cell row and supplying power to all cells in the same cell row are:
This is equivalent in layout design.

Conventionally, when a layout design of a power supply wiring of an embedded array system is performed by a cell-based LSI, the following method has been adopted by utilizing a cell structure of the cell-based LSI. That is, first, in the first step, cells are arranged in a cell array set on the chip, and a feed-through cell that fills the gap is arranged in a cell array where no cell is arranged. Next, in a second step, power and ground buses (hereinafter, also simply referred to as buses) which are generally orthogonal to the cell rows are arranged, and power and ground terminals of the first metal layer are connected as wires for connecting to the buses. It is arranged in the cell at the end of each cell row, and then laid out such that the power supply wiring from the bus is connected to the power supply and ground terminals.

FIG. 9 is a plan view of an LSI that has been automatically laid out by the conventional method. The power supply wiring 20 connected to each cell column 12 is provided with a via 16 connecting the different layers for connection to the bus 14, and the power supply wiring is connected to each other so that the wirings of different potentials do not short-circuit. A necessary interval is provided therebetween, and necessary wiring bending is laid out. Among the cell-based LSIs, the embedded array method is a method in which the absolute position of the cell row 12 is fixed from the initial stage of the layout as described above. In the case of the same method, the cell array 12 is fixed. In addition, it is necessary to predict an area required for bending the power supply wiring 20 in advance.

For this reason, first, a space required for bending is predicted for the entire cell row. Cells are arranged in each cell column 12 based on the predicted space, and power supply wirings 20 from each cell column 12 to the bus 14 are actually provided.
Layout is performed. When the layout of the power supply wiring 20 is completed, the necessary wiring layout of the signal lines is continuously performed.

[0006]

According to the above-mentioned conventional automatic layout design method, a space for bending is predicted with a uniform size for all the cell rows, and based on that, the arrangement of the cell rows is actually determined. It is determined. For this reason, as shown in FIG. 9, the space 21 expected for a cell row where bending is not actually provided is wasted, and the chip density is reduced due to the wasted space 21. There is.

In addition, it is difficult to accurately predict the space for the above-mentioned bending, and if the space is estimated to be small, the space required between the wirings in the actual layout design of the power supply wiring is insufficient, and some spaces are required. The design period is lengthened due to repeated estimation and layout trials. Also, if the space is largely estimated, the area of the largely estimated portion cannot be used, and the degree of integration of the chip is further reduced.

According to the present invention, in view of the above-described drawbacks of the conventional LSI automatic layout design method, the space necessary for bending the power supply wiring can be determined without excess or deficiency. In addition, there is no unnecessary space for lowering the integration degree.
It is an object of the present invention to provide an automatic layout design method of I.

[0009]

In order to achieve the above object, an automatic layout design method for an LSI according to the present invention comprises: a plurality of cell rows in which at least one end is aligned with each other and provisionally positioned; A bus arranged at a predetermined distance from the one end of the column is arranged on a chip, and a power supply line from the bus to the one end of each of the cell columns is arranged. If the wiring needs to be bent, the one end of the cell row is moved away from the bus by a predetermined distance depending on the distance between the bent position and the bus. If the position of one end is determined and the power wiring does not need to be bent,
It is characterized in that the one end is determined as it is at the provisionally positioned position, and a cell is arranged in each cell row finally determined by the determination and determination.

[0010]

According to the automatic layout design method of the present invention, one end of a cell row is temporarily positioned, and the position of one end of the cell row is determined each time according to the presence or absence of bending when arranging a power supply wiring. Alternatively, the cell row is determined before the cell arrangement in the cell row, and the space required for bending can be determined without excess or deficiency, so that no unnecessary space is generated. It is not necessary to repeatedly perform a space estimation and a layout trial.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in more detail with reference to the drawings. FIG. 1 is a flowchart showing a main routine of layout design in the automatic layout design method according to one embodiment of the present invention. This routine is all performed by CAD. As shown in the figure, in the method of this embodiment,
First, in step S01, a cell row in which one or both ends are temporarily positioned on a chip and a bus bar adjacent to the end are arranged. Next, in step S02, a power supply wiring extending from the provisionally positioned end of each cell column to the bus is performed, and at that time, a final determination of the end of the cell column is performed. Then, after arranging cells in each cell column in step S03,
In step S04, a layout design on a chip is performed by laying out signal wiring between each cell and the outside.

FIG. 2 is a flowchart showing details of the arrangement of the power supply lines and the determination of the position of the end of the cell row in step S02. As shown in the figure, in this layout design method, the power supply wiring is arranged from the first cell row to the last cell row, and at the same time, the end of the cell row is positioned. In addition, the order of the cell columns in which the power supply wiring is performed can be arbitrarily selected. In FIG. 2, first, step S
At 22, the first cell row is selected, and the cell row selected at step S <b> 23 is tentatively laid out as it is without bending the power supply wiring. In this state, it is checked whether or not the power supply wiring needs to be bent by checking whether a necessary separation distance from other wirings can be obtained (step S24). If bending is not necessary, the cell row and the temporarily laid out power supply wiring are determined at the same position (step S27).

In step S24, if, for example, a bend is required to obtain a required separation distance from another power supply wiring or the like which has already been determined, the position of the bend is determined. The provisionally positioned end of the cell row is retracted to a position where the bending position can be given to shorten the cell row (step S25), and the arrangement of the power supply wiring and the cell row is determined at that position (step S26). ).

Next, if the cell row on which the above processing has been performed is not the _NT- th last cell row (step S28),
The next cell column is selected, and the layout of the power supply wiring and the arrangement of the cell columns are determined in the same manner. When the determination of the power supply wiring and the arrangement of the cell columns is completed for the last cell column, the process returns to step S03 of the main routine in FIG. 1, and the cells are arranged in each cell column as described above.

FIGS. 3 to 7 are chip plan views showing the layout of the power supply wiring and the manner of determining the end of the cell column for one end of the cell column shown as the right end in the drawings. FIG. 3 shows a state in which the ends of the cell columns are temporarily positioned with the distance between each cell column 12 and the I / O cell 13 being L. The distance L is determined from the sum of the width of each bus bar on the high potential side and the low potential side and the required separation distance between the wirings.

Next, as shown in FIG. 4, the layout of both buses 14A and 14B actually provided as the second metal layer is determined. Both buses 14A and 14B are orthogonal to the cell row 12, and the high potential side bus 14 on the left side in the drawing.
A is connected via a via 16 to a power supply line 15 of the first metal layer extending from the I / O cell 13. At this point, a virtual cell 22 is arranged at the end of each cell row. The power supply terminal and the ground terminals 18A and 18B constituting the first metal layer are arranged on the virtual cell row 22 above.

In FIG. 5, the power supply terminal and the ground terminal 18A, 18B of the virtual cell 22 are connected to the bus 14A,
Each of the power supply wirings 20 extending to 14B is laid out as a metal first layer. As shown in FIG.
The power supply wiring 20 of each of the second and fifth cell columns 12 is:
Both buses 14A, 14 without bending
B can be connected. For this reason, in the cell row 12, the temporarily arranged right end is determined as it is as the right end of the cell row.
On the other hand, in the layout of the power supply line 20 in the third column 12, the power supply line 15 on the high potential side in the first metal layer is used.
In order to provide a predetermined separation distance between the power supply wiring 20 on the low potential side of the third column and the power supply wiring 20 on the third column,
Requires bending.

For this reason, in the third cell row, the virtual cell 22 is moved from the end of the cell row by a predetermined distance necessary for connection to the bent portion, and this bending is realized. Similarly, the power supply wiring of the fourth cell row 20 needs to be bent to provide a necessary predetermined distance between power supply wirings of different potentials with the power supply wiring 20 of the third cell row. Becomes In this case, cell column 2 is located between the bus and the cell column.
Since the two folds are arranged so as to overlap, the moving distance of the virtual cell 22 in the fourth row is twice the moving distance of the virtual cell 22 in the third row. As described above, the moving distance of the virtual cell 22 varies depending on the distance of the bending position from the generatrix.

FIG. 6 shows an arrangement of cell rows determined after laying out the power supply wiring. At this point, the virtual cell has been removed, and the right end in the drawing of the virtual cell whose position is determined in FIG. 5 is determined as the right end of the cell row. Such determination of the power supply wiring and one end of the cell row is similarly performed at the other end of the cell row. Next, the cells 17 are automatically arranged in each of the thus determined cell rows, and the feedthrough cells are arranged at the positions of the empty cells as in the conventional case (FIG. 7). Automatic layout of the signal wiring of each cell is performed subsequent to the cell arrangement.

In the above embodiment, when the power supply wiring of the cell row needs to be bent, the cells are not arranged in the bent portion as in the conventional case, but the bending is not actually required. Cells can be arranged in the cell column. In this way, as shown in FIG. 7, the cells can be arranged in the area 21 where the cells are not arranged as the area for bending uniformly conventionally. For this reason, the chip area can be effectively used, and the LSI can be highly integrated. In this embodiment, the necessity of bending is determined on the basis of the actual layout. Therefore, it is not necessary to estimate the area for bending the power supply wiring, which is required in the conventional LSI layout design method. Become.

An increase in the number of cells realized by the layout design method of the above embodiment will be estimated. On the chip, power supply wires are connected to the left and right ends of each cell row, respectively. For example, the total number of cell rows is 200, the pitch required for bending the power supply wiring is 9 μm per cell, the overlapping of the bending is 5 cell rows, and the cell rows that actually need to be bent on the left and right sides of the chip Is assumed to be 10 steps, and the grid width, which is the minimum structural unit of the cell, is 15 μm. In that case, the number of grids of cells that is reduced by shifting one end because bending is required is 9 × 5/15 = 3.

In the 200 chips of the whole chip, even in the method of the embodiment, except for each of the 10 cell rows in which the cells are actually reduced at each end, all the other cell rows have the same arrangement as the temporary arrangement. Cells can be placed. For this reason, the difference in the number of grids from the conventional method in which cells are uniformly reduced is 3 × (200−10) ×
2 = 1140. Normally, one cell can be constituted by two or three grids, so that when 1140 grids are converted into the number of cells, it becomes about 400. That is, according to the method of the above embodiment, a region corresponding to about 400 cells can be newly and effectively used as compared with the conventional method.

FIG. 8 is a plan view of an LSI for illustrating another example of the automatic layout design method for an LSI according to the embodiment of the present invention. In the LSI shown in the figure, a macro block 24 and a cell column 12 are arranged in a mixed manner, and a state of power supply from the buses 23A and 23B to the macro block 24 and the cell column 12 is shown. First, the second metal perpendicular to the cell row
Layer buses 23A and 23B are arranged between cell column 12 and macroblock 24. Next, the macro block 24
Are connected to the buses 23A and 23B by conductors 25A and 25B of the first metal layer, respectively. Subsequently, the power supply wiring 20 to each cell column 12 is performed in the same manner as described with reference to FIGS. In the layout obtained, FIG.
As shown in, the cell row 1
It is only two rows that the end of 2 is retracted, and the other cell rows 12
FIG. 3 shows that cells can be arranged even in the area 21 where cells cannot be arranged conventionally.

According to the present invention, the ends of the temporarily positioned cell row are moved depending on the necessity of bending of the power supply wiring and the position of the bending, so that the end of the power supply wiring is required for layout. The main point is to determine a suitable space each time and determine the layout of the cell rows. Therefore, the layout design method described in the above embodiment and the configuration of the cell row and the layout of the power supply wiring obtained by the layout design are all merely examples, and various modifications and changes can be made therefrom.

[0025]

As described above, according to the LSI automatic layout design method of the present invention, when arranging the power supply wiring of each cell column, the space actually required for bending can be obtained without excess or shortage. As a result of effective use of the area, the degree of integration of the LSI can be improved, and the repetition of bending estimation and wiring layout trial can be avoided, so that efficient design is possible.

[Brief description of the drawings]

FIG. 1 is a flowchart of an automatic layout design method for an LSI according to an embodiment of the present invention.

FIG. 2 is a flowchart showing a routine for determining a power supply line and a cell column end in the flowchart of FIG. 1;

FIG. 3 is a plan view of a chip showing one example of a layout performed by the embodiment of FIG. 1 as one stage.

FIG. 4 is a plan view of a chip showing one example of a layout performed by the embodiment of FIG. 1 as one stage;

FIG. 5 is a plan view of a chip showing one example of a layout performed by the embodiment of FIG. 1 as one stage.

FIG. 6 is a plan view of a chip showing one example of a layout performed by the embodiment of FIG. 1 as one stage.

FIG. 7 is a plan view of a chip showing one example of a layout performed by the embodiment of FIG. 1 as one stage.

FIG. 8 is a plan view of a chip showing another example of a layout performed by the embodiment of FIG. 1;

FIG. 9 is a plan view of a chip showing an example of a layout result according to a conventional method.

[Explanation of symbols]

 Reference Signs List 12 cell row 13 I / O cell 14A, 14B bus 15 power supply line 16 via 17 cell 18A, 18B virtual cell power terminal 20 power supply wiring 21 space 22 virtual cell 23A, 23B bus 24 macroblock 25A, 25B power supply line

Claims (4)

(57) [Claims] 1. A plurality of cell rows each having a predetermined row width and at least one row end being aligned with each other and temporarily positioned, and a predetermined separation distance from the one row end of each cell row. And a power supply line extending from the bus line to the one end of each of the cell columns when the power supply line needs to be bent. Determines the position of the one row end by moving the one row end of the cell row away from the bus by a predetermined distance depending on the separation distance between the bending position and the bus bar. In the case where the power supply wiring does not need to be bent, the one column end is fixed as it is at the provisionally positioned position, and the cells are arranged in each cell column finally determined by the determination and determination. LSI automatic layout characterized by performing A total way. 2. The automatic layout design method for an LSI according to claim 1, wherein a signal wiring layout is performed after arranging the cells. 3. The LSI automatic layout design method according to claim 1, wherein the bending occurs to secure a necessary separation distance between wirings having different potentials. 4. The arrangement of a power supply wiring and the determination and determination of an end of a cell column at the other end of the cell column in the same steps as those of the one end.
5. An automatic layout design method for an LSI according to claim 1.