JP2747012B2 - Digital signal decoding circuit - Google Patents

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial application field) The present invention relates to a digital signal decoding method for determining "1" and "0" of a received digital signal in, for example, a digital mobile communication system.

(Prior Art) In a digital mobile communication system, the transmitting side replaces "1" and "0" of a digital signal with a change in frequency or a change in voltage and transmits the signal, and the receiving side transmits the signal from the transmitting side. After the signal is received and demodulated, "1" and "0" are determined by comparing the received digital signal with a reference signal level. FIG. 6 shows an example of the decoding operation.
By setting the reference signal level Vth to an appropriate value in advance and comparing the received digital signal RD with the reference signal level Vth as shown in FIG.
A decoded digital signal OD as shown in FIG.

(Problems to be Solved by the Invention) However, in this type of decoding circuit, since the reference signal level Vth is fixedly set, for example, a fluctuation of the modulation / demodulation frequency or a fluctuation of the voltage value occurs on the transmission side or the reception side. As a result, if the DC level of the received digital signal RD changes as shown in FIG. 7 (a), for example, accurate level determination cannot be performed. As a result, as shown in FIG. There was a problem that an error occurred.

It is an object of the present invention to pay attention to this point and to provide a digital signal decoding circuit capable of always performing accurate decoding without being affected by a change in the DC level of a received digital signal.

Another object of the present invention is to provide a digital signal decoding circuit capable of always setting an optimum reference signal level by removing the influence of a signal value of a received digital signal even if the signal value temporarily changes suddenly due to noise or the like. To provide.

[Structure of the Invention] (Means for Solving the Problems) According to the present invention, even when the DC level of a received digital signal changes, the amplitude value between "1" and "0" of the received digital signal is substantially constant. Focusing on the fact that there is a signal value detecting means for detecting the signal value of the received digital signal at the level determination point, and a signal value detected by the signal value detecting means, based on a known amplitude value of the digital signal. A center value calculating means for adding or subtracting a preset fixed value to obtain a center value of the amplitude of the received digital signal at the level determination point, wherein the center value calculated by the center value calculating means is used as a next level determination point. Is set as the reference signal level.

In another aspect of the present invention, when the reference signal level is set, an average of each center value at a plurality of past continuous level determination points obtained by the center value calculating means is obtained, and this average value is used as a next level determination point. Is set as the reference signal level.

(Operation) As a result, according to the present invention, since the reference signal level is constantly set to the center value of the received digital signal, even if the DC level of the received digital signal changes for some reason,
The reference signal level changes following the change in the DC level. For this reason, the received digital signal is always determined to be "1" or "0" according to the optimum reference signal level, whereby high-quality decoding without errors can be performed.

According to another aspect of the present invention, when setting the center value of the received digital signal as the reference signal level at the next level determination point, an average of the respective center values obtained at the past continuous decoding level determination points is calculated. Since this average value is set as the reference signal level at the next level determination point, even if the signal value of the received digital signal temporarily changes suddenly due to noise, etc. The problem that the value is set as the reference signal level at the next level determination point as it is is eliminated, and thus the reference signal level can be set more accurately.

(Embodiment) FIG. 1 shows a configuration of a digital signal decoding circuit according to an embodiment of the present invention. This circuit has a control unit (CPU) 1 composed of a microprocessor.
The CPU 1 is connected via a bus to a ROM 2 storing a control processing program and a RAM 3 for storing various data, and furthermore, an input buffer latch circuit 4 and an input / output interface comprising, for example, a programmable peripheral interface (PPI). The circuits 5 are connected to each other. An analog / digital (A / D) conversion circuit 6 is connected to the input buffer latch circuit 4. The A / D conversion circuit 6 samples the signal value of the received signal RD for each bit in synchronization with the clock CLK, converts the signal value VS into a digital signal, and outputs the digital signal. 7 and 8 are the reception digital signal RD and the clock CLK.
The input / output interface circuit 5 has a DIP switch (SW) 9 and a D-type flip-flop (D-F
F) are connected to each other. Of these, the dip switch 9 is used to input a fixed amplitude value ΔV, which is one of the parameters required for decoding. The fixed amplitude value ΔV is a value corresponding to の of the amplitude value between “1” and “0” of the received digital signal RD detected in advance. The output latch circuit 10
The sign determination data output from the PPI 5 is temporarily latched in synchronization with the clock CLK inverted by the inverter circuit 11, and the latched sign determination data is decoded data OD.
Is output as

Next, the operation of the circuit configured as described above will be described.
First, prior to the operation of the circuit, an amplitude value between “1” and “0” of the received digital signal RD is detected, and a half value of the amplitude value is set as a fixed amplitude value ΔV by the dip switch 9.

When the power is turned on in this state, the CPU 1 performs predetermined initial processing and then sets its own operation mode to the interrupt inhibition mode in step 2a as shown in FIG. After clearing the data stored in the RAM 3 in step 2b, initialization is performed on the PPI 5 in step 2c. Then, the fixed amplitude value ΔV set in the dip switch 9 is loaded to the CPU 1 via the PPI 9 and the CPU 1 stores the fixed amplitude value ΔV in a predetermined area of the RAM 3 in step 2d. After storing the fixed amplitude value ΔV, the CPU 1
Sets its own operation mode to the interrupt permission mode in step 2e, and thereafter starts the decoding process.

That is, first, in the preamble period set at the head of the received digital signal RD, the reference signal level
Initialize Vth. In the preamble period, the received digital signal RD repeats "1" and "0", and the signal value VS is sampled and digitized by the A / D conversion circuit 6 for each bit in this repeating pattern. Every time the interrupt signal INT synchronized with the clock CLK is inputted, the CPU 1 performs the digitization of the repetition pattern from the A / D conversion circuit 6 through the input buffer latch circuit 4 in steps 3a to 3c as shown in FIG. The signal is loaded, and processing for obtaining the DC level of the received digital signal RD from the value VS of the digital signal is performed. Then, when a stable DC level is obtained, an initial value of the reference signal level Vth is set according to the value of the DC level, and the initial value of the reference signal level Vth is stored in the RAM 3 in step 3d.

When the setting of the initial value of the reference signal Vth is completed, the CPU 1 sets the input buffer latch circuit 4 in step 3e every time the interrupt signal INT synchronized with the clock CLK is input.
, The digitized signal value VSn of the received digital signal RD is loaded from the A / D conversion circuit 6 via. And step 3
The reference signal level Vth is read from the RAM 3 by f, and the digitized signal value VSn is compared with the reference signal level Vth.
As a result of this comparison, when it is determined that the digitized signal value VSn is equal to or higher than the reference signal level Vth, it is determined that the bit level of the received digital signal RD input at this time is "1", and the process proceeds to step 3g. Here, the determination signal of "1" is sent to the PPI5. On the other hand, when it is determined that the digitized signal VSn is lower than the reference signal level Vth, it is determined that the bit level of the received digital signal RD at this time is “0”,
The process proceeds to step 3i, where a determination signal of “0” is output to PPI5. These "1" and "0" judgment signals are output from the PPI 5 to the D-type flip-flop 10,
After being latched in synchronization with the clock CLK at 10, the decoded signal O
Output as D.

By the way, in the decoding circuit of this embodiment, as described above, the reference signal level Vth is updated every time the received digital signal RD is decoded by one bit. That is, when the output of the determination signal is completed, the CPU 1 shifts to step 3h when “1” is output, where the digitized signal value VSn
Is subtracted from the fixed amplitude value ΔV stored in the RAM 3 to calculate the center value Vn of the amplitude of the received digital signal RD. If "0" is output, the process proceeds to step 3j, where the fixed amplitude value ΔV is added to the digitized signal value VSn to calculate the center value Vn of the amplitude of the received digital signal RD. For example, if the received digital signal RD as shown in FIG. 4 is input now the first bit position t ₁ is detected by the A / D converter circuit 6 a digital signal value V
Since S ₁ is determined to be “1”, the digitized signal value VS
_The fixed amplitude value ΔV is subtracted from ₁ to calculate the center value V ₁ of the bit amplitude at this time. At the next bit position t ₂ , the digitized signal value VS ₂ is determined to be “0”, so that the value of the digitized signal value VS ₂ has the fixed amplitude value ΔV
The adds to calculate the central value V ₂ of the amplitude of bits of the time. Similarly, at the subsequent bit positions t ₆ , t ₇ ,..., The digitized signal values VS ₆ , VS ₇ ,. performs subtraction or addition of the [Delta] V, thereby to calculate the received digital signal center value V ₆ of the amplitude of each bit in RD, V _7, ..., respectively. Then, the central value Vn of the amplitude of each bit calculated in this manner is obtained from the CPU 1 in step 3k of FIG. 3 (b).
The data is transferred to the RAM 3 and stored.

When the storing of the amplitude center value Vn is completed, the CPU 1 then proceeds to the past continuous m-bit amplitude center values V _{n-m + 1} , V _{n-m + 2} ,... Including the amplitude center value Vn just calculated. , Vn in step 3l
Each of them is read from AM3, and in step 3o, the average value Vn 'of these m amplitude center values Vn _{-m + 1} , Vn _{-m + 2} ,..., Vn is calculated. Then, the calculated average value Vn ′ is used for the next bit position.
RAM3 as the new reference signal level Vth used at t _{n + 1}
To be stored. For example, now m = 5, and under this condition the fourth
When the bit position t ₇ shown in FIG attempts to set a new reference signal level Vth to be used in the next bit position t ₈ is the last 5 bits comprise V ₇ from RAM3 amplitude center value V _3,
The _{V 4, V 5, V 6} , V 7 reads from each of RAM 3. And the average value of these 5 bit amplitude center values V ₃ , V ₄ , V ₅ , V ₆ , V ₇
V ₇ ′ is calculated, and the average value V ₇ ′ is set as a new reference signal level Vth used in the next bit position t ₈ , and the old reference signal level stored in the RAM 3 is rewritten to the new reference signal level Vth. .

When the reference signal level Vth is updated in this manner, the CPU 1 returns to step 3e of FIG.
The signal level is determined at V _{n + 1} and the reference signal level Vth is updated, and thereafter the above control is repeated for each bit position.

As described above, in the present embodiment, the signal value VSn is detected for each bit of the received digital signal RD, and the reference signal level Vth
Is compared with the level to determine “1” or “0”, and the amplitude fixed value Δ prepared in advance for the signal value VSn.
Digital signal received by adding or subtracting V
The amplitude center value Vn of the RD is calculated, and this amplitude center value Vn is updated as a new reference signal level Vth used in the next bit. Therefore, even if the DC level of the received digital signal RD changes for some reason, the reference signal level Vth changes as shown in FIG. 5, for example, following the change in the DC level. Therefore, the received digital signal RD can always be decoded in accordance with the optimum reference signal level Vth. Moreover, in the present embodiment, when the reference signal level Vth is updated, the average of the amplitude center values in a plurality of past consecutive bits is averaged, and this average value is used as the new reference signal level. Therefore, even if the signal value of the received digital signal RD temporarily changes largely due to noise or the like, the effect of the temporary signal change can be reduced and a stable reference signal level can be set. Therefore, the stability of the decoding operation can be improved. Further, in this embodiment, the signal level “1”,
Since all processes for determining “0” and updating the reference signal level Vth are performed digitally by the CPU 1, highly accurate decoding can be performed.

The present invention is not limited to the above embodiment. For example, in the above embodiment, the digital circuit is used.
You may comprise by an analog circuit. In the above embodiment, the reference signal level is updated for each bit. However, the reference signal level may be updated every fixed bit. In this way, the load on the CPU 1 can be reduced, and a higher-speed received digital signal can be handled accordingly. Further, the reference signal level may be manually input together with the fixed amplitude value using a dip switch,
In this case, other input means such as a numeric keypad may be used as the input means. Conversely, the fixed amplitude value may be automatically set together with the reference signal level based on the signal level of the received digital signal RD. In addition, the value of the number of bits m to be referred to when determining the reference signal level, the configuration of the means for detecting the signal value of the received digital signal, the configuration of the center value detection means, the configuration of the reference signal level setting means, etc. Various modifications can be made without departing from the spirit of the invention.

[Effects of the Invention] As described above in detail, according to the present invention, a signal value detecting means for detecting a signal value of a received digital signal at a level determination point, and a signal value detected by the signal value detecting means, Center value calculating means for adding or subtracting a fixed value set in advance based on the known amplitude value of the digital signal to obtain the center value of the received digital signal at the level determination point. By setting the obtained center value as the reference signal level at the next level determination point, even if the DC level of the received digital signal changes, the digital signal can always be accurately decoded without being affected by this change. A decoding circuit can be provided.

According to yet another aspect of the present invention, when setting the reference signal level, an average of each center value at a plurality of past consecutive level determination points obtained by the center value calculating means is obtained, and this average value is set to the next level. Even if the signal value of the received digital signal temporarily changes suddenly due to noise, the influence is removed and the optimum reference signal level is always set by setting the reference signal level at the judgment point. An obtained digital signal decoding circuit can be provided.

[Brief description of the drawings]

1 to 5 are diagrams for explaining a digital signal decoding circuit according to an embodiment of the present invention. FIG. 1 is a circuit configuration diagram, and FIGS. 2 and 3 are control procedures and control of a CPU. FIG. 4 is a signal waveform diagram for explaining a reference signal level update processing operation, FIG. 5 is a signal waveform diagram for explaining a determination operation by the circuit shown in FIG. 1, and FIG. FIG. 7 and FIG. 7 are signal waveform diagrams showing the operation of the conventional digital signal decoding circuit. DESCRIPTION OF SYMBOLS 1 ... Control circuit (CPU), 2 ... ROM, 3 ... RAM, 4 ... Input buffer latch circuit, 5 ... Input / output interface circuit (PP
I), 6: Analog / Digital conversion circuit (A / D conversion circuit), 7, 8: Input buffer, 9: Dip switch, 10
… Output latch circuit, 11… Inverter circuit, 12… Output buffer, RD… Received digital signal, CLK… Clock, OD…
Decoded signal, ΔV: fixed amplitude value, Vth: reference signal level, V
Sn: digitized signal value, Vn: amplitude center value.

 ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-2-20941 (JP, A) JP-A-63-131719 (JP, A) JP-A-61-258524 (JP, A) JP-A-2-210 305149 (JP, A) JP-A-1-125503 (JP, A) JP-A-2-305148 (JP, A)

Claims (2)

(57) [Claims] 1. A digital signal decoding circuit for comparing a received digital signal with a reference signal level in its bit cycle to determine "1" or "0" detects a signal value of the received digital signal at the level determination point. A signal value detecting means for adding or subtracting a fixed value set in advance based on a known amplitude value of the digital signal to the signal value detected by the signal value detecting means, A center value calculating unit for obtaining an amplitude center value; and a reference level setting unit for setting the amplitude center value obtained by the center value calculating unit as a new reference signal level used at a next level determination point. Digital signal decoding circuit. 2. A digital signal decoding circuit for comparing a received digital signal with a reference signal level in its bit period to determine "1" or "0" detects a signal value of the received digital signal at the level determination point. A signal value detecting means for adding or subtracting a fixed value set in advance based on a known amplitude value of the digital signal to the signal value detected by the signal value detecting means, A center value calculating means for calculating the amplitude center value, and a new average value for calculating the average of each amplitude center at a plurality of past consecutive level determination points obtained by the center value calculating means is used at the next level determination point. And a reference level setting means for setting a reference signal level.