JP2752800B2 - Bit error addition circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bit error adding circuit used for simulating a bit error characteristic by forcibly inverting a predetermined bit of a signal transmitted on a line.

[0002]

2. Description of the Related Art FIG. 6 shows an example of a conventional bit error adding circuit. This bit error adding circuit includes a random number generator 11, an error adding circuit 12, and a gate circuit 13. For example, in an ATM (Asynchronous Transfer Mode) communication system in which multimedia such as data of various speeds and video / audio signals are handled. A bit error characteristic is simulated by forcibly inverting a predetermined bit of a signal transmitted on a line. More specifically, one word of a cell to be input is, for example, about 10
It is composed of a plurality of bits, for example, 16 bits of parallel data in 0nsec, performs a calculation of generating a random number of, for example, 4 bits for each word, and periodically generates a bit error event by the clock count of the error adding circuit. Then, the enable signal S10 is input from the error adding circuit 12 to the gate circuit 13, and the 1-bit data at a predetermined position in the word, that is, the data of the random number bit on the parallel data corresponding to the 4-bit random value is obtained. Inversion was performed to add a bit error.

[0003]

However, in the current processor technology, in the above-described conventional bit error adding circuit, it takes about 300 nsec to calculate a random number, and the data input every about 100 nsec is required. As a result, the operation speed could not be kept in time, and it was not possible to add an accurate bit error to a necessary portion of data.

Accordingly, the present invention has been made in view of the above-mentioned problems, and an object of the present invention is to increase the time required for calculating a random number and accurately add a bit error to a necessary portion of data. To provide a bit error adding circuit.

[0005]

In order to achieve the above object, a bit error adding circuit according to the present invention has been made by paying attention to the fact that too many bit errors do not occur in an actual communication line. . The feature is that the bit error position is calculated with one cycle every predetermined plural words,
The point is that a means for adding a bit error to the calculated bit error position is provided. More specifically, a bit error adding circuit for adding a bit error to an arbitrary portion of one word of the plurality of words as one cycle for each of a plurality of predetermined words of a signal to be transmitted, wherein the error occurrence rate is predetermined. An error occurrence rate calculation circuit 1 for determining whether or not to add a bit error for each cycle so as to obtain a value; a control unit 6 for outputting the predetermined value to the error occurrence rate calculation circuit; A first error position calculation circuit 2 for calculating a bit error position in a word in the one cycle, determining the predetermined number of words, and determining to which word in the plurality of words an error is to be added; A second error position calculating circuit for calculating in one cycle, and a word of a plurality of words for each cycle when receiving a signal to add a bit error from the error occurrence rate calculating circuit. The first error location in It is characterized in that a error localization circuit 4 for adding a bit error of the calculated bit error addition position by calculation circuit and said second error location calculating circuit.

[0006]

According to the bit error adding circuit configured as described above, it is only necessary to calculate which bit of one word is to be added with an error in the transmission time (one cycle) of a plurality of words, and the calculation time is reduced. You can earn money.

[0007]

FIG. 1 is a block diagram showing an embodiment of a bit error adding circuit according to the present invention. The bit error adding circuit according to this embodiment is, for example, an ATM which handles multimedia such as data of various speeds and video / audio signals.
(Asynchronous transfer mode) In the communication system, it is used when simulating the bit error addition characteristic, and includes an error rate calculation circuit 1, a first error position calculation circuit 2, a second error position calculation circuit 3, and an error position determination. The circuit includes a circuit 4, a gate circuit 5, and a control unit 6.

The error occurrence rate calculation circuit 1 determines whether or not to add a bit error to the data input to the gate circuit 5, and includes an initial value register 1a, a random number generator 1
b, a threshold register 1c and a comparator 1d.

The random number generator 1b is constituted by a circuit based on a so-called PN pattern generated by an M-sequence cyclic code generator as shown in FIG. Further, an initial value register 1a provided at the preceding stage is set based on a command from the control unit (CPU) 6, and a random number signal S1 of a certain bit is generated and compared according to the signal from the initial value register 1a after this setting. Output to the container 1d.

The threshold register 1c outputs a threshold signal S2 of a threshold value having the same bit width as a predetermined random number to the comparator 1d based on a command from the control unit 6.

The comparator 1d compares the random number signal S1 from the random number generator 1b with the threshold signal S2 from the threshold register 1c. When the random number signal S1 is smaller, it indicates that a bit error addition event has occurred. The enable signal S3 is output to the error position determination circuit 4.

The first error position calculating circuit 2 calculates an error position in the direction (column direction) of the input parallel data, that is, an error position of data in one word as shown in FIG. , A random number generator 2a and a decoder 2b.

The random number generator 2a generates, for example, a 4-bit random number and outputs it to the decoder 2b. The decoder 2b converts the 4-bit random number to 16 bits and outputs the converted signal as a column direction position signal S4. Output to

As shown in FIG. 2, the second error position calculation circuit 3 calculates an error position in the word direction (row direction) of the parallel data, that is, an error position in the time axis direction. It comprises a decoder 3b.

The random number generator 3a generates, for example, a 2-bit random number and outputs the 2-bit random number to the decoder 3b. The decoder 3b converts the 2-bit random number into 4 bits, and generates a row direction position signal S5. Output to

When the enable signal S3 is input from the error occurrence rate calculation circuit 1, the error position determination circuit 4 specifies the error position determination circuit 4 by using the column direction position signal S4 and the row direction position signal S5 from the error position calculation circuits 2 and 3. An inverted signal S6 is output to the gate circuit 5 in order to invert the bit at the matrix position of the parallel data.

Here, the operation of the error occurrence rate calculation circuit 1, the first error position calculation circuit 2, and the second error position calculation circuit 3 for determining the bit error addition position described above takes about 400 nse.
c, ie, every four words of the input parallel data (corresponding to one cycle T of bit error calculation).

FIG. 5 shows an embodiment of the error position determination circuit 4. The row direction position signal S5 (4 bits) output from the second error position calculation circuit 3 is written to the shift register 4a every time four words of parallel data are transmitted. The data written in the shift register 4a is shifted by one bit each time the parallel data is input to the one-word (16-bit) gate circuit 5. In order to determine whether or not to invert the parallel data, the signal shifted and output from the shift register 4a and the enable signal S3 from the error rate operation circuit 1 are combined with the OR circuit 4.
Input to b.

An inverted signal for inverting the parallel data is selected based on the output of the OR circuit 4b. Specifically, when the inputs of the OR circuit 4b are both zero, the output becomes zero, and the inverter 4c to which the column direction position signal S4 (16 bits) output from the first error position calculation circuit 2 is input is selected. I do. That is, the inverted signal S6 corresponding to the position of the column determined by the random number generator 2a becomes 1. The gate circuit 5 inverts the corresponding bit of the parallel data according to the inverted signal S6 and outputs the inverted bit.

When any of the inputs of the OR circuit 4b is 1, the output becomes 1, and the inverter 4d is selected. That is, the inverted signal S6 of all bits becomes zero regardless of the column direction position signal S4. The gate circuit 5 outputs the parallel data as it is by the inverted signal S6.

The column direction position signal S4 output from the first error position operation circuit 2 is a bit error operation one cycle T
And the row direction position signal S5 output from the second error calculation circuit 3 corresponds to the number of bits that can represent the number of bits of input data.

The gate circuit 5 is composed of, for example, an exclusive OR circuit, and receives parallel data of 16 bits in one word at about 100 nsec. The gate circuit 5 outputs data as it is while the 16-bit inverted signal S6 is not input from the error position determination circuit 4 (S6 = 0), and when the inverted signal S6 is input (S6 = 1). The bit at the matrix position of the data specified by the inverted signal S6 is inverted, and the bit error is added and output.

As described above, in the bit error adding circuit configured as described above, while four words of parallel data are input to the gate circuit 5 (corresponding to one cycle T of bit error calculation), the next four words are added. Calculate the bit error position to be added inside. For example, when the enable signal S3 is being input from the error occurrence rate calculation circuit 1 to the error position determination circuit 4, the random number generator 2a in the first error position calculation circuit 2 as shown in FIG. If the random number signal is "010
0 ”, the random number generator 3 in the second error position calculation circuit 3
When the random number signal of “a” is “01”, as shown in FIG. 3, the bits of the knitted portion in the parallel data are inverted.

Therefore, in the above-described embodiment, a plurality of words (4 in the embodiment) are used instead of each word of the parallel data.
Since the calculation of the bit error position is performed for each word), the calculation time for adding the bit error can be efficiently obtained, and the bit error can be reliably added to the necessary portion of the parallel data. Further, the above-described circuit can be configured with the existing TTL without changing the number of buses. Further, in the present embodiment, a bit error can be added only in 1/4, but in an actual communication line, not too many bit errors occur, and the simulation can be sufficiently performed in the present embodiment.

In the above-described embodiment, a case has been described in which only one bit of parallel data is inverted to add a bit error. In the case of performing a simulation assuming that many operations cannot be performed in time, a 4-bit error may be continuously inverted by outputting all 0s to the decoder 3b.

[0026]

As described above, the bit error adding circuit according to the present invention uses one bit for every plural words of a signal to be transmitted.
It is a configuration that has a means for adding a bit error to an arbitrary part of one word in the period. Therefore, the operation time for adding the bit error is efficiently obtained, and the bit is surely added to the necessary part of the parallel data. Errors can be added.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a bit error adding circuit according to the present invention;

FIG. 2 is a diagram showing an example of parallel data input to a gate circuit in the circuit

FIG. 3 is a diagram showing an example in which a bit error is added to a predetermined portion of parallel data in the same circuit

FIG. 4 is a block diagram showing an embodiment of an M-sequence cyclic code generator.

FIG. 5 is a block diagram showing an embodiment of an error locating circuit;

FIG. 6 is a block diagram showing an example of a conventional bit error adding circuit.

[Explanation of symbols]

Reference Signs List 1 error occurrence rate operation circuit, 2 first error position operation circuit 3 second error position operation circuit, 4 error position determination circuit 5 gate circuit, 6 control unit T bit error operation cycle

Claims (1)

(57) [Claims] 1. A method according to claim 1, wherein each of a plurality of words of the signal to be transmitted is
One cycle, any part of one of the words
A bit error adding circuit for adding a bit error to the data at each of the above-mentioned periods so that an error occurrence rate becomes a predetermined value.
Error rate calculation circuit to determine whether or not to add error
(1) a control unit that outputs the predetermined value to the error rate calculation circuit
(6) and the bit error position in the one word is determined by the one cycle
A first error position calculation circuit (2) for calculating the predetermined number of words;
Which word to add an error to in one cycle
And a second error position calculating circuit (3) for performing bit error addition from the error occurrence rate calculating circuit.
When a signal is received, a plurality of words are
The first error position calculation circuit in one word of
The bit error calculated by the second error position calculation circuit
An error location determination circuit that adds a bit error to the additional location
(4) A bit error adding circuit comprising: