JP2763545B2 - Bit slide device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing apparatus, and more particularly, to a data processing apparatus that converts information bits of one value “1” or “0” included in binary data having a predetermined number of bits. The present invention relates to a bit slide device for sliding to an upper side or a lower side, and a bit counting device for counting the number of information bits of one value “1” or “0” included in the binary data using the bit slide device.

2. Description of the Related Art Conventionally, there is known a bit counter for counting the number of information bits of one value of “1” or “0” included in binary data having a predetermined number of bits. This bit counting device is widely used in an image data processing device or an audio data processing device. For example, in the case of an 8-bit bit counting device, it is configured using 11 1-bit full adders.

Further, the bit counting device includes, for example, a bit slide circuit that slides a “1” information bit included in the binary data to, for example, a lower side, and a “1” information bit based on data output from the bit slide device. It is composed of an encoder with a priority that encodes and outputs data representing the number of bits. The bit slide circuit is, for example, “10
The 8-bit data of "101010" is converted to "00001111" and output. The encoder with priority assigns the data "00001111" to the least significant bit with the highest priority and the most significant bit to the lowest. And outputs 4-bit data “0100” representing the number of information bits of “1” included in the data “00001111”.

[Problems to be Solved by the Invention] However, the above-described bit counting device is
Since the configuration is made up of 11 1-bit full adders, the configuration circuit becomes very complicated. When the bit counting device is formed on an integrated circuit chip (hereinafter, referred to as an IC chip), it is large. There is a problem that it occupies the substrate area.

Similarly, the above bit slide circuit is provided with a plurality of 1s.
In the case of using a bit full adder, the circuit becomes very complicated, and when the bit slide circuit is formed on, for example, an IC chip, there is a problem that a large substrate area is occupied.

A first object of the present invention is to solve the above problems and to provide a bit slide device which can be constituted by a simpler circuit than the conventional example.

A second object of the present invention is to solve the above problems and to provide a bit counting device which can be constituted by a simpler circuit than the conventional example.

[Means for Solving the Problem] The bit slide device according to the first invention includes first and second bit slide devices.
And a plurality of n data converters having input terminals and first and second output terminals for inputting and outputting data in accordance with the following truth table. Connect to get Each of the data conversion means includes: first gate means for switching whether to output data input to a second input terminal based on data input to a first input terminal; and A first pull-down resistor for pulling down the output of the first gate means to "0" when the output of the means is other than "1"; data input to the first input terminal; and the first gate An OR gate that performs a logical sum of data output from the means and outputs data of a logical result to a first output terminal; and an OR gate that outputs data input to a second input terminal based on output data of the first gate means. Second gate means for switching whether or not to output to the second output terminal; and when the output of the second gate means is other than "1", the output of the second gate means is pulled down to "0". The second pull-down resistor It is characterized by having.

Further, the bit slide device according to the second invention slides the information bit of one value included in the input 2-bit binary data to the upper side or the lower side to output the 2-bit binary data, respectively. A plurality of data conversion means, and slides an information bit of one value included in the binary data of a plurality of bits input to the input terminal to an upper side or a lower side to output the binary data of a plurality of bits to an output terminal. The plurality of data conversion means are connected so as to output, and each of the data conversion means outputs data input to a second input terminal based on data input to a first input terminal. A first pull-down resistor for pulling down the output of the first gate means to “0” when the output of the first gate means is other than “1”; An OR gate that performs a logical sum of data input to an input terminal of the first gate and data output from the first gate means and outputs data of a logical result to a first output terminal; A second gate means for switching whether or not to output data input to the second input terminal to the second output terminal based on the first gate means, and when the output of the second gate means is other than "1", A second pull-down resistor for pulling down the output of the second gate means to "0".

Further, a bit slide device according to a third invention is a bit slide device for sliding an information bit of one value included in input binary data of a plurality of bits to an upper side or a lower side, wherein The information bit of one value included in the 2-bit binary data input to the second input terminal is slid to the upper side or the lower side, and the 2-bit binary data is transmitted to the first and second output terminals. A plurality of data converting means for outputting the data, wherein the least significant bit input terminal of the bit slide device is connected to the first terminal of the first data converting means.
The input terminal of the most significant bit of the bit slide device is connected to the second input terminal of the second data conversion means, and the output terminal of the least significant bit of the bit slide device is connected to the first input terminal. Connected to the first output terminal of the data conversion means, and the output terminal of the most significant bit of the bit slide device is connected to the second output terminal of the third data conversion means. First gate means for switching whether or not to output data input to the second input terminal based on data input to the first input terminal; and output of the first gate means being "1" A first pull-down resistor for pulling down the output of the first gate means to “0” when the value is other than “1”; data input to the first input terminal; and data output from the first gate means. Sum of An OR gate that outputs data of a logical result to a first output terminal and outputs data input to a second input terminal to a second output terminal based on output data of the first gate means A second gate means for switching whether or not the second gate means is turned off; and a second pull-down resistor for pulling down the output of the second gate means to "0" when the output of the second gate means is other than "1". It is characterized by having.

Here, the first and second gate means are, for example, transmission gates, respectively.

Preferably, the bit slide device is coded into binary data representing the number of information bits of one value included in the binary data based on the binary data output from the bit slide device. Encoding means.

[Operation] By configuring as described above, the information bits of one value included in the binary data of a plurality of bits input to the input terminal of the bit slide device are slid to the upper side or the lower side, and the plurality of bits are shifted. Binary data can be output.

In addition, when the encoding means is provided, the encoding means includes a binary value representing the number of information bits of one value included in the binary data based on the binary data output from the bit slide device. Encode the data and output. Therefore, binary data representing the number of information bits of one value included in the binary data input to the bit slide device can be obtained.

Embodiment FIG. 1 is a block diagram of a bit counter according to an embodiment of the present invention. FIG. 2 shows the data conversion circuit 10- of FIG.
It is a circuit diagram of 1 to 10-28. The data used in the following embodiments are all binary data having one value information bit of “1” or “0”.

The bit counting device of the present embodiment has a bit slide circuit 1
The bit slide circuit 1 comprises 28 data conversion circuits 10-1 through 10-1.
It consists of -28.

In FIG. 1, D0 to D7 are input terminals of the bit counting device and the bit slide circuit 1. Data of the least significant bit is input to the input terminal D0, while data of the most significant bit is input to the input terminal D7. You. E0 to E7 are output terminals of the bit slide circuit 1, and the least significant bit data is output from the output terminal E0.
Outputs the data of the most significant bit. Further, Q0 to Q3 are output terminals of the encoder 2 with priority and the bit counting device, and output data of the least significant bit is output from the output terminal Q0, while data of the most significant bit is output from the output terminal Q3.

The input terminals D0 to D6 are respectively connected to the data conversion circuit 10-1.
The input terminal D7 is connected to the input terminal A2 of the data conversion circuit 10-7. Each output terminal B1 of the data conversion circuits 10-1 to 10-7 is connected to an output terminal E0 and the data conversion circuits 10-1 to 10-, respectively.
6 is connected to each input terminal A2, and each output terminal B2 of the data conversion circuits 10-1 to 10-7 is connected to a data conversion circuit.
10-8 to 10-13 input terminals A1 and data conversion circuit
Connected to input terminal A2 of 10-13.

Each output terminal B1 of the data conversion circuits 10-8 to 10-13 has an output terminal E1 and the data conversion circuits 10-8 to 10-13, respectively.
10−12 are connected to each input terminal A2, and the data conversion circuit 10−
The output terminals B2 of 8 to 10-13 are connected to the input terminals A1 of the data conversion circuits 10-14 to 10-18 and the input terminal A2 of the data conversion circuit 10-18, respectively.

Each output terminal B1 of the data conversion circuits 10-14 to 10-18 has an output terminal E2 and the data conversion circuits 10-14 to 10-14, respectively.
Connected to each input terminal A2 of 10-17, the data conversion circuit 10-
The output terminals B2 of 14 to 10-18 are connected to the input terminals A1 of the data conversion circuits 10-19 to 10-22 and the input terminal A2 of the data conversion circuit 10-22, respectively.

The output terminals B1 of the data conversion circuits 10-19 to 10-22 are respectively connected to the output terminal E3 and the data conversion circuits 10-19 to 10-19.
Connected to each input terminal A2 of 10−21, the data conversion circuit 10−
The output terminals B2 of 19 to 10-22 are connected to the input terminals A1 of the data conversion circuits 10-23 to 10-25 and the input terminal A2 of the data conversion circuit 10-25, respectively.

Each output terminal B1 of the data conversion circuits 10-23 to 10-25 has an output terminal E4 and the data conversion circuits 10-26 to 10-26, respectively.
10-27 is connected to each input terminal A2,
Output terminals B2 of 23 to 10-25 are connected to input terminals A1 of data conversion circuits 10-26 and 10-26 and input terminal A2 of data conversion circuit 10-26, respectively.

Each output terminal B1 of the data conversion circuits 10-26 and 10-27 is connected to the output terminal E5 and the input terminal A2 of the data conversion circuit 10-26, respectively, and each output terminal of the data conversion circuits 10-26 to 10-27. B2 is connected to the input terminal A1 and the input terminal A2 of the data conversion circuit 10-28, respectively.

Output terminals B1 and B2 of data conversion circuit 10-28 are connected to output terminals E6 and E7, respectively. The output terminals E0 to E7 are respectively connected to the 8-bit input terminals of the encoder 2 with priority, and the 4-bit output terminals of the encoder 2 are connected to the output terminals Q0 to Q3, respectively.

FIG. 2 shows the data conversion circuits 10-1 to 10-28 of FIG.
FIG.

In FIG. 2, the input terminal A1 is connected to the first input terminal of the OR gate OR and the disable terminal of the transmission gate TG1, and is connected to the enable terminal of the transmission gate TG1 via the inverter INV1. Input terminal A2 is transmission gate TG
The gate is connected to the second input terminal of the OR gate OR via one gate, and is connected to the output terminal B2 via the gate of the transmission gate TG2. The output terminal of the OR gate OR is connected to the output terminal B1.

The output terminal of the gate of the transmission gate TG1 is also connected to the disable terminal of the transmission gate TG2 and to the ground via the pull-down resistor R1. The output terminal of the gate of the transmission gate TG1 is further connected to the enable terminal of the transmission gate TG2 via the inverter INV2.

The output terminal of the transmission gate TG2 is connected to ground via a pull-down resistor R2.

The data conversion circuits 10-1 to 10-28 configured as shown in FIG. 2 operate as shown in the truth table of Table 1. That is, the data conversion circuits 10-1 to 10-28 respectively slide the information bit of "1" included in the 2-bit data input to the input terminals A1 and A2 to the lower side, that is, the output terminal B1. On the other hand, the information bit of "0" is slid to the upper side, that is, to the output terminal B2 side, and then output to the output terminals B1 and B2 as 2-bit data.

The data slide circuit 1 configured as shown in FIG.
The information bit of "1" included in the 8-bit data input to the input terminals D0 to D7 is shifted to the lower side, that is, the output terminal E0.
Side, while the information bit of “0” is
That is, after sliding to the output terminal E7 side, the data is output to the output terminals E0 to E7 as 8-bit data.

The priority encoder 2 encodes the 8-bit data input to the input terminal with the highest priority of the least significant bit and the lowest priority of the most significant bit, and is included in the input data. 8-bit data representing the number of information bits of "1" is output to output terminals Q0 to Q3.

In the bit counting device configured as described above, for example, 8-bit data “10011010” is input to the input terminals D0 to D0.
7, the bit slide circuit 1 slides the "1" information bit included in the data to the lower side, that is, to the output terminal E0, and shifts the "0" information bit to the upper side, that is, the output terminal. After sliding to the terminal E7 side, 8-bit data “00001111” is output to the output terminals E0 to E7. Next, the priority encoder 2 encodes the 8-bit data “00001111” input to the input terminal by assigning the highest priority to the least significant bit and the lowest priority to the most significant bit. 8-bit data “0100” representing the number of information bits “1” included in the input data is output to the output terminals Q0 to Q3.

By configuring the bit slide circuit 1 and the bit counting device as shown in FIG. 1, it can be realized with a simpler circuit than the conventional example. Thus, there is an advantage that the bit slide circuit 1 and the bit counting device can be formed on an IC chip with a smaller occupied area as compared with the conventional example. For example, in the case of an 8-bit bit counter, according to a trial calculation made by the inventor, the bit counter can be formed on an IC chip with an area occupied by 1/3 as compared with the conventional example.

In the above embodiments, the 8-bit bit counter and the bit slide circuit 1 are described. However, the present invention is not limited to this, and the bit counter and the bit slide circuit 1 for processing a plurality of bits of data can be similarly configured. That is, the n-bit slide circuit 1 is configured as shown in FIG. That is, a cell having the circuit shown in FIG. 2 is designated as X, and each cell X is numbered as shown in FIG. 3, and the terminal names of each cell X are A1 (1,1), A2 (1, 1),
B1 (1,1), B2 (1,1) ‥‥ A1 (α, β), A2 (α,
β), B1 (α, β), B2 (α, β) ‥‥ A1 (n, n), A2 (n,
n), B1 (n, n), B2 (n, n), the cell X
The connection of each terminal of (α, β) is as follows.
(However, n ≧ 2, 1 ≦ α ≦ n, 1 ≦ β ≦ n) Here, Dn indicates an input pin name, En indicates an output pin name, and “=” indicates connection between terminals.

In the above embodiment, the bit slide circuit 1 that slides the information bit of "1" to the lower side and slides the information bit of "0" to the upper side is described. D7 and output terminals E0 to E7
, The information bit of “1” can be slid to the upper side and the information bit of “0” can be slid to the lower side. That is, the input terminal D0 is for the most significant bit, the input terminal D7 is for the least significant bit, the output terminal E0 is for the most significant bit, and the output terminal E7 is for the least significant bit.

[Effect of the Invention] As described above in detail, according to the present invention, one information bit included in input 2-bit binary data is slid to the upper side or the lower side to convert the 2-bit binary data. A plurality of data conversion means for outputting each of the plurality of data bits, and sliding the information bits of one value included in the plurality of binary data inputted to the input terminal to the upper side or the lower side to output the plurality of binary data; The plurality of data conversion means are connected to each other, and each of the data conversion means determines whether to output data input to the second input terminal based on data input to the first input terminal. First gate means for switching; a first pull-down resistor for pulling down the output of the first gate means to "0" when the output of the first gate means is other than "1"; Input end An OR gate for performing a logical sum of the data input to the first and the data output from the first gate means and outputting data of a logical result to a first output terminal; and an OR gate based on the output data of the first gate means. Second gate means for switching whether or not to output data input to the second input terminal to the second output terminal; and when the output of the second gate means is other than "1", the second gate means Since it is provided with the second pull-down resistor for pulling down the output of the gate means to "0", the bit slide device can be realized with a simpler circuit than the conventional example.

Further, in addition to the bit slide device, coding for coding into binary data representing the number of information bits of one value included in the binary data based on the binary data output from the bit slide device Since the means is provided, a bit counting device can be realized with a simpler circuit than the conventional example.

[Brief description of the drawings]

FIG. 1 is a block diagram of a bit counting device according to one embodiment of the present invention, FIG. 2 is a circuit diagram of a data conversion circuit of FIG. 1, and FIG. 3 is a block diagram showing another embodiment. 1. Bit slide circuit, 2. Encoder with priority, 10-1 to 10-28 Data conversion circuit.

Continued on the front page (72) Inventor Ryo Fukui 1-3-6 Nakamagome, Ota-ku, Tokyo Inside Ricoh Company (72) Inventor Kazuho Sakamoto 1-3-6 Nakamagome, Ota-ku, Tokyo Co., Ltd. Ricoh (72) Inventor Masafumi Tanaka 1-3-6 Nakamagome, Ota-ku, Tokyo Ricoh Co., Ltd. (56) References JP-A-64-22323 (JP, A) JP-A-55-33223 (JP) , A) (58) Field surveyed (Int. Cl. ⁶ , DB name) G06F 7/00-7/04 G06F 7/24

Claims (5)

(57) [Claims] A plurality of data conversion means having first and second input terminals and first and second output terminals for inputting and outputting data in accordance with the following truth table; Are connected so that the logical relationship shown in the table below can be obtained. Each of the data conversion means includes: first gate means for switching whether to output data input to a second input terminal based on data input to a first input terminal; and A first pull-down resistor for pulling down the output of the first gate means to "0" when the output of the means is other than "1"; data inputted to the first input terminal and the first gate; An OR gate that performs a logical sum of data output from the means and outputs data of a logical result to a first output terminal; and an OR gate that outputs data input to a second input terminal based on output data of the first gate means. Second gate means for switching whether or not to output to the second output terminal; and when the output of the second gate means is other than "1", the output of the second gate means is pulled down to "0". Second pulldown Bit slide apparatus characterized by comprising an anti-city. 2. A plurality of data conversion means for sliding information bits of one value included in input 2-bit binary data to an upper side or a lower side to output 2-bit binary data, respectively. The plurality of data bits are output so that one value information bit included in the multi-bit binary data input to the input terminal is slid to the upper side or the lower side to output the multi-bit binary data to the output terminal. A first gate means for connecting the conversion means, wherein each of the data conversion means switches whether or not to output the data input to the second input terminal based on the data input to the first input terminal; A first step of pulling down the output of the first gate means to "0" when the output of the first gate means is other than "1";
An OR gate for performing a logical sum of the data input to the first input terminal and the data output from the first gate means, and outputting a logical result data to the first output terminal; A second gate means for switching whether or not to output data input to the second input terminal to the second output terminal based on output data of the first gate means; and When the value is other than "1", the output of the second gate means is pulled down to "0".
A bit slide device comprising: a pull-down resistor. 3. A bit slide device for sliding an information bit of one value included in binary data of a plurality of bits to be inputted to an upper side or a lower side, wherein the information bit is inputted to first and second input terminals. A plurality of data conversion means for sliding the information bit of one value included in the binary data of two bits to the upper side or the lower side to output the binary data of two bits to the first and second output terminals. The input terminal of the least significant bit of the bit slide device is connected to the first input terminal of the first data conversion means, and the input terminal of the most significant bit of the bit slide device is connected to the second input terminal.
Connected to the second input terminal of the data conversion means, and connected to the output terminal of the least significant bit of the bit slide device to the first output terminal of the first data conversion means. An output terminal of the upper bit is connected to a second output terminal of the third data conversion means, and each of the data conversion means is input to a second input terminal based on data input to the first input terminal. First gate means for switching whether or not to output data to be output, and a second means for pulling down the output of the first gate means to "0" when the output of the first gate means is other than "1". 1
An OR gate for performing a logical sum of the data input to the first input terminal and the data output from the first gate means, and outputting a logical result data to the first output terminal; A second gate means for switching whether or not to output data input to the second input terminal to the second output terminal based on output data of the first gate means; and When the value is other than "1", the output of the second gate means is pulled down to "0".
A bit slide device comprising: a pull-down resistor. 4. The bit slide device according to claim 1, wherein said first and second gate means are transmission gates. 5. The bit slide device according to claim 1, 2, 3 or 4, and the binary data included in the binary data based on the binary data output from the bit slide device. Encoding means for encoding binary data representing the number of information bits of one value and outputting the binary data.