JPS5829917B2 - Weyl code encoding circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a facsimile signal encoding circuit, and particularly to an improvement of the encoding circuit using a fill encoding method.

As a method for shortening the transmission time of facsimile signals, a method is known in which a long run length of white or black pixels is encoded and transmitted.

In this case, variable-length coding is effective in increasing conversion efficiency by giving short codes to run lengths that occur frequently and long codes to run lengths that occur less frequently. It is known.

A fill encoding method is well known as such an encoding method.

FIG. 1 shows fill codes depending on the length of the run length.

(For the fill encoding circuit, H, Wyle, T
, Erb, R-Banow-ReducedT
ime Facsimile Transmissi
on by Digi-tal Coding,
IRF Trans, page C8215 (Sep.

1961) and US Pat. No. 3,061,672.

) In FIG. 1, the address code is a code that predicts the code length of the subsequent reminder code, and the reminder code represents a run length code corresponding to the run length.

The code length of the address code is 1 bit when the run length is 1 to 4, and n bits when the run length is 2n+1 to 2n+1 (where n≧2).

Once the address code length is determined, the address code is uniquely determined as shown in FIG.

The reminder code is obtained by subtracting 1 from the run length, converting it into a binary number, and deleting the highest bit.

Further, the code length is equal to the code length of the address code.

However, in the case of a run length of 1 to 4, the highest bit of the binary number obtained by the above operation is not omitted and is divided into 2 bits.

Therefore, in this case, the code length is 2 bits.

As a result, the total code length is as shown in the fourth column.

Decoding of the fill code is performed by the reverse procedure of encoding.

If the first bit of the address code is 0'', this is the only address code, and the following 2-bit code is the reminder code.

If the first bit of the address code is 111", the address code has subsequent bits, so after remembering that there was one bit of the address code, read the next code, and when this is 110", the address code is finished. However, the code length of the address code is 2 bits.

Therefore, the code length of the reminder code is found to be 2 bits, and the following 2-bit code is stored.

As mentioned earlier, the highest bit of the reminder code has been deleted, so the memory code will be replaced with a pad at the beginning of the two memorized bits.
” code is added.

This 3-bit binary number represents the run length minus 1.

Similarly, look at the address code delimiter "pa0" and
The chord length is memorized, and the chord that follows the chord section is memorized, and a 1" code is added to the beginning of the chord.

This is the run length minus 1, plus 1
If you add , the run length will be reproduced.

FIG. 2 is an example of a fill encoding circuit.

First, a signal to be encoded is inputted from the terminal 8 and quantized via the AND gate 7 in units of sampling pulses 9.

That is, m pulses representing the length of white or black of the facsimile signal, that is, the run length m, are obtained as the output 10 of the facsimile signal.

10 is a binary signal 11 which is led to a binary counter 1 and represents m.
is converted to

The binary signal 11 thus converted is input to a code matrix 2 and a code length matrix 3.

2 immediately outputs a signal 12 representing each bit of the fill code corresponding to input 11.

3 immediately creates a binary number representing the code length corresponding to input 11 and outputs signal 13.

After counting m pulses, a write pulse is applied from the terminal 15 to transfer the signal 12 to the register 4 in parallel.

Next, the contents of the register 4 are shifted in accordance with a shift pulse inputted from the terminal 16, and a fill code is outputted to the terminal 14.

At the same time, a shift pulse 16 is applied to the binary counter 6 and 14
Count the number of bits output to .

The counted value is output as a signal 17 to the matching circuit 5.

The matching circuit 5 compares the signals 17 and 13, and when they match, outputs a matching pulse 18, indicating that all the fill codes have been read out, clears the binary counters 1 and 6, and returns the encoder to the encoder circuit. is cleared, the system returns to the initial state, and one cycle of code conversion processing is completed.

Although the encoding circuit described above can be said to be a versatile encoding circuit that can be applied not only to fill encoding circuits but also to any other run-length encoding method, it has a major drawback.

The problem is that the code matrix and code length matrix require very large hardware.

Let us consider a case where the maximum run length is 1024, assuming that a read-only memory (ROM) is used as a method for realizing this matrix.

From Figure 1, the run length is 1024, and the code length of the fill code is 18 bits, the binary number representing the code length requires 5 bits, and the binary counter required to count up to 1024 requires 10 bits. .

Therefore, the ROM capacity required for the code matrix is 2
The capacity of the ROM required for the 10×18 bits is approximately 18 bits, and the ROM capacity required for the code length matrix is 210×5 bits, approximately 5 bits, making a total of 23 bits.

When the maximum run length is between 1025 and 2048, the required ROM capacity is approximately 50 bits.

An object of the present invention is to provide a practical encoding circuit that uses a simple and economical configuration by focusing on the regularity of code assignment that fill codes have.

An embodiment of the present invention will be described in detail below.

In this actual MflJ, the maximum run length is 20
48 cases were shown.

FIG. 3 is a block diagram of a fill encoding circuit according to the present invention.

101 is the run length of the signal to be encoded 201 and the sampling unit clock pulse 202 minus 1, which is 2.
A counting unit converts into a base number and outputs run length information 206, 102 is code information 20 for creating an address code and a reminder code from the run length information 206.
8, 103 is run length information 206
This is a code synthesis unit that synthesizes a fill code 204 from the code information 208 and the code information 208.

203 is a code request pulse, 205 is a reset pulse for resetting the binary counter included in 101, 207 is an address code and reminder code sending end pulse, and 221 is a code sending start.

FIG. 4 shows a specific configuration of the counting section 101.

201 and 202 are quantized via an AND gate 104.

That is, a pulse 209 indicating the run length is obtained as the output of 104.

Flip-flop 105 and AND gate 106 function to subtract one from the run length.

That is, the flip-flop 105, which is in the reset state in the initial state, is set by the first pulse of 209, and 210 is set to O.
It might become 1.

209 and 210 are 11-digit counter 1 via 106
07 clock pulse 211.

Since 211 has the first pulse of 209 masked by 210, 107 counts the run length minus 1.

The output of each digit of 107 is output as run length information 206.

However, 206-a is the output of the first digit of 107, and in the following order: ep dy e, L gy hp l, j and 1
The output of each digit of 07 is output, and 206- is the 1 of 107.
This is the output of the first digit.

Reset pulse 205 when all fill codes are sent
After that, 105 and 107 return to their initial states and are ready for a new encoding request.

FIG. 5 shows a specific configuration of the control section 102.

108 is a converter from decimal to binary, which selects logic level 1 of the highest input terminal among the logic levels input to input terminals 1 to 9, and converts the binary complement of that input terminal number. It functions to output from output terminals A to DK.

FIG. 6 shows this conversion rule.

114 is a 4-digit counter that can be input in parallel.

Run length information (204-c) to (206-k) is 1
08, the rosinf level 10 input is examined among each input, and the maximum digit in the input is determined and converted into the binary complement number 212-215 corresponding to the maximum digit.

Therefore, it is converted into these outputs 212-215.

Therefore, the outputs 212 to 215 represent the complement of the code length number of the run length address code minus one.

However, 215 is the upper digit.

212 to 215 are also used when creating the complement of the code length of the reminder code.

As can be seen from Figure 1, the code length of the reminder code is equal to the code length of the address code, except for run lengths 1 to 4, so run lengths 1 to 4 are used.
It is only necessary to set the code length to 2 in cases up to .

This conversion is performed by Nant gate 110, AND gate 112, and flip-flop 109.

The operation will be explained in more detail using the case where the run length is 60 as a column.

FIG. 7 is a time chart of each signal.

Now, the run length 60 is converted into a binary number representing 59 by 101, and the run length information 206 becomes "00000111011" in order from the upper bit.

The lower two bits 206a of the run length information 206,
'000001110'' excluding b is converted by 108 and becomes 215, 214, 213, 212, which is the binary number of the code length (5 bits) of the address code minus 1, that is, the 4's complement number.

"l O11" is obtained.

In the initial state, the flip-flop 109 is reset and its output 216 is "O".

Therefore, the output 219 of the Nant gate 110 becomes 1'', and the output 220 of the AND gate 112 becomes the same signal as 212.

When the code transmission start pulse 221 is input from the outside, the polarity is reversed through the NOR gate 113 and the load pulse 218 is output.
is input to the parallel input counter 114, and 114
is set to "1011".

At the same time, 109 is also set, and 216 becomes tt 1pp, preparing for setting the chord length of the next main chord.

The counter 114 counts +1 each time the code request pulse 203 is received, and stores the counted contents in the code information 20.
Output as 8.

When all the signals of 208 are 1'1'', the final bit of the address code is prepared, and when the final bit is read out with the next pulse of 203 (see Figures 8 to 10 described later),
All 208 become 'O', and address code transmission is completed.

The signal 208 is converted by the code synthesis unit 103 and returned as the sending pulse end signal 207.

207 is input to 114 as 21B whose polarity is inverted via 113, and "1011" is set in the counter again.

Below, in the same way as for the address code, counting is carried out in synchronization with 203, and code information 208 is sent out, and all 208 are tt.
When it becomes Oll, transmission of all fill codes (described later) ends.

The reason why 114 is loaded again at this time is to prevent 207 from being reset forever if 208 is all "O" and 207 becomes at 1pp.

Next, the operation when the run length is 1 to 4, which makes the reminder code special, will be explained.

Here, the case of run leg 4 will be taken as an example.

Run length 4 is converted by 101 and run length information 2
06 is output as "00000000011".

206 is "ooooooooooo" excluding the lower 2 bits.
” is input to 108 and converted to 212-215”
1111”.

Since 109 is set for the address code, 2
Since 16 is l'' and 213 to 215 are 1'', the output 219 of the Nantes gate 110 is at Opp,
220 becomes tt O'' via 212.

Therefore, "1110" is set in 114, and the code length of the address code can be set to 2 bits.

In the case of a remaining goo code, it works the same as the previous column.

FIG. 8 shows a specific configuration of the code synthesis section 103.

Reference numeral 111 is a well-known 10-bit selector which selects one of the input signals 16 to 16 corresponding to the value indicating the inputs A-D as the output Y.

This relationship is shown in FIG.

Reference numeral 117 is a flip-flop for distinguishing between an address code and a reminder code, and its state changes at the fall of the input signal 207 to the CP, and the initial state is the output 22.
3 is tt On output 224 is '1''.

Here, as in the case of the control unit 102, the run length is 60.
The operation will be explained using the case of .

FIG. 10 shows the time chart.

The run length counting has already been completed, and the run length information (206-j) to (206-a) contains "0000111011", and the code information (208-d)
) to (208-a) are given "1011", respectively.

Since 117 is in the initial state, 223 is "O" and 224 is "1".

When the code information 208 includes even one 0'', ul'' is output to the output 222 of the Nantes gate 116, and 20
When all 8 are tt 1pp, 'O'' is output,
Therefore, an address code of "11110" is output.

This output 222 is output as an address code 204 via an AND gate 120 and an OR gate 121.

When all the signals 208 are turned on, a sending end pulse 207 is outputted through the NOR gate 115, and the state of the flip-flop 117 changes so that 223 becomes 1'' and 224 becomes 0.

Corresponding to the contents of 208, 111 selects one signal from inputs 206a to 206j and outputs it as main code 217.

217 is output as code 204 via AND gates 119 and 121.

When all the signals 208 are turned on, the signal 207 is outputted via the NOR gate 115.

At this time, since 223 is 1'', a reset pulse 205 is outputted through the Nant gate 118, and at the same time, 117 is returned to its initial state, and the transmission of the fill code is completed.

As explained above, the present invention significantly simplifies the creation of codes and code length information by utilizing the characteristics of the fill encoding method, and also by configuring the address code and reminder code to be created sequentially, the code The sending circuit has also been simplified to make it more economical.

Not only is it significantly simpler than the above-mentioned US Pat. No. 3,061,672, but it can also be realized at about one-tenth the cost compared to the case shown in FIG.

[Brief explanation of the drawing]

FIG. 1 shows the code for each run length of the fill encoding method, FIG. 2 is a block diagram of a conventional fill encoding circuit, FIG. 3 is a block diagram of one embodiment of the present invention, and FIGS. Figures 5 and 8 are detailed circuit diagrams of Figure 3, and Figure 6 is a detailed circuit diagram of Figure 3.
The figure shows the conversion rule of the converter 108 shown in FIG. 5, FIG. 7 is a time chart of each signal line in FIG.
The figure shows the relationship between the input and output signals of the selector 111 shown in FIG. 8, and FIG. 10 is a time chart of each signal line in FIG. 8. 101 is a counting section, 102 is a control section, 103 is a code synthesis section for synthesizing fill codes, 105 is a flip-flop, 1
07 is a counter, 108 is a decimal number to binary number converter, 109 is a flip-flop, 114 is a counter, 111 is a 10-bit selector, 117 is a flip-flop, 201 is a signal to be encoded, 202 is a clock pulse, 203 204 is a fill code output, 205 is a run-length counter reset pulse, 206 is a parallel signal representing run-length information, 207 is an address code and reminder code sending end pulse, 221 is a code request pulse input from the outside, To the code transmission start pulse input from the outside

Claims (1)

[Scope of Claims] 1. In a fill code encoding circuit that converts a human run-length code into a fill code composed of an address code and a main code,
a counting means for counting a number obtained by subtracting 1 from the number of concatenations of t Opp; means for generating a control signal corresponding to the code length of the address code and the reminder code based on the output of the counting means; and the control signal. means for generating a first control signal group consisting of the same number of control signals as the code length of the address code and a second control signal group consisting of the same number of ff51# signals as the code length of the reminder code in response to the address code; , address code creation means for creating the address code in response to each control signal of the first control signal group; and means for creating the reminder code in response to each control signal of the second control signal group. A fill code encoding circuit comprising: