JP2765566B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JP2765566B2 JP2765566B2 JP13722796A JP13722796A JP2765566B2 JP 2765566 B2 JP2765566 B2 JP 2765566B2 JP 13722796 A JP13722796 A JP 13722796A JP 13722796 A JP13722796 A JP 13722796A JP 2765566 B2 JP2765566 B2 JP 2765566B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- compound semiconductor
- semiconductor device
- layer
- water
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims description 32
- 238000000034 method Methods 0.000 title claims description 23
- 238000004519 manufacturing process Methods 0.000 title claims description 13
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 24
- 150000001875 compounds Chemical class 0.000 claims description 19
- 230000005669 field effect Effects 0.000 claims description 12
- 230000001681 protective effect Effects 0.000 claims description 12
- 238000005406 washing Methods 0.000 claims description 11
- 239000000758 substrate Substances 0.000 claims description 8
- 229910052785 arsenic Inorganic materials 0.000 claims description 7
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 7
- 239000008367 deionised water Substances 0.000 claims description 4
- 229910021641 deionized water Inorganic materials 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 4
- 239000010410 layer Substances 0.000 description 41
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 24
- 229910052751 metal Inorganic materials 0.000 description 12
- 239000002184 metal Substances 0.000 description 12
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 8
- KRKNYBCHXYNGOX-UHFFFAOYSA-N citric acid Chemical compound OC(=O)CC(O)(C(O)=O)CC(O)=O KRKNYBCHXYNGOX-UHFFFAOYSA-N 0.000 description 6
- 238000010894 electron beam technology Methods 0.000 description 6
- 238000005530 etching Methods 0.000 description 6
- 239000001301 oxygen Substances 0.000 description 6
- 229910052760 oxygen Inorganic materials 0.000 description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 4
- 239000000203 mixture Substances 0.000 description 4
- 238000010306 acid treatment Methods 0.000 description 3
- 238000009832 plasma treatment Methods 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- 239000002253 acid Substances 0.000 description 2
- 230000002411 adverse Effects 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 238000001451 molecular beam epitaxy Methods 0.000 description 2
- 150000002926 oxygen Chemical class 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 239000003870 refractory metal Substances 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- NWUYHJFMYQTDRP-UHFFFAOYSA-N 1,2-bis(ethenyl)benzene;1-ethenyl-2-ethylbenzene;styrene Chemical compound C=CC1=CC=CC=C1.CCC1=CC=CC=C1C=C.C=CC1=CC=CC=C1C=C NWUYHJFMYQTDRP-UHFFFAOYSA-N 0.000 description 1
- 229910005191 Ga 2 O 3 Inorganic materials 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000003456 ion exchange resin Substances 0.000 description 1
- 229920003303 ion-exchange polymer Polymers 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
- 230000005533 two-dimensional electron gas Effects 0.000 description 1
Landscapes
- Junction Field-Effect Transistors (AREA)
- Electrodes Of Semiconductors (AREA)
- Weting (AREA)
Description
【0001】[0001]
【発明の属する技術分野】本発明は化合物半導体を用い
た半導体装置の製造方法、特にリセス構造を有する化合
物半導体電界効果トランジスタの製造方法に関する。The present invention relates to a method for manufacturing a semiconductor device using a compound semiconductor, and more particularly to a method for manufacturing a compound semiconductor field effect transistor having a recess structure.
【0002】[0002]
【従来の技術】GaAsを用いたMESFET(金属−
半導体電界効果トランジスタ)やAlx Ga1-x As
(0<x<1)等を用いたHJFET(異種接合電界効
果トランジスタ)においては、ゲート−ソース間の抵抗
を小さくするために、チャネル層の上部にGaAs等の
高ドープ低抵抗層(コンタクト層)を設けておき、フォ
トレジストをマスクにしてゲート部のコンタクト層をチ
ャネル層までエッチング除去してゲート形成を行ういわ
ゆるリセスゲート方式が一般的である。2. Description of the Related Art MESFETs using GaAs (metal-
Semiconductor field effect transistor) and Al x Ga 1-x As
In an HJFET (heterojunction field effect transistor) using (0 <x <1) or the like, a highly doped low-resistance layer (contact layer such as GaAs) such as GaAs is formed on the channel layer in order to reduce the resistance between the gate and the source. ) Is provided, and a gate is formed by etching and removing a contact layer of a gate portion to a channel layer using a photoresist as a mask.
【0003】この従来技術について例をあげて説明す
る。[0003] This prior art will be described with an example.
【0004】例えば、特開平7−86309号公報に記
載されているように、半絶縁性GaAs基板(図5の
1)に高純度GaAsバッファ層2、n型Alx Ga
1-x As電子供給層3及びn型GaAsコンタクト層4
を順次に堆積して化合物半導体基板を準備する。次にソ
ースおよびドレイン用オーミック電極(ソース電極6,
ゲート電極7)をリフトオフ法で形成する。For example, as described in JP-A-7-86309, a high-purity GaAs buffer layer 2 and an n-type Al x Ga
1-x As electron supply layer 3 and n-type GaAs contact layer 4
Are sequentially deposited to prepare a compound semiconductor substrate. Next, ohmic electrodes for source and drain (source electrodes 6,
The gate electrode 7) is formed by a lift-off method.
【0005】次にAlx Ga1-x AsとGaAsを等速
度を削るウェットエッチングまたはドライエッチング、
あるいはGaAsに比べてAlx Ga1-x Asを削る速
度が極めて小さい選択性ウェットエッチングまたはドラ
イエッチングによりリセス構造を形成し、金属ゲートを
蒸着・リフトオフ法により形成する。このリフトオフに
使用したレジスト膜を剥離液を用いて除去し、酸素プラ
ズマ処理を行なう。このとき自然酸化膜や酸素プラズマ
によってAlx Ga1-x As層3表面に形成された酸化
膜を塩酸処理により除去してから、リセス開口部表面安
定化のための表面保護膜を成膜し、電極部を開口して完
成する。[0005] Next, wet etching or dry etching of Al x Ga 1 -x As and GaAs at a constant speed,
Alternatively, a recess structure is formed by selective wet etching or dry etching in which the rate of removing Al x Ga 1 -x As is extremely small as compared with GaAs, and a metal gate is formed by a vapor deposition / lift-off method. The resist film used for the lift-off is removed using a stripper, and oxygen plasma treatment is performed. At this time, a natural oxide film or an oxide film formed on the surface of the Al x Ga 1 -x As layer 3 by oxygen plasma is removed by hydrochloric acid treatment, and then a surface protective film for stabilizing the surface of the recess opening is formed. Then, the electrode portion is opened to complete.
【0006】ゲート金属材料としては、低抵抗でAlx
Ga1-x As電子供給層3との界面が安定なAl(アル
ミニウム)を用いたり、Alx Ga1-x Asと直接接触
する部分をMo膜9−1等の電子銃蒸着の可能な高融点
金属とし、この上にゲート抵抗低減のためにAu膜9−
4を厚く堆積させる方法が広く用いられている。この場
合は、Au膜と高融点金属との接着をよくするために、
両金属の間にはTi膜9−2とPt膜9−3の2層構造
を挟んだ構造にすることが一般的である。[0006] As a gate metal material, low resistance Al x
Al (aluminum) having a stable interface with the Ga 1-x As electron supply layer 3 is used, or a portion in direct contact with the Al x Ga 1-x As is formed at a high level where the electron gun vapor deposition such as the Mo film 9-1 can be performed. A melting point metal, and an Au film 9-
4 is widely used. In this case, to improve the adhesion between the Au film and the refractory metal,
In general, a two-layer structure of a Ti film 9-2 and a Pt film 9-3 is sandwiched between the two metals.
【0007】[0007]
【発明が解決しようとする課題】リセス構造電界効果ト
ランジスタは、素子特性の安定化のために、リセス開口
部に表面保護膜を堆積させることが一般的に行なわれて
いる。In a field effect transistor having a recess structure, a surface protective film is generally deposited on a recess opening in order to stabilize device characteristics.
【0008】表面保護膜は素子特性に大きく影響を及ぼ
すことが知られており、特に保護膜とリセス開口部半導
体表面との界面が清浄であることが、漏れ電流の少ない
良好な素子特性をもたらす。実際には、保護膜成長前の
段階で、リセス開口部表面のAlx Ga1-x As層に
は、酸化膜が意図せず形成されているので、これを除去
する必要がある。It is known that a surface protective film greatly affects device characteristics. In particular, a clean interface between the protective film and the semiconductor surface of the recess opening results in good device characteristics with little leakage current. . Actually, an oxide film is unintentionally formed in the Al x Ga 1 -xAs layer on the surface of the recess opening before the protective film is grown, and it is necessary to remove the oxide film.
【0009】従来の問題点は、表面保護膜成膜の前処理
として塩酸処理を行なうと、ゲート電極材料のAlやT
iが浸食されて、ゲートの破損原因となることである。
その理由は、AlやTiが塩酸の酸化作用をうけ易いこ
とにある。The conventional problem is that when a hydrochloric acid treatment is performed as a pretreatment for forming the surface protective film, Al or T
i is eroded, causing damage to the gate.
The reason is that Al and Ti are easily oxidized by hydrochloric acid.
【0010】Al単層膜でゲート電極を形成する場合に
は、この塩酸処理によって形状変化がおこったり若しく
はAlx Ga1-x As層からはがれる原因となる。また
高融点金属膜とAl膜の接着をよくするためのTi膜9
−2が図5に示すように浸食された場合は、高融点金属
膜(9−1)とAu膜9−4が分離しやすくなり、ゲー
ト電極の機械的破損の原因となり易い。When the gate electrode is formed of an Al single layer film, the hydrochloric acid treatment causes a shape change or peels off from the Al x Ga 1 -x As layer. Also, a Ti film 9 for improving the adhesion between the refractory metal film and the Al film.
When -2 is eroded as shown in FIG. 5, the high melting point metal film (9-1) and the Au film 9-4 are easily separated, which is likely to cause mechanical damage to the gate electrode.
【0011】本発明の目的は、ゲート電極に悪影響を与
えることなく保護膜形成前の酸化膜除去を行なえる電界
効果トランジスタ形成工程を含む半導体装置の製造方法
を提供することにある。It is an object of the present invention to provide a method of manufacturing a semiconductor device including a field effect transistor forming step capable of removing an oxide film before forming a protective film without adversely affecting a gate electrode.
【0012】[0012]
【課題を解決するための手段】本発明の第1の半導体装
置の製造方法は、リフトオフ法により、ヒ素を含む化合
物半導体層に接触するショットキーゲート電極を形成す
る際に、前記リフトオフ法用のレジスト膜を除去した後
に前記化合物半導体層表面の酸化膜を水洗処理で除去
し、ついで表面保護膜を被着する電界効果トランジスタ
形成工程を含むというものである。According to a first method of manufacturing a semiconductor device of the present invention, when forming a Schottky gate electrode in contact with a compound semiconductor layer containing arsenic by a lift-off method, the method for the lift-off method is used. After the resist film is removed, an oxide film on the surface of the compound semiconductor layer is removed by a water washing treatment, and then a field effect transistor forming step of applying a surface protective film is included.
【0013】本発明第2の半導体装置の製造方法は、化
合物半導体基板の表面にレジスト膜パターンを形成し、
前記レジスト膜パターンをマスクとして前記化合物半導
体基板をエッチングしてリセス部を形成してその底面に
ヒ素を含む化合物半導体層を露出させ、導電膜を堆積し
前記レジスト膜パターンとその上部の前記導電膜を除去
してショットキーゲート電極を形成する工程と、水洗処
理を行ない前記ショットキーゲート電極で選択的に被覆
された化合物半導体層表面の酸化膜を除去する工程と、
表面保護膜を被着する工程とを有するというものであ
る。According to a second method of manufacturing a semiconductor device of the present invention, a resist film pattern is formed on a surface of a compound semiconductor substrate.
The compound semiconductor substrate is etched using the resist film pattern as a mask to form a recessed portion, exposing a compound semiconductor layer containing arsenic on the bottom surface, depositing a conductive film, and forming the resist film pattern and the conductive film on the resist film pattern. Removing the oxide film on the surface of the compound semiconductor layer selectively covered with the Schottky gate electrode by performing a water washing process,
And a step of applying a surface protective film.
【0014】ヒ素を含む化合物半導体層は、Aly Ga
1-y As層(0≦y≦1)であってもよい。The compound semiconductor layer containing arsenic is Al y Ga
It may be a 1-y As layer (0 ≦ y ≦ 1).
【0015】水洗処理は脱イオン水又は電解イオン水で
行なうことができる。The washing process can be performed with deionized water or electrolytic ionized water.
【0016】ショットキー電極で選択的に被覆されたヒ
素を含む化合物半導体層表面の酸化膜は水により除去さ
れる。この酸化膜は水溶性のAs2 O3 などを含む混合
物と考えられるので、水に殆んど溶けない酸化物も同時
に除去される。The oxide film on the surface of the compound semiconductor layer containing arsenic selectively covered with the Schottky electrode is removed by water. Since this oxide film is considered to be a mixture containing water-soluble As 2 O 3 and the like, oxides that are almost insoluble in water are also removed.
【0017】[0017]
【発明の実施の形態】次に、本発明の第1の実施の形態
について説明する。Next, a first embodiment of the present invention will be described.
【0018】まず、図1(a)に示すように、半絶縁性
GaAs基板1上に厚さ600nmのアンドープの高純
度GaAsバッファ層2、厚さ40nmでSiドープ
(Nd=2×1018cm-3)のn型Alx Ga1-x As
電子供給層3、厚さ80nmでSiドープ(Nd=3.
5×1018cm-3)のn型GaAsコンタクト層4を順
に周知の分子線エピタキ(MBE)法を用いてエピタキ
シャル結晶成長する。n型Alx Ga1-x As電子供給
層3のAl組成比xは0.25とした。First, as shown in FIG. 1A, an undoped high-purity GaAs buffer layer 2 having a thickness of 600 nm is formed on a semi-insulating GaAs substrate 1, and a Si-doped layer (Nd = 2 × 10 18 cm) is formed with a thickness of 40 nm. -3 ) n-type Al x Ga 1 -x As
The electron supply layer 3 is 80 nm thick and is Si-doped (Nd = 3.
An n-type GaAs contact layer 4 of 5 × 10 18 cm −3 ) is epitaxially grown in sequence using a well-known molecular beam epitaxy (MBE) method. The Al composition ratio x of the n-type Al x Ga 1 -x As electron supply layer 3 was set to 0.25.
【0019】次に、周知のフォトリソグラフィー法とリ
フトオフ法を用いてAlGeNi蒸着膜からなるソース
電極6およびドレイン電極7を形成する。ソース電極6
およびドレイン電極7は、AlGeNi蒸着膜形成後、
約400℃のH2 雰囲気中でAuGeNi蒸着膜とn型
GaAsコンタクト層4を合金化させ、低抵抗のオーム
接合を形成した。Next, a source electrode 6 and a drain electrode 7 made of a vapor-deposited AlGeNi film are formed by using a well-known photolithography method and a lift-off method. Source electrode 6
And the drain electrode 7 are formed after forming the AlGeNi deposited film.
The AuGeNi vapor-deposited film and the n-type GaAs contact layer 4 were alloyed in an H 2 atmosphere at about 400 ° C. to form a low-resistance ohmic junction.
【0020】次いで、図1(b)に示す様に、電子線レ
ジスト膜に電子線露光装置を使ってゲート電極長Lgを
0.2μmとするために、0.2μmの開口を設けてレ
ジスト膜パターン8を形成し、GaAsとAlx Ga
1-x Asの選択比が大きいBCl3 およびSF6 の混合
ガスのプラズマを用いて、この開口部のn型GaAs層
4のイオンエッチングを行なう。この時、GaAsのエ
ッチングレートをAlxGa1-x Asのエッチングレー
トの100倍程度以上とすることにより、n型Alx G
a1-x As電子供給層3をほとんどエッチングすること
なくリセス部10を形成することができる。Next, as shown in FIG. 1B, an opening of 0.2 μm is provided in the electron beam resist film by using an electron beam exposure apparatus so that the gate electrode length Lg is 0.2 μm. A pattern 8 is formed, and GaAs and Al x Ga
Using a plasma of a mixed gas of BCl 3 and SF 6 having a high 1-x As selectivity, ion etching of the n-type GaAs layer 4 in this opening is performed. At this time, by setting the etching rate of GaAs to about 100 times or more the etching rate of Al x Ga 1 -x As, the n-type Al x G
The recess portion 10 can be formed without substantially etching the a 1-x As electron supply layer 3.
【0021】次に、図1(c)に示す様に、ゲート金属
を蒸着した後にレジスト膜パターン8を除去することに
より、電子線レジスト膜上のゲート金属がリフトオフさ
れて、図1(d)に示すように、ゲート電極9が形成さ
れる。ゲート金属はAl膜11を300nm蒸着した。
電子線レジスト膜を除去する際には、剥離液に浸したの
ち、酸素プラズマ処理を行なうが、この酸素プラズマ処
理により、リセス部のAlx Ga1-x As膜(3)表面
に酸化膜(図示しない)が意図せず形成される。Next, as shown in FIG. 1C, by removing the resist film pattern 8 after depositing the gate metal, the gate metal on the electron beam resist film is lifted off, and as shown in FIG. A gate electrode 9 is formed as shown in FIG. As the gate metal, an Al film 11 was deposited to a thickness of 300 nm.
When the electron beam resist film is removed, it is immersed in a stripping solution and then subjected to oxygen plasma treatment. By this oxygen plasma treatment, an oxide film (3) is formed on the surface of the Al x Ga 1 -x As film (3) in the recess. (Not shown) are formed unintentionally.
【0022】その後、水洗処理によりリセス部のAlx
Ga1-x As膜表面酸化膜を除去したのち、図2に示す
ように、表面保護膜としてSiO2 膜12をCVD法に
より100nm堆積して電界効果トランジスタが完成す
る。水洗処理に用いたのは通常のイオン交換樹脂を用い
て製造された電気比抵抗17MΩ・cm(25℃)のも
の(脱イオン水)である。Thereafter, the Al x in the recessed portion is washed with water.
After removing the oxide film on the surface of the Ga 1-x As film, as shown in FIG. 2, an SiO 2 film 12 is deposited as a surface protective film to a thickness of 100 nm by a CVD method to complete the field effect transistor. What was used for the water-washing process was one having an electrical resistivity of 17 MΩ · cm (25 ° C.) (deionized water) manufactured using a normal ion exchange resin.
【0023】表面酸化膜は、水に溶けるAs2 O3 を含
んだ混合物と考えられるので、殆ど水に溶けないAl2
O3 やGa2 O3 なども同時に除去されると思われる。
リセス部のAlx Ga1-x As膜表面酸化膜を酸を用い
ず水洗処理を用いて除去するためゲート金属のAlが浸
食されることなく、漏れ電流の少ない整流性の良いショ
ットキーゲート電極を再現性よく形成でき、従来の製造
方法と比べて電界効果トランジスタの歩留まりは10%
以上向上した。Since the surface oxide film is considered to be a mixture containing As 2 O 3 which is soluble in water, Al 2 which is hardly soluble in water is used.
It is considered that O 3 and Ga 2 O 3 are also removed at the same time.
The Alx Ga1-x As film surface oxide film in the recess is removed by washing with water without using acid. Al of the gate metal is not eroded, and a rectifying Schottky gate electrode with low leakage current is reproduced. And the yield of the field effect transistor is 10% as compared with the conventional manufacturing method.
This has improved.
【0024】次に、本発明の第2の実施の形態について
説明する。Next, a second embodiment of the present invention will be described.
【0025】まず、図3(a)に示すように、第1の実
施の形態と同様に半絶縁性GaAs基板1A上に厚さ5
00nmのアンドープの高純度GaAsバッファ層2
A、厚さ30nmでSiドープ(Nd=2×1018cm
-3)のn型Alx Ga1-x As電子供給層3A、厚さ7
0nmでSiドープ(Nd=3.5×1018cm-3)の
n型GaAsコンタクト層4Aを順に周知の分子線エピ
タキシ(MBE)法を用いてエピタキシャル結晶成長す
る。n型Alx Ga1-x As電子供給層3AのAl組成
比xは0.20とした。First, as shown in FIG. 3A, as in the first embodiment, a layer having a thickness of 5 mm is formed on a semi-insulating GaAs substrate 1A.
00 nm undoped high-purity GaAs buffer layer 2
A, 30 nm thick and Si-doped (Nd = 2 × 10 18 cm)
-3 ) n-type AlxGa1 - xAs electron supply layer 3A, thickness 7
An n-type GaAs contact layer 4A having a thickness of 0 nm and doped with Si (Nd = 3.5 × 10 18 cm −3 ) is epitaxially grown in sequence using a well-known molecular beam epitaxy (MBE) method. The Al composition ratio x of the n-type Al x Ga 1 -x As electron supply layer 3A was set to 0.20.
【0026】次に、周知のフォトリソグラフィー法とリ
フトオフ法を用いてAuGeNi蒸着膜からなるソース
電極6Aおよびドレイン電極7Aを形成する。ソース電
極6Aおよびドレイン電極7Aは、AuGeNi蒸着膜
形成後、約400℃のH2 雰囲気中でAuGeNiとn
型GaAsコンタクト層4Aを合金化させ、低抵抗のオ
ーム接合を形成した。Next, a source electrode 6A and a drain electrode 7A made of a deposited AuGeNi film are formed by using a well-known photolithography method and a lift-off method. The source electrode 6A and the drain electrode 7A after AuGeNi deposited film formation, AuGeNi and n in H 2 atmosphere of approximately 400 ° C.
The type GaAs contact layer 4A was alloyed to form a low-resistance ohmic junction.
【0027】次いで図3(b)に示す様に、電子線レジ
スト膜に電子線露光装置を使ってゲート電極長Lgを
0.2μmとするために0.2μmの開口を設けてレジ
スト膜パターン8Aを形成しGaAsとAlx Ga1-x
Asの選択比が大きいクエン酸系エッチャント(クエン
酸50%:H2 O2 30%=3:1)を用いて、この開
口部のn型GaAsのエッチングレートの100倍程度
以上とすることにより、n型Alx Ga1-x As電子供
給層3Aをほとんどエッチングすることなくリセス部1
0Aを形成することができる。Next, as shown in FIG. 3B, an opening of 0.2 μm is formed in the electron beam resist film by using an electron beam exposure apparatus so that the gate electrode length Lg is set to 0.2 μm. To form GaAs and Al x Ga 1-x
By using a citric acid-based etchant having a large As selectivity (citric acid 50%: H 2 O 2 30% = 3: 1), the etching rate of the n-type GaAs in the opening is set to be about 100 times or more. , N-type Al x Ga 1 -x As electron supply layer 3A
OA can be formed.
【0028】次に、図4(a)に示す様に、ゲート金属
を蒸着した後に、レジスト膜パターン8Aを除去するこ
とにより、図4(b)に示す様に、レジスト膜パターン
8A上のゲート金属がリフトオフされて、ゲート電極9
Aが形成される。ゲート金属は50nmのMo膜9−1
A、5nmのTi膜9−2A、5nmのPt膜9−3
A、400nmのAu膜9−4Aをこの順に蒸着した。
レジスト膜パターン8Aを剥離液を用いて除去し、酸素
プラズマ処理を行なうが、この酸素プラズマ処理によ
り、リセス部Alx Ga1-y As膜4A表面に図示しな
い酸化膜が意図せず形成される。Next, as shown in FIG. 4A, after depositing the gate metal, the resist film pattern 8A is removed, thereby forming the gate on the resist film pattern 8A as shown in FIG. 4B. The metal is lifted off and the gate electrode 9
A is formed. The gate metal is a 50 nm Mo film 9-1.
A, 5 nm Ti film 9-2A, 5 nm Pt film 9-3
A, a 400 nm Au film 9-4A was deposited in this order.
The resist film pattern 8A is removed using a stripping solution, and oxygen plasma processing is performed. By this oxygen plasma processing, an oxide film (not shown) is formed unintentionally on the surface of the recess Al x Ga 1-y As film 4A. .
【0029】その後、水洗処理によりリセス部Alx G
a1-x As膜4A表面酸化膜を除去したのち、図4
(c)に示すように表面保護膜12としてSi3 N4 膜
をCVD法により100nm堆積して電界効果トランジ
スタが完成する。水洗処理に用いたのは、pH1.7の
電解イオン水(電解アノード水)である。Thereafter, the recess portion Al x G is formed by washing with water.
After removing the surface oxide film of the a 1-x As film 4A, FIG.
As shown in (c), a Si 3 N 4 film is deposited as a surface protection film 12 by a CVD method to a thickness of 100 nm to complete the field effect transistor. What was used for the water washing process was electrolytic ionized water (electrolytic anode water) having a pH of 1.7.
【0030】この実施の形態では、リセス部Alx Ga
1-x As膜表面酸化膜を除去するのに酸を用いず水洗処
理を用いているため、ゲート金属のTi膜9−2Aが浸
食されることがないため、従来の製造方法と比べて電界
効果トランジスタの歩留りは従来と比べて10%以上向
上し、高歩留りで漏れ電流が少ない整流性の良いショッ
トキーゲート電極を有する電界効果トランジスタが得ら
れた。In this embodiment, the recess portion Al x Ga
Since the 1-x As film surface oxide film is washed with water without using an acid, the gate metal Ti film 9-2A is not eroded. The yield of the effect transistor was improved by 10% or more as compared with the conventional case, and a field effect transistor having a Schottky gate electrode having a high yield, a small leakage current and a good rectifying property was obtained.
【0031】以上説明したように、リセス部を形成する
ためのエッチングは反応性イオンエッチングあるいはウ
ェットエッチングのいずれを用いてもよく、水洗処理に
は脱イオン水あるいは電解イオン水のいずれを用いても
良好な結果が得られる。As described above, the etching for forming the recess may be performed by either reactive ion etching or wet etching, and the washing process may be performed by using either deionized water or electrolytic ionic water. Good results are obtained.
【0032】以上、電子供給層としてAlx Ga1-x 層
を有するHJFETを例にあげて説明したが、リセス部
にゲート電極をリフトオフ法で形成するFETの製造方
法において、リセス底面に露出する化合物半導体層の材
料としては、GaAs、AlAs、Inz Ga1-z As
などのようにAsを構成元素に有するものであれば本発
明を適用することができる。The HJFET having the Al x Ga 1-x layer as the electron supply layer has been described above as an example. However, in the method of manufacturing the FET in which the gate electrode is formed in the recess by the lift-off method, the HJFET is exposed at the bottom of the recess. As the material of the compound semiconductor layer, GaAs, AlAs, In z Ga 1 -z As
The present invention can be applied as long as it has As as a constituent element, such as.
【0033】[0033]
【発明の効果】以上説明したように本発明は、リフトオ
フ法を用いてリセス部にショットキーゲート電極を形成
した後、ショットキーゲート電極で選択的に被覆された
リセス底面の酸化膜を水洗処理により除去することによ
り、ショットキーゲート電極に浸食などの悪影響を与え
なくてすむので、漏れ電流の少ない良好な特性の電界効
果トランジスタを有する半導体装置を高歩留りで製造で
きるという効果がある。As described above, according to the present invention, after a Schottky gate electrode is formed in a recess portion using a lift-off method, an oxide film on the bottom surface of the recess selectively covered with the Schottky gate electrode is washed with water. As a result, the Schottky gate electrode is not adversely affected by erosion or the like, so that a semiconductor device having a field effect transistor with good characteristics and low leakage current can be manufactured at a high yield.
【0034】[0034]
【図1】本発明の第1の実施の形態について説明するた
めの(a)〜(d)に分図して示す工程順断面図。FIGS. 1A to 1D are cross-sectional views illustrating a first embodiment of the present invention in the order of steps, which are separately illustrated in FIGS.
【図2】図1に続いて示す断面図。FIG. 2 is a cross-sectional view shown after FIG. 1;
【図3】本発明の第2の実施の形態について説明するた
めの(a),(b)に分図して示す工程順断面図。FIGS. 3A and 3B are cross-sectional views in the order of steps, for explaining the second embodiment of the present invention.
【図4】図3に続いて(a)〜(c)に分図して示す工
程順断面図。FIG. 4 is a cross-sectional view in the order of steps, which is shown separately in FIGS.
【図5】従来例について説明するための断面図。FIG. 5 is a cross-sectional view for explaining a conventional example.
1,1A 半絶縁性GaAs基板 2,2A 高純度GaAsバッファ層 3,3A n型Alx Ga1-x As電子供給層 4,4A n型GaAsコンタクト層 5 2次元電子ガス 6,6A ドレイン電極 7,7A ソース電極 8,8A レジスト膜パターン 9,9A ゲート電極 9−1,9−1A Mo膜 9−2,9−2A Ti膜 9−3,9−3A Pt膜 9−4,9−4A Au膜Reference Signs List 1,1A semi-insulating GaAs substrate 2,2A high-purity GaAs buffer layer 3,3An n-type Al x Ga 1-x As electron supply layer 4,4An-type GaAs contact layer 5 Two-dimensional electron gas 6,6A Drain electrode 7 , 7A Source electrode 8, 8A Resist film pattern 9, 9A Gate electrode 9-1, 9-1A Mo film 9-2, 9-2A Ti film 9-3, 9-3A Pt film 9-4, 9-4A Au film
Claims (5)
半導体層に接触するショットキーゲート電極を形成する
際に、前記リフトオフ法用のレジスト膜を除去した後に
前記化合物半導体層表面の酸化膜を水洗処理で除去し、
ついで表面保護膜を被着する電界効果トランジスタ形成
工程を含むことを特徴とする半導体装置の製造方法。When forming a Schottky gate electrode in contact with a compound semiconductor layer containing arsenic by a lift-off method, an oxide film on the surface of the compound semiconductor layer is washed with water after removing the resist film for the lift-off method. Remove with
A method for manufacturing a semiconductor device, comprising a step of forming a field-effect transistor for applying a surface protective film.
ターンを形成し、前記レジスト膜パターンをマスクとし
て前記化合物半導体基板をエッチングしてリセス部を形
成してその底面にヒ素を含む化合物半導体層を露出さ
せ、導電膜を堆積し前記レジスト膜パターンとその上部
の前記導電膜を除去してショットキーゲート電極を形成
する工程と、水洗処理を行ない前記ショットキーゲート
電極で選択的に被覆された化合物半導体層表面の酸化膜
を除去する工程と、表面保護膜を被着する工程とを有す
ることを特徴とする半導体装置の製造方法。2. A resist film pattern is formed on the surface of the compound semiconductor substrate, and the compound semiconductor substrate is etched using the resist film pattern as a mask to form a recessed portion, exposing a compound semiconductor layer containing arsenic on the bottom surface. Forming a Schottky gate electrode by depositing a conductive film and removing the resist film pattern and the conductive film on the resist film pattern; and performing a water washing process to selectively cover the compound semiconductor with the Schottky gate electrode. A method for manufacturing a semiconductor device, comprising: a step of removing an oxide film on a layer surface; and a step of applying a surface protective film.
1-y As層(0≦y≦1)である請求項1又は2記載の
半導体装置の製造方法。3. The method according to claim 1, wherein the compound semiconductor layer containing arsenic is Al y Ga
3. The method for manufacturing a semiconductor device according to claim 1, wherein the 1-y As layer (0 ≦ y ≦ 1).
1,2又は3記載の半導体装置の製造方法。4. The method of manufacturing a semiconductor device according to claim 1, wherein a washing process is performed with deionized water.
1,2又は3記載の半導体装置の製造方法。5. The method for manufacturing a semiconductor device according to claim 1, wherein a water washing process is performed with electrolytic ionic water.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13722796A JP2765566B2 (en) | 1996-05-30 | 1996-05-30 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13722796A JP2765566B2 (en) | 1996-05-30 | 1996-05-30 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH09321062A JPH09321062A (en) | 1997-12-12 |
| JP2765566B2 true JP2765566B2 (en) | 1998-06-18 |
Family
ID=15193761
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|---|---|---|---|
| JP13722796A Expired - Lifetime JP2765566B2 (en) | 1996-05-30 | 1996-05-30 | Method for manufacturing semiconductor device |
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| Country | Link |
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| JP (1) | JP2765566B2 (en) |
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|---|---|---|---|---|
| JP2003068769A (en) * | 2001-08-29 | 2003-03-07 | Murata Mfg Co Ltd | Method of manufacturing field effect transistor and field effect transistor |
| JP4697650B2 (en) * | 2003-08-29 | 2011-06-08 | 信越半導体株式会社 | Light emitting element |
| JP2015032631A (en) * | 2013-07-31 | 2015-02-16 | 住友電気工業株式会社 | Semiconductor device, and method of manufacturing the same |
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