JP2771377B2 - Pulse generation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pulse generation circuit,
In particular, it relates to a one-shot pulse generation circuit using a MOS field effect transistor.

[0002]

2. Description of the Related Art Conventionally, a pulse generating circuit of this kind has been disclosed in FIG.
As shown in (a), a two-input AND circuit 1 and a delay circuit 2
Consists of a, to one input terminal of the AND circuit 1 receives an input signal phi _IA directly input signal to the other input terminal phi _IA
Is input with a delay of a predetermined time, and an output signal φ _O is taken out from the output terminal of the AND circuit 1.

Next, the operation of the circuit will be described with reference to FIG. Input signal _φIA is a rectangular wave having a certain pulse width. When the input signal φ _IA is input, the waveform of the signal φ _D at the output terminal of the delay circuit 2 is delayed by the time specified by the delay circuit 2.

Therefore, when the input signal φ _IA and the delay signal φ _D
Is input to the ND circuit 1, start rising at the rising edge of the signal waveform of the delayed signal phi _D, falling start output signal phi _O on the falling edge of the signal waveform of the input signal phi _IA is obtained.

[0005] In this manner, the amount delayed waveform and the delay circuit 2 of the input signals phi _IA by determining appropriately, it is possible to obtain a one-shot pulse waveform of any pulse width.

[0006]

In the above-described conventional one-shot pulse generation circuit, the circuit operating point is determined using both the rising edge and the falling edge of the input signal waveform due to the nature of the circuit. Therefore, when the operating point of the transistor shifts due to the rounding of the signal waveform, the pulse width of the generated one-shot pulse varies.

[0007]

According to the one-shot pulse generation circuit of the present invention, a first NMOS transistor and a second NMOS transistor are connected in series between a high-order power supply terminal and a low-order power supply terminal, and the series connection thereof is performed. A connection point serves as an output terminal, a third NMOS transistor is provided between the gate electrode of the first NMOS transistor and the lower power supply terminal, and an input signal is directly input to the gate electrode of the first NMOS transistor. The input signal is input to the gate electrode of the second NMOS transistor and the gate electrode of the third NMOS transistor with a predetermined time delay.

[0008]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a preferred embodiment of the present invention. FIG. 1A is a circuit diagram of one embodiment of the present invention.

Referring to FIG. 1A, in this embodiment,
Two NMOS transistors Q ₁ and Q ₂ are connected in series between a high-level power supply terminal (potential V _DD ) 3 and a ground terminal (potential GND) 4, and an output signal φ is output from the serial connection point.
_O is taken out. NM connected to high power supply terminal 1
Between the OS transistor Q gate electrode and the ground terminal 4 of _1, NMOS transistor Q ₃ is connected. The input signal φ _IA is directly input to the gate electrode of the NMOS transistor Q ₁ ,
Is input to the MOS transistor gate electrode of the gate electrode and the NMOS transistor Q ₃ of Q _2.

[0010] In FIG. 1 (b), the first when the input signal phi _IA is low, NMOS transistor Q ₁ is off.
Similarly, since the output signal φ _D of the delay circuit 2 is also low, the NMOS transistor Q ₂ is also off. Therefore,
The output signal phi _O becomes high impedance state, if the input signal phi _IA is a signal that there is a period in which always high at least once in an initial state, the output signal phi _O is low.

[0011] Next, when the input signal φ _IA is changed from low to high, NMOS transistor Q ₁ along with it is turned from OFF to ON. At this time, the delay signal φ from the delay circuit 2
_{Since D} is still low, NMOS transistors Q ₂ and Q ₃ are off. Therefore, the level of high is outputted to the output signal phi _O. However, since the delay signal φ _D from the delay circuit 2 changes from low to high after a certain delay time,
The NMOS transistors Q ₂ and Q ₃ turn on. NMOS
NMOS transistor Q ₁ the transistor Q ₃ is turned on is turned off. At this time, since the NMOS transistor Q ₂ is turned on the output signal phi _O will change from high to low. In this embodiment, the input signal phi _IA is would be forcibly reset by the delay signal phi _D,
It will be deformed like the signal φ _IB . However, the signal phi _IB since only have small driving ability is determined by the ratio between the pre-stage of the drive circuit, guarantees the driving capability of the output portion by the ability of the NMOS transistor Q ₂ of the output. Thus, a one-shot pulse can be generated. The pulse width of this one-shot pulse is
It is defined only by the delay time of the delay circuit 2.

[0012]

As described above, according to the present invention, since the operating point of the circuit is determined only by the rising edge of the input signal waveform, the present invention has an effect that the controllability of the signal width of the one-shot pulse is excellent.

Another advantage is that the number of transistor elements can be smaller than that of a conventional transistor.

[Brief description of the drawings]

FIG. 1 (a) is a circuit diagram of one embodiment of the present invention. FIG. 6B is a signal waveform diagram for explaining the operation of the circuit shown in FIG.

FIG. 2A is a circuit diagram of an example of a conventional pulse generation circuit. FIG. 6B is a signal waveform diagram for explaining the operation of the circuit shown in FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 AND circuit 2 Delay circuit 3 High power supply terminal 4 Ground terminal

Claims (1)

(57) [Claims] A first NMOS transistor and a second NMOS transistor connected in series between a high power supply terminal and a low power supply terminal, and a connection point between the first and second NMOS transistors is used as an output terminal; A third NMOS transistor is provided between the gate electrode of the first NMOS transistor and the lower power supply terminal; an input signal is directly input to a gate electrode of the first NMOS transistor; a gate electrode of the second NMOS transistor; 3. A pulse generating circuit according to claim 3, wherein the input signal is input to the gate electrode of the NMOS transistor with a predetermined time delay.