JP3080716B2 - Semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit,
In particular, it relates to a MOS semiconductor integrated circuit forming a one-shot pulse generation circuit.

[0002]

2. Description of the Related Art Conventionally, this kind of one-shot pulse generating circuit has a circuit configuration as shown in FIG. And
The operation waveform is as shown in FIG.

In FIGS. 3 and 4, the conventional circuit includes a delay circuit D1 and an AND circuit 1. Input signal φ4 is input, and output signal φ6 is output.

Next, the circuit operation will be described with reference to FIGS. The input signal φ4 is a rectangular wave having a certain pulse width. When the input signal φ4 is input, the delay circuit D2
Has a waveform delayed by the time specified by the delay circuit. Therefore, when the signal waveforms of the input signals φ4 and φ5 are input to the AND circuit 1, the waveform of the signal φ6 which starts rising at the rising edge of the waveform of the signal φ5 and the waveform of the signal φ6 which starts falling at the falling edge of the signal waveform of the signal φ4 becomes can get.

Thus, by appropriately determining the amount of delay of the input waveform φ4 and the delay circuit D2, a signal φ6 having a one-shot pulse waveform having an arbitrary pulse width can be obtained.

[0006]

In such a conventional one-shot pulse generating circuit, the circuit operating point is determined using both the rising edge and the falling edge of the input signal φ4 due to the nature of the circuit. In relation, the operating point of the transistor shifts due to the rounding of the signal waveform,
This has the disadvantage that the one-shot pulse width varies.

An object of the present invention is to provide a semiconductor integrated circuit which solves the above-mentioned drawbacks and does not change the one-shot pulse width even when the input signal waveform becomes dull.

[0008]

According to the present invention, there is provided a semiconductor integrated circuit comprising a series body of first and second transistors,
The common connection point of the series body is an output terminal, and the input terminal is the first terminal via a transfer gate transistor .
The input terminal is connected to the gate of the second transistor via a delay circuit, and the output of the delay circuit is used as the gate input of the transfer gate transistor and the first terminal is connected to the first terminal. a gate to a constant potential of the transistor and the gate input of the third transistor connected between, and the Trang
Sfa gate transistors and the first to third transistors.
Conductive channel type field effect different from transistor
It is characterized by having a transistor .

[0009]

FIG. 1 is a circuit diagram showing a semiconductor integrated circuit according to one embodiment of the present invention, and FIG. 2 is a waveform diagram showing its operation.

1 and 2, this embodiment has transistors Q1 to Q4 and a delay circuit D1, and receives an input signal φ1 and an output signal φ3. Only the transistor Q1 is of a P-channel type, and the others are of an N-channel type.

In this embodiment, a delay circuit D1 for delaying an input signal φ1 and an N-channel (ch) transistor Q4 driven by a control signal φ2 output from the delay circuit D1.
And the input signal φ1 is connected to the gate of the output driving Nch transistor Q3 via the transfer gate of the Pch transistor Q1.
3 has at least one or more resetting Nc
h transistor Q2 is connected to the gate electrode of the Pch transistor Q1 and the reset Nc.
The gate electrode of the h transistor Q2 is connected to the control signal φ2 output from the delay circuit D1.

First, when the input signal φ1 is at a low level, the output signal φ2 of the delay circuit D1 is low, so that the transistor Q1 is ON, the output of the transistor Q1 is low, and the transistor Q3 is OFF
It is. Further, since the output signal φ2 is Low, the transistor Q4 is OFF. Therefore, if the output signal φ3 is in a high impedance state, but the input signal φ1 is a signal that always has a period of at least once at a high level in the initial state, the output signal φ3 is low.
It is.

Next, the input signal φ1 is changed from Low to High.
, Since the output signal φ2 of the delay circuit D1 remains Low, the transistor Q1 is in the ON state,
The gate of the transistor Q3 changes from Low to High, and the transistor Q3 changes from OFF to ON. At this time, since the output signal φ2 remains Low, the transistor Q4 is OFF. Since the transistor Q3 is ON, a High level is output as the output signal φ3.

However, after a certain delay time, the output signal φ2 of the delay circuit D1 changes from low to high, so that the transistor Q1 turns off and the transistor Q2 turns on.
Therefore, the gate of the transistor Q3 is changed from High to L
ow, the transistor Q3 is turned off, and the output signal φ2 is high.
N. Therefore, the output signal φ3 changes from High to Low.

In this manner, a one-shot pulse can be similarly generated. The pulse width of the one-shot pulse is defined only by the delay time of the delay circuit D1.

As described above, in the one-shot pulse generation circuit of the present embodiment, the input signal φ1 is changed from Low (GND) to H
When the signal changes to high (VDD), an Nch transistor Q3 for transmitting the change as it is via a transfer gate of the Pch transistor Q1, an Nch transistor Q2 for resetting the Nch transistor Q3, and a signal delay. Delay circuit D
1 and an Nch transistor Q4 for resetting the output signal after a delay time.

[0017]

As described above, according to the present invention, since the operating point of the circuit is determined only by the rising edge of the input signal waveform, the present invention has an effect that the controllability of the pulse width of the one-shot pulse is excellent.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a semiconductor integrated circuit according to one embodiment of the present invention.

FIG. 2 is an operation waveform diagram of FIG.

FIG. 3 is a circuit diagram of a conventional one-shot pulse generation circuit.

FIG. 4 is an operation waveform diagram of FIG.

[Explanation of symbols]

 D1, D2 Inverter delay circuit 1 AND circuit Q1 P-type MOS transistor Q2, Q3, Q4 N-type MOS transistor φ1, φ4 Input control signal φ3, φ6 Output signal φ2, Q5 Internal signal

Claims (2)

(57) [Claims] 1. A first, the provided series of second transistors, an output terminal ungated a common connection point of the series connection body, the input terminal through a transistor for a transfer gate to a gate of said first transistor The input terminal is further connected to the gate of the second transistor via a delay circuit, and the output of the delay circuit is used as the gate input of the transfer gate transistor, and the first input terminal is connected to the first input terminal. a gate to a constant potential of the transistor and the gate input of the third transistor connected between, and the preparative
A transistor for transfer gate and the first to third transistors
Electric field of a conductive channel type different from that of other transistors
A semiconductor integrated circuit comprising an effect transistor . 2. The semiconductor integrated circuit according to claim 1, wherein the transfer gate transistor is a P-channel type, and the first to third transistors are N-channel type field effect transistors.