JP2772067B2 - Semiconductor memory device - Google Patents

Description

The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device suitable for application to a semiconductor memory such as a static RAM (random access memory). About.

(Prior Art) In recent years, a section WL (Section WL) method is generally adopted for a semiconductor memory circuit in order to realize low power consumption. In the section WL (Section WL) method, by dividing the memory cell array into multiple sections, the word line (WL) is not activated in the unselected section memory, and the cell current can be reduced.

FIG. 4 is a circuit diagram of an output portion of a conventional semiconductor memory representing one section of a plurality of section memories. As shown in FIG.
One of the memory cells (MC) 1, 1,... Is selectively connected, and complementary data is input. This sense amplifier 2
It is controlled by the sense amplifier control circuit 6.
When the address IN1 or IN2 from the address input 9 changes, when selected, the section is passed through the predecoder 8, the row decoder 3, and the column decoder 4 to the word line N1, the column switch line N8, and the sense amplifier control signal N10.
, An active signal is transmitted. On the other hand, the address transition detection circuit 7 detects an address transition. By this detection, the clock pulse φ generated from this circuit 7 is transmitted through the pulse control circuit 5 to the equalizing signals N9 and N1.
Output as 1, N12.

The word line N1 is connected to the memory cell 1, the column switch line N8 is connected to the transistors Tr3 and Tr4, and the equalizing signal N9 is connected to the gate of the transistor Tr5.
11 is supplied to the gate of the transistor Tr6, and the equalize signal N12 is supplied to the gate of the transistor Tr7.

Bit lines N2 and N3 are connected to the memory cells 1, 1,..., And a transistor Tr5 is connected between the bit lines N2 and N3.
The bit line N2 and the I / O line N4 are connected via a transistor Tr3, and the bit line N3 and the I / O line N5 are connected via a transistor Tr4. The I / O lines N4 and N5 are connected to the sense amplifier 2. A transistor Tr6 is connected between the I / O lines N4 and N5. Sense amplifier 2 leads sense amplifier output lines N6 and N7. A transistor Tr7 is connected between the sense amplifier output lines N6 and N7.

The transistors Tr5, Tr6, Tr7 become active (ON) for a certain period of time, and equalize the bit lines N2 and N3, the I / O lines N4 and N5, and the sense amplifier output lines N6 and N7, respectively. The equalization signals N9, N11, N12 are for the above equalization,
N9 = N11 = N12 may be satisfied. When an active signal is output to the word line N1 and the column switch line N8, and the sense amplifier control signal N10 becomes an active signal, the data of the memory cell 1 is transmitted to the bit lines N2 and N3 and is transmitted through the transistors Tr3 and Tr4. It is transmitted to I / O lines N4 and N5.

On the other hand, as transistors for pulling up the bit lines N2 and N3, the transistors Tr1 and Tr2 are used in a normally-on state. Assuming that the threshold value of this transistor is V _THE (V), the bit lines N2 and N3 are at V _cc −V _THE if there is no discharge of the memory cell.
Potential. As transistors for pulling up the I / O lines N4 and N5, the transistors Tr8 and Tr9 are used in a normally-on state. If the threshold of this transistor is V _THE (V),
I / O line N4, N5 is likewise a potential of V _cc -V _THE.

When the selected memory cell 1 discharges, the bit lines N2, N
There is a slight potential difference between the three. As a result, the data of the bit lines N2 and N3 are transferred through the transistors Tr3 and Tr4 to the I / O line N
4, transmitted to N5 and sense amplifier 2. This sense amplifier 2
As a result, the level difference between the I / O lines N4 and N5 is amplified. The amplification result is output to the sense amplifier output lines N6 and N7.

As a means of pull-up, N of transistors Tr8 and Tr9 etc.
By using -MOS transistor, the input voltage of the sense amplifier 2 becomes a voltage slightly lower than V _cc voltage, setting of the operating point of the sense amplifier 2 is facilitated.

FIG. 5 is an operation waveform diagram when an address transition to a new memory cell 1 is performed. That is, when the address input changes, the equalizing signals N9, N11, N12 are output. As a result, the sense amplifier output lines N6 and N7 change to an undefined state according to the equalization of the bit lines N2 and N3 and the I / O lines N4 and N5. Next, a sense amplifier control signal N10 is output. Thereafter, the column switch line N8 changes. Thereafter, the word line N1 changes, and the data of the memory array is determined. Therefore, the bit line N3 and the I / O line N5 change with the change of the data corresponding to the new address. Therefore, the sense amplifier output lines N6 and N7 are determined and new data is output.

During such data access, the output transistor in the last stage of the memory circuit performs charging and discharging. Moreover,
The output stage has a large channel dimension in consideration of external driving. For this reason, the power supply voltage oscillates at Ldi / dt due to charging / discharging at the time of data access, which causes power supply noise. The power supply noise from the output stage buffer is as shown by the transistors Tr1, Tr2, Tr in FIG.
8, also transmitted to the power supply of Tr9.

Here, the transistors Tr1 and Tr2 in FIG. 4 are shown as transistors Tr0 in FIG. 6, and the operation thereof will be described. The power supply of the transistor Tr0 is indicated by a terminal. Power supply to _Vcc
= And 5.0V, if the threshold voltage of the transistor Tr0 and a V _THE, the potential of the terminal becomes (V _cc -V _THE) V. Therefore, for example, if V _THE = 1.0 V, the potential of the terminal becomes 4.0 V. When the condition (V _GS ≦ V _THE ) is satisfied, the transistor Tr0
Is turned off. Therefore, the transistor Tr0 is turned off when the terminal voltage becomes 4.0V.

Therefore, it is assumed that the power supply has fluctuated due to noise in the power supply voltage as shown in FIG. Time t1 is in a steady state and is in a state of _Vcc = 5.0V. On the other hand, at times T2, T3, T4, and T5, there is fluctuation due to power supply noise. 8.0V at time T2, 3.0V at time T3, 6.0V at time T4, time
T5 is 4.0V.

As described above, at the time of the voltage at the time t1, the transistor Tr0
Is charged to 4.0 V, and the transistor Tr0 is turned off. Next, when the power supply terminal of the transistor Tr0 becomes 8.0V of the voltage at the time T2, the terminal is changed from 4.0V.
The transistor Tr0 is charged to 7.0 V and keeps off. Next, when the voltage of the power supply terminal becomes 3.0V at time T3, the terminal becomes 7.0V and the power supply terminal becomes 3.0V. Thus, while the terminal has been acting as the source of the transistor Tr0, the power supply terminal v now acts as the source. In this case, V _GS = 0V and V
_{Since THE} = 1.0 V, the result is V _GS <V _THE , and the transistor Tr0 is off. Therefore, terminal x is 7.0V
Remains. Next, when the power supply terminal of the transistor Tr0 reaches the voltage of 6.0 V at the time T4, the power supply terminal also becomes the source, so that V _GS <V _THE , and the transistor Tr0 is off. The power supply terminal v of the transistor Tr0 is at time T5
When the voltage becomes 4.0 V, the transistor Tr0 is turned off in the same manner.

Therefore, since the terminal of the transistor Tr0 has no discharge path, 7.0 V is maintained. This is the fourth
Apply it to the figure. In the unselected memories of the memory cells 1, 1,..., The word line N1 is off. Therefore, when the transistors Tr1 and Tr2 are connected, the bit lines N2 and N3 and the I / O lines N4 and N5 to which the transistors Tr8 and Tr9 are connected have no discharge path. Therefore, when noise occurs in the power supply, the potentials of the bit lines N2 and N3 and the I / O lines N4 and N5 rise.

(Problems to be Solved by the Invention) By the way, the operating point of the sense amplifier needs to be set so that data can be effectively amplified with respect to its input. Sense amplifier 2 shown in FIG.
Is a sense amplifier selectively connected to the memory cell 1. Therefore, the input voltage of the sense amplifier is _Vcc- V
Near _THE . Therefore, the operating point of the sense amplifier 2 needs to be set so that data amplification can be performed effectively with this input voltage. Therefore, when the bit line potential of the unselected memory cell array is higher than the normal potential due to power supply noise, when a cell in the memory cell array is selected, the input of the sense amplifier selectively connected to the memory cell is selected. And the operating point will be mismatched. For this reason, it becomes impossible to perform more effective data amplification.

FIG. 8 is an operation waveform diagram at the time of such an access.
Before the transition of the address input, the potential of the bit lines N2 and N3 and the potentials of the I / O lines N4 and N5 are kept higher than _Vcc due to the influence of power supply noise. When the transition of the address input is performed from this state, first, equalizing signals N9, N11, N12 are transmitted, and the equalizing of the bit lines N2, N3, the I / O lines N4, N5, and the sense amplifier output lines N6, N7 is performed. Done. At this time, the sense amplifier control signal N10 and the column switch line N8 change. Thereafter, the word line N1 changes. However, the bit line N3 and the I / O line N5 do not easily follow the data of the new address due to the mismatch with the sense amplifier. For this reason, the state of the sense amplifier output lines N6 and N7 is not easily determined, and the sense amplifier output lines N6 and N7 are determined with an extremely long delay.

As described above, if there is a mismatch between the input of the sense amplifier and the operating point, a delay in access time occurs, which is a major obstacle to high-speed memory access.

An object of the present invention is to solve the above-mentioned drawbacks of the prior art. It is an object of the present invention to discharge data to the operating point potential when reading data even if the bit line potential rises above the operating point potential due to power supply noise. An object of the present invention is to provide a semiconductor memory device in which an amplifier operates properly.

[Configuration of the invention]

(Means for Solving the Problems) According to a first semiconductor memory device of the present invention, there are provided a plurality of memory cells for storing data, and a complementary memory cell connected to a selected one of the plurality of memory cells. A bit line, a complementary data line connected to the complementary pit line via a column switch, a complementary data line connected to the complementary bit line via a column switch, and A sense amplifier that inputs a signal corresponding to the data transmitted to the complementary data line via a complementary data line and the column switch, and outputs a signal corresponding to the data to an output line; and an input of the sense amplifier. Between each of the complementary data lines on the output side and the output line on the output side is temporarily turned on at the time of memory address transition, It constituted a potential of the complementary data lines as an input side of the amplifier as comprising a conducting circuit for setting the operating point potential of the sense amplifier.

According to a second semiconductor memory device of the present invention, in the first semiconductor memory device, the output line on the output side of the sense amplifier is configured as a complementary line, and the conduction circuit is connected to an input side of the sense amplifier. A first conducting means for conducting between one of the complementary data lines and one of the output lines on the output side, and a second conducting means for conducting between the other of the complementary data lines and the other of the output lines. It is constituted as having.

In a third semiconductor memory device according to the present invention, in the first semiconductor memory device, the output line on the sense amplifier output side is configured as a single line, and the conduction circuit includes:
A first conducting means for conducting one of the complementary data lines on the input side of the sense amplifier to the output line; and a second conducting means for conducting the other of the complementary data lines to the output line. It is configured as something.

(Operation) At the time of a memory address transition, conduction between the input side (complementary data line) and the output side (output line) of the sense amplifier is temporarily conducted by the conduction circuit. As a result, the input side and the output side of the sense amplifier eventually have the same potential. That is, for example, when the potential of the complementary data line is higher than the operating point potential due to power supply noise, the charge corresponding to the rising potential of the complementary data line is discharged to the output line. In this case, the discharge is performed toward the output section of the sense amplifier in this manner, so that the input of the sense amplifier is discharged to the operating point of the sense amplifier without excess or shortage. That is, due to conduction between the input side and the output side of the sense amplifier, the potential of the complementary data line becomes the operating potential of the sense amplifier.
In this state, complementary data from the selected memory cell is output to the complementary data line. As described above, since the complementary data line is at the operating potential, the sense amplifier operates properly and outputs correct data to the output line.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of one embodiment of the present invention. In FIG. 1, components equivalent to those in FIG. 4 are denoted by the same reference numerals as those in FIG. As shown in FIG.
The transistor T1 is arranged between the O line N4 and the sense amplifier output line N6. Further, a transistor T2 is arranged between the I / O line N5 and the sense amplifier output line N7. The clock φ1 applied to the gates of the transistors T1 and T2 is
The address transition detection clock is output from the pulse control circuit 5. This clock φ1 is for performing an initialization operation at the time of address transition. for that reason,
It may be the same signal as the equalize signals N9, N11, N12 output from the pulse control circuit 5.

Next, the operation of the above configuration will be described with reference to FIGS. 1 and 3.

FIG. 3 is an operation waveform diagram when a new memory cell 1 is accessed. Before the time when the address input transitions, the unselected section is affected by power supply noise and the bit line
The potentials of N2, N3 and I / O lines N4, N5 are maintained at a potential higher than _Vcc . In this state, when a non-selected section is selected by transition of the address input, first, the equalizing signals N9, N11, N12 and the clock φ1 are output from the pulse control circuit 5. Thereby, the transistor Tr5
Tr7 is turned on, and the bit lines N2 and N3, the I / O lines N4 and N5, and the sense amplifier output lines N6 and N7 are equalized. At the same time, the transistor T1 turns on between the I / O line N4 and the sense amplifier output line N6, and the transistor T2 turns on between the I / O line N5 and the sense amplifier output line N7. Subsequently, the sense amplifier control signal N10 is output from the sense amplifier control circuit 6, and is output from the column decoder 4 to the column switch line N8. As a result, the transistor Tr3 turns on, and the bit line N2 and the I / O line N4 conduct, and the transistor Tr4 conducts, so that the bit line N3 and the I / O line N5 conduct. As a result, until then V
_{When the} potentials of the bit lines N2 and N3 held at a potential higher than _cc are equalized with the sense amplifier output, the bit lines N2 and N3 are discharged to the operating point of the sense amplifier. Thereafter, the output from the row decoder 3 to the word line N1 changes. However, at this time, bit lines N2 and N3, I / O
The potentials of the lines N4 and N5 have been discharged to the operating point of the sense amplifier 2. Therefore, the potential of those lines N2, N3, N4, N5 is
It is immediately determined according to the data of the cell selected by the new address. Therefore, the sense amplifier output lines N6 and N7, which are the outputs of the sense amplifier 2, are also promptly determined as new data.

In the above embodiment, the case where the data output lines of the sense amplifier 2 are two complementary sense amplifier output lines N6 and N7 has been exemplified. However, as shown in the circuit diagram of FIG.
The present invention is also applicable when the number of output lines of the sense amplifier 2 is one (N6). In this case, the transistors T1 and T2 are connected between the I / O line N4 and the output line N6 and the I / O line N5.
And the output line N6. Thus, when the transistors T1 and T2 are turned on at the time of the address transition, the potential of the I / O lines N4 and N5 can be discharged to the operating point of the sense amplifier 2. This allows effective data amplification. In the case of FIG. 2, it is natural that the sense-up 2 is configured to selectively output a signal corresponding to one of the input complementary data.

As described above, according to the present invention, the input side of the sense amplifier is not simply conducted to the ground side, but is conducted to the output side. The potential of the data line can be automatically and self-settingly set to the operating point potential of the sense amplifier, regardless of the potential of the input side (complementary data line). The potential on the input side can be adjusted to the operating point potential of the sense amplifier in a self-setting manner without any excess or shortage, whereby the data read from the memory cell can be properly sensed and amplified by the sense amplifier. Therefore, for example, even if the potential of the complementary data line as the input side of the sense amplifier is increased due to power supply noise or other causes, a signal corresponding to data from the memory cell is applied to the sense amplifier in this state. Rather than simply lowering the potential on the input side of the sense amplifier, instead of setting it to their operating point potential in relation to this sense amplifier,
The sense amplifier can properly sense and amplify data from the memory cell. Moreover, in the present invention, the level is not adjusted simply by connecting the input side of the sense amplifier to another node, but the output side of the own sense amplifier is focused on, and the connection and conduction are performed here. The potential on the side can be set to the operating point potential that causes the sense amplifier to perform proper operation, that is, automatically inevitably automatically, and the data read from the memory cell is performed by ensuring the proper operation of the sense amplifier thereafter. It can be performed with high reliability.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of one embodiment of the present invention, FIG. 2 is a circuit diagram of another embodiment of the present invention, FIG. 3 is a waveform diagram for explaining the operation of FIG. 1, and FIG. 5 is a circuit diagram, FIG. 5 is a waveform diagram for explaining the general operation of FIG. 4, FIG. 6 is an operation explanatory diagram of a transistor as a load resistor used in FIG. 4, and FIG. FIG. 8 is a waveform diagram for explaining the operation of the configuration of FIG. 4 when the input voltage of the sense amplifier changes due to power supply noise. 1 ... memory cell, 2 ... sense amplifier, 21,22,23 ...
Sense amplifier, 3 row decoder, 4 column decoder, 5 pulse control circuit, 6, 61, 62 sense amplifier control circuit, 7 address transition detection circuit, 8 predecoder, 9 … Address input, T1, T
2 ... Transistor.

──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Masami Masuda 1 Komukai Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa Prefecture Inside the Toshiba Tamagawa Plant (56) References JP-A 1-222991 (JP, A) (58) Field surveyed (Int.Cl. ⁶ , DB name) G11C 11/41

Claims (3)

(57) [Claims] A plurality of memory cells for storing data; a complementary bit line connected to a selected one of the plurality of memory cells; and a column switch for each of the complementary bit lines. A signal corresponding to the data transmitted to the complementary data line from the memory cell via the complementary data line and the column switch, and a signal corresponding to the data. A sense amplifier that outputs a signal to an output line, and temporarily connects between each of the complementary data lines on the input side of the sense amplifier and the output line on the output side at the time of memory address transition. A conductive circuit for setting the potential of the complementary data line as a side to the operating point potential of the sense amplifier. Apparatus. 2. The sense amplifier according to claim 1, wherein the output line on the output side of the sense amplifier is configured as a complementary line, and the conductive circuit is connected to one of the complementary data line on the input side of the sense amplifier and the output line on the output side. 2. The semiconductor memory device according to claim 1, further comprising: a first conductive unit that connects one of the complementary data lines, and a second conductive unit that connects the other of the complementary data lines and the other of the output lines. 3. 3. The sense amplifier according to claim 1, wherein the output line on the output side of the sense amplifier is configured as a single line, and the conduction circuit is configured to conduct between one of the complementary data lines on the input side of the sense amplifier and the output line. 2. The semiconductor memory device according to claim 1, further comprising: a conductive unit for connecting said second data line to said output line and a second conductive unit for connecting said other of said complementary data lines to said output line.