JP2953102B2 - Semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and, more particularly, to adjusting the potential of an I / O line (input / output line) for connecting a bit line constituting a memory cell array to a common data bus. Circuit.

[0002]

2. Description of the Related Art A semiconductor memory device has a memory cell array composed of a plurality of memory cells provided in an array and a plurality of bit lines and word lines respectively connected thereto, and is used to select a predetermined memory cell. A row decoder and a column decoder are arranged adjacent to the memory cell array. In addition, a path for reading and writing data to and from a memory cell selected by these row decoder and column decoder is provided.
/ O line is arranged. One end of this I / O line is connected to a bit line pair whose potential difference is amplified by a sense amplifier via a selection switch, and the other end is connected to the periphery of a semiconductor chip via a buffer circuit and an I / O line selection circuit. It is connected to a common data bus connected to input / output pads provided in the section.

In general, in a semiconductor memory device, in order to speed up a read operation, an I / O line is composed of two pairs of lines having a level-complementary relationship. A method of using a small amplitude near the level is used. In order to make the potential difference displacement of the wiring pair small amplitude,
A precharge circuit for supplying a power supply voltage to two wirings at the time of reading is provided. The precharge circuit is provided between, for example, a power supply terminal and a wiring, and includes a transfer gate which is turned on at the time of reading.

By providing such a precharge circuit, a power supply voltage is always supplied to two wirings at the time of reading. On the other hand, one bit line pair is electrically connected to the two wirings by the selection switch, and one of the two wirings is connected to the high level in the sense amplifier connected to the bit line pair. Then, another line is to be amplified to a low level. However, since the amplification capability of one sense amplifier is smaller than the power supply voltage supply capability of the precharge circuit, the voltage level of the wiring corresponding to the low level does not become the ground potential, and is about 5% lower than the power supply potential level. Only.

By reducing the potential difference between the wiring pairs forming the I / O line at the time of reading, the displacement of the potential difference between the wiring pairs is small when one data is read and then the next data is read. The operation can be performed at high speed.

[0006]

By the way, in a recent semiconductor memory device, a plurality of times of reading data from a plurality of memory cells below one word line selected according to an input address are performed. A device having a so-called high-speed page mode for continuously performing a random access operation has appeared.

In this first page mode operation, after reading data stored in one memory cell, only the column address is updated without selecting another word line, and the other word line under the same word line is updated. An operation of reading data stored in a memory cell is performed. That is, after one data is read, another bit line pair is selected by a selection switch that operates according to the column address, and this bit line pair is electrically connected to the I / O line to read as the next data. The output operation is continuously performed a plurality of times.

However, a period from the time when one data is read until the time when the next data is read, that is, a transition period in which the connection of the I / O line is switched from one bit line pair to another bit line pair by the selection switch. In a state where a column decoder for generating a control signal for controlling the selection switch generates a control signal for simultaneously selecting a plurality of bit line pairs due to a shift in the input timing of the input column address, in other words, the selection state The switch may be in a multi-select state.

In such a state, a plurality of sense amplifiers simultaneously amplify the potential of the wiring pair forming the I / O line to a high level and a low level. The number of bit line pairs selected simultaneously is large (for example, 8 to 10 pairs)
Depending on the combination of the high level and the low level of the selected bit line pair, the level of one wiring is close to the power supply potential and the level of the other wiring is the power supply potential (for example, 5 V).
V) may be less than half the potential (for example, 2 V).

As described above, when the potential of one of the wiring pairs forming the I / O line is significantly reduced during the transition period,
Not only does it take time to read the next data, but also the data stored in the memory cell may be destroyed.

Therefore, an object of the present invention is to provide a circuit in which the potential of the I / O line is changed even when the selection switch is in the multi-select state during the transition period from the time when one data is read to the time when the next data is read. It is an object of the present invention to provide a semiconductor memory device capable of preventing a large drop.

[0012]

A semiconductor memory device according to the present invention includes a memory cell array including a plurality of memory cells provided in an array and a plurality of bit lines and word lines respectively connected thereto, and a selection circuit. An I / O line composed of a first wiring and a second wiring connected to a predetermined number of bit lines of a plurality of bit lines, a precharge circuit for supplying a power supply potential to the I / O line at the time of reading, First means for connecting the first wiring and the second wiring when the first wiring has a predetermined voltage value or more higher than the second wiring, the circuit being activated at the time of reading; Has a clamp circuit including second means for connecting the first wiring and the second wiring when the voltage becomes equal to or higher than a predetermined voltage value than the first wiring.

Preferably, the first means comprises a first transistor having a first node connected to the gate and a source / drain path connected between the first node and the second node; The means comprises a second transistor having a second node connected to the gate and a source / drain path connected between the first node and the second node, wherein the first node is connected to the first wiring, The second node is connected to the second wiring.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described with reference to FIG. As shown in FIG. 1, the memory cell array 1 is formed by arranging a so-called one-transistor-one-capacitor type cell MS in which a cell is constituted by one N-channel transistor and one capacitance element. The bit line is connected to each one sense amplifier SA with BLa and BLb as a pair. The row decoder 2 selects one of the plurality of word lines WL according to the input row address. The column decoder 3 outputs one of the selection signals Y1, Y2, Y3,... Yn according to the input column address.
One is supplied to the selection switch 4 as an active level (high level). The selection switch 4 receives the selection signals Y1, Y2, Y3,... Yn from the column decoder 3 at its gate, and has a source / drain path between the input / output terminal of the sense amplifier SA and the wirings La and Lb forming the I / O line. It is composed of a group of transistors provided.

A pair of bit lines BLa and BLb selected by the selection switch 4 are connected to wirings La and Lb, respectively. The wirings La and Lb complementarily supply read data and write data, and one end is connected to a data amplifier and a write amplifier (not shown). The wires La and Lb are also connected to a precharge circuit 5 for raising the potential of the wires to near the power supply potential during a read operation. The precharge circuit 5 receives a control signal .phi.p which becomes an active level (low level) at the time of a read operation at a gate, and a source / drain path has a power supply terminal Vcc.
And the wirings La and Lb.

Further, the wirings La and Lb are connected to a clamp circuit 6 which is a feature of the present invention, so that the potential difference between the two wirings does not exceed a predetermined potential difference during a read operation. The clamp circuit 6 supplies a control signal φW to the gate which becomes active level (low level) during a read operation.
R, the source / drain path is connected between the wiring La and the node N1, and the gate receives the control signal φWR.
b, a P-channel transistor 13 connected between the node N2, a gate connected to the node N1, a source / drain path connected between the node N1 and the node N2, and a gate connected to the node N2. , And an N-channel transistor 15 whose source / drain path is connected between the nodes N1 and N2.

Next, the operation of this embodiment will be described with reference to the drawings. During a read operation, control signal φW
R and φp are both at an active level (low level) (see FIGS. 2A and 2B). The power supply voltage forms an I / O line via P-channel transistors 10 and 11 until row address RA and column address CA are input to row decoder 2 and column decoder 3, respectively, and one bit line pair is selected. Wirings La and Lb
It is only supplied to Therefore, the levels of the wirings La and Lb are both at the VCC level (for example, 5 V) (FIG. 2).
(D)).

Next, after one word line WL is selected by the row decoder 2 according to the row address RA, the column address CA is input (see FIG. 2C). The column decoder 3 selects the selection signal Y according to the column address CA.
1 as an active level (high level) (FIG. 2
(See (e).) Therefore, a set of bit line pairs corresponding thereto is selected by the selection switch 4. The level of the selected bit line pair BLa, BLb corresponds to the data stored in the memory cell MS selected according to the address, and is set to BLa.
Is at a high level and BLb is at a low level.
The sense amplifier SA operates to set BLa to high level and BLb to low level.

The bit line BLa selected by the selection switch 4 is electrically connected to the wiring La, and the bit line BLb
Is connected to the wiring Lb, the wiring La maintains the Vcc level, but the potential of the wiring Lb is lowered to the low level by the sense amplifier SA of the selected bit line pair. However, since the amplification capability of one sense amplifier SA is smaller than the power supply capability of the precharge circuit 5, the voltage level of the wiring Lb does not become the ground potential, and is not higher than Vcc.
The potential level is about 300 mA lower than 00 (see FIG. 2).
(D)).

A data amplifier (not shown) further amplifies the potential difference between the lines La and Lb and outputs this as read data to an input / output terminal (not shown) via a common data bus. The data read operation ends.

When the read operation is in the high-speed page mode, the row address RA is read again to read the next data.
, The operation of continuously reading data stored in the memory cells MS under the same word line is performed by updating only the column address CA (see FIG. 2C). When the next column address CA is input,
The column decoder 3 sets the selection signal Y1 to an inactive level (low level) and sets the column address CA
Is set to the active level (see FIG. 2D).

In the transition period TA during which the selection signal switches, a state is generated in which the column decoder 3 generates a control signal for selecting the bit line pair due to a shift in the input timing of the input column address CA (FIG. 2). (A state where the selection signal Y3 is at a high level). In some cases, a plurality of high-level selection signals may be generated. In this case, a plurality of bit line pairs are connected to the I / O line, that is, the selection switch is in a multi-select state.

In the transition period TA shown in FIG. 2, a multi-select state in which many bit line pairs (about eight) are selected at one time is shown. If many bit line pairs are selected at the same time as described above, conventionally, depending on the combination of the high and low levels of the selected bit line pair, the level of one of the wirings (for example, the wiring La) is changed to the level of the selected bit line. The potential of the power supply potential is reduced to half or less (for example, 2 V or less) by the sense amplifier SA of the line pair, and data in the memory cell may be destroyed. However, according to the present embodiment, even in such a case, the potential difference between the wires La and Lb is reduced to a certain potential or less by the clamping operation of the clamp circuit 6 described later in detail, and the minimum potential of the wire La is suppressed to about 3.5 V. (See FIG. 2D), the probability of data destruction is reduced and the read speed is increased as compared with the conventional case.

After the elapse of the transition period TA, the column address C
A bit line pair corresponding to A is selected, and one data is read out in the same manner as the operation described above. Further, when a predetermined number of column addresses CA are continuously input, a read operation in a high-speed page mode for reading data stored in a memory cell under one word line WL at a high speed is performed.

On the other hand, in the write operation, when a row address RA and a column address CA for writing are input (see FIG. 2C), both control signals φWR and φp are at an inactive level (high level). Level), and at the same time, the wirings La and Lb are set to the high level and the low level (near the GND level) according to the write data by the write amplifier (not shown) (see FIG. 2D). Thereafter, the column decoder sets one selection signal (in this case, Y1) to an active level in accordance with the column address, thereby storing write data in one memory cell MS.

Next, the operation of the clamp circuit 6 during the transition period TA will be described in more detail with reference to FIG. After one data is read, when a column address CA for reading the next data is input, a selection signal (Y2 in this case) corresponding to this column address starts to rise to a high level. On the other hand, the selection signal Y which was high level until then
1 begins to fall to low level. At this time, another selection signal (Y3 in this case) may rise to a certain potential due to a shift in input timing of the input column address CA. In some cases, a large number of selection signals such as Y3 may be generated. When many bit line pairs are selected at the same time as described above, depending on the combination of the high and low levels of the selected bit line pair, the level of one of the lines (in this case, the line La) is changed to the selected bit line pair. Quickly falls to the low level by the sense amplifier SA. At this time, since control signal φWR is at the active level, transistors 12 and 13 are on, and the potential of node N1 falls to low level simultaneously with wiring La. At this time, the potential of the wiring Lb rises slightly in the Vcc direction by the sense amplifier.

The potential of the wiring La decreases and the wiring La
And Lb, that is, the potential difference between nodes N1 and N2 is equal to the threshold voltage Vth (eg, 7
When the voltage exceeds (00 mV) (see t1 in FIG. 3), the N-channel transistor 15 becomes conductive, a current flows from the node N2 to N1, and the potential difference between the wirings La and Lb is clamped. Since the wiring La is electrically connected to the wiring Lb whose potential is close to Vcc, the speed of the potential drop is reduced, and the lowest potential of the wiring La can be finally suppressed to about half of the conventional level. Becomes Therefore, according to the present embodiment, even if one of the wirings has a potential lower than half of the power supply potential (eg, 2 V or lower) due to the multi-select state in the related art, the clamping operation of the clamp circuit 6 causes the wiring La to be disconnected. The minimum potential can be suppressed to about 3.5V.

This clamping operation is performed while the potential of the wiring La is decreasing. Thereafter, when the level of Y3 or the like falls and the level of the wiring La starts to rise by the precharge circuit 5, the potential difference between the nodes N1 and N2 becomes equal to or lower than the threshold voltage Vth, so that the N-channel transistor 15 is turned off. , The wirings La and Lb rise rapidly.

According to the above-described operation, according to the present embodiment, even if a potential drop occurs in the I / O line during the transition period, which conventionally destroys the data of the memory cell, the clamp circuit 6 operates according to the present embodiment. Since the clamping operation is performed between the two wirings constituting the / O line, one of the wirings does not significantly decrease. Accordingly, data destruction of the memory cell can be prevented, and a decrease in the potential of the wiring is small, so that the next read operation can be sped up.

In the above description, an example in which the wiring La rapidly falls to the low level when the wiring La is in the multi-select state is shown. Since the potential difference exceeds the threshold voltage Vth of N-channel transistor 14, node N
A clamp operation in which a current flows from 1 to N2 is performed, and the same effect as described above is obtained.

Next, a second embodiment of the present invention will be described with reference to FIG. This embodiment is different from the first embodiment shown in FIG. 1 only in the configuration of the clamp circuit, and all other configurations are the same. In this embodiment, the clamp circuit 106
A node N11 connected to the gate and a source / drain path provided between the lines La and Lb forming the I / O line.
A node L12 is connected to the gate of the channel transistor 41, and the source / drain path forms an I / O line.
N-channel transistor 42 provided between a and Lb
And a gate receives a control signal φWR that becomes an active level (low level) at the time of reading, a P-channel transistor 43 whose source / drain path is provided between the wiring La and the node N11, and a control signal φWR at its gate, A P-channel transistor 44 having a drain path provided between the wiring La and the node N12, and a control signal φW
R, the source / drain path is connected to the ground potential and the node N11.
An N-channel transistor 45 provided therebetween, and an N-channel transistor 46 having a gate receiving the control signal φWR and having a source / drain path provided between the ground potential and the node N12.

Next, the operation of this embodiment will be described with reference to FIG. The only difference between the present embodiment and the first embodiment in the operation is the operation of the clamp circuit 106 during the transition period TA, and the other operations are the same as those of the first embodiment.
Only the operation of will be described below.

After one data is read, when a column address CA for reading the next data is input, a selection signal (Y2 in this case) corresponding to this column address is input.
Begins to rise to a high level. On the other hand, the selection signal Y1 which has been high level starts falling to low level. At this time, if a large number of selection signals such as Y3 are generated and many bit line pairs are selected at the same time as in the first embodiment due to a shift in the input timing of the input column address CA or the like, the selection is made. Depending on the combination of the high and low levels of the bit line pair, one wiring (in this case, the wiring L
The level of a) rapidly falls to the low level by the sense amplifier SA of the selected bit line pair.

At this time, since the control signal φWR is at the active level (low level), the P-channel transistor 4
3 and 44 are conductive, N-channel transistor 45
And 46 become non-conductive. In the case of this embodiment, the potentials of the nodes N11 and N12 are
Since the voltage passes through 44, the potential change is delayed by that amount (see the dotted line in FIG. 5) and falls to the low level. At this time, the potential of the wiring Lb rises slightly in the Vcc direction by the sense amplifier.

The potential of the wiring La decreases and the wiring La
When the potential difference between the node N12 and the node N12 exceeds the threshold voltage Vth (for example, 700 mV) of the N-channel transistor 42 (see t11 in FIG. 5), the N-channel transistor 42 becomes conductive, and current flows from the wiring Lb to the wiring La,
The potential difference between the wirings La and Lb is clamped. By this clamping operation, the speed of falling to the low level is reduced, and the lowest potential of the wiring La can be suppressed as compared with the conventional example, as in the first embodiment.

This clamping operation is performed while the potential of the wiring La is falling. In this embodiment, even if the level of the wiring Y3 or the like falls and the levels of the wiring La and Lb start rising by the precharge circuit 5, Since the potential change at the node N12 changes with a delay due to the presence of the P-channel transistor 44 as shown by the dotted line, at this time (t12 in FIG. 5).
Then, the potential difference between the wiring La and the node N12 is a threshold voltage. Therefore, immediately after the wiring La rises, the N-channel transistor 42 is still in a conductive state, and the wiring La electrically connected to the wiring Lb having a higher potential level than the wiring La rises to the first level. It is faster than in the embodiment. Thereafter, when the potential difference between the wiring La and the rising node 12 becomes equal to or lower than the threshold voltage Vth, the N-channel transistor 42 is turned off.

Since the N-channel transistor 42 is still conducting even when the level of the wiring Lb falls, such as Y3 (t12 in FIG. 5), the potential of the wiring La and the potential of the node N1 continue thereafter.
The potential level decreases until the potential difference from 2 reaches the threshold voltage. Therefore, the rise of the wiring La rapidly reaches a high level as compared with the wiring Lb, and conversely, the potential of the wiring La becomes higher than the potential of Lb, and the potential difference of the wiring becomes equal to or higher than the threshold voltage Vth. (T13 in FIG. 5), the node N1
Since the potential change of 1 changes with a delay due to the presence of the P-channel transistor 43 as shown by the dotted line, at this time (t13 in FIG. 5), the potential difference between the wiring Lb and the node N11 is the threshold of the N-channel transistor 41. It is equal to or lower than the voltage Vth. Therefore, the N-channel transistor 41 does not become conductive, and the wiring La can quickly rise to the high level as it is.

When the multi-select state is set and the line Lb rapidly falls to the low level as in the first embodiment, the potential difference between the node N11 and the line Lb causes the threshold voltage Vth of the N-channel transistor 41 to decrease. Therefore, a current flows from the wiring La to the wiring Lb, and a clamping operation is performed. Thus, the same effect as described above can be obtained.

As described above, the present embodiment has the effect that the potential of the wiring rises faster than in the first embodiment. Further, in the first embodiment, the transistors for flowing the current due to the potential difference between the wirings La and Lb are the P-channel transistors 12 and 13 and the N-channel transistor 1.
In contrast to the total number of four transistors 4 and 15, four N-channel transistors 41 and 42 are required in this embodiment. Since the size of the transistors through which these currents flow must be designed to be large, the number of transistors constituting the clamp circuit in the second embodiment is larger than that of the first embodiment, but the number of transistors constituting the clamp circuit must be small. As a result, it is possible to configure the clamp circuit with a smaller formation area than in the first embodiment.

[0040]

As described above, according to the semiconductor memory device of the present invention, even if a potential drop occurs on the I / O line which would destroy the data in the memory cell, the clamp circuit can operate the I / O line.
Since the clamping operation is performed between the two lines constituting the O line, one of the lines does not significantly decrease.

Accordingly, data destruction of the memory cell can be prevented, and the potential of the wiring is small, so that the next read operation can be sped up.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a waveform diagram for explaining an operation of the semiconductor memory device shown in FIG. 1;

FIG. 3 is a circuit diagram showing a part of the waveform shown in FIG. 2 in further detail.

FIG. 4 is a circuit diagram showing a configuration of a semiconductor memory device according to a second embodiment of the present invention.

FIG. 5 is a waveform diagram for explaining an operation of the semiconductor memory device shown in FIG. 4;

[Explanation of symbols]

 Reference Signs List 1 memory cell array 2 row decoder 3 column decoder 4 selection switch 5 precharge circuit 6 clamp circuit

Claims (1)

(57) [Claims] 1. A memory cell array comprising a plurality of memory cells provided in an array, a plurality of bit lines and word lines respectively connected thereto, and a predetermined number of bits of the plurality of bit lines via a selection circuit. An I / O line comprising a first wiring and a second wiring connected to the wiring, and a control terminal receiving a control signal which becomes an active level at the time of reading and provided between the first wiring and a first node. A first transfer gate, a second transfer gate provided between the second wiring and a second node receiving the control signal at a control terminal, and a ground potential receiving the control signal at a control terminal. a third transfer gate provided between the first node, and a fourth transfer gate provided between the ground potential receiving said control signal to the control terminal and the second node, the first Of the second wiring is
The first wiring when the voltage becomes higher than the predetermined voltage by a predetermined voltage.
First means for connecting the second wiring and the second wiring;
The potential of the node is higher than the potential of the first wiring by the predetermined voltage.
The first wiring and the second wiring when larger
And a second means for connecting the semiconductor memory device.