JP2772085B2 - Programmable logic element - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial applications]

The present invention relates to a programmable logic element whose logic function is determined by externally input definition data. The present invention relates to a programmable logic element capable of improving the performance.

[Prior art]

For example, in a programmable logic element whose logic function is determined by definition data input from a memory such as an external ROM or EPROM, for example, in a programmable gate array, it is necessary to supply logic function definition data to each programmable logic element. is there. Therefore, conventionally, as shown in FIG. 4, for example, a read-only memory (ROM) 30 containing data for defining its logic function can be connected to the programmable logic element 10, and the programmable logic element 10
For example, 8-bit definition data is supplied to the logic function definition memory 12 via the data bus 32 so that the function of the programmable logic element 10 is defined. When the logic function definition data is loaded, the built-in changeover switch 18, the input / output port 19, and the programmable logic element 10 built in the programmable logic element 10 are supplied from the address generation circuit (counter) 11 of the programmable logic element 10. The ROM 30 is connected to an address bus 34 via an external switch 31 for external connection switching provided outside the ROM 30.
For example, a 16-bit address is output, and corresponding to this address, for example, 8-bit definition data is stored in the ROM 30.
Then, the data is transferred to the logic function definition memory 12 via the external switch 36 for switching the external connection, the input / output port 21 built in the programmable logic element 10 and the built-in switch 22 via the data bus 32. In the figure, reference numerals 24 and 26 denote input / output ports for inputting and outputting data and addresses (in the case of a memory) with other external logic circuits (functional blocks), for example, an external memory 38 such as an SRAM. When a plurality of programmable logic elements are included, as shown in FIG. 5, for example, the most upstream programmable logic element is a master mode programmable logic element (hereinafter referred to as a master logic element). As 10a, the ROM 30 is replaced with the master logic element.
Connect to 10a. On the other hand, for example, n slave mode programmable logic elements (hereinafter, referred to as slave logic elements) having the same hardware configuration as the master logic element 10a, which are made subordinate to the master logic element 10a. ) 10b is connected in series with the master logic element 10a. When loading the data for defining the logical function,
From the address counter 11 of the master logic element 10a to R
An address is output to the OM 30, and for example, 8-bit definition data is output from the ROM 30 in accordance with the address.
According to the definition data, first, the master logic element 10a
The master data is stored in the logic function definition memory 12 of the master, and then the slave data is stored in the master logic element.
Output from the output terminal Dout of 10a, input to the input terminal Din of the downstream logic element for slave 10b, the slave No.
1,... No.n are sequentially transferred and stored. That is, the logic element 10b that is a slave other than the master receives the logic function definition data from the ROM 30 via the master logic element 10a. After the definition, normal operation starts. In FIG. 5, reference numeral 14 denotes a pulse generator (PG) for generating a synchronizing clock CCLK for determining data fetch timing, and 16 counts the synchronizing clock so that each slave logic element 10b can accurately determine Is a pulse counter for receiving the definition data. On the other hand, in recent years, in order to enable high-speed circuit operation and increase the integration density, it has been considered to incorporate an external memory 38 such as an SRAM which is conventionally provided outside in the programmable logic element 10.

[Problems to be solved by the invention]

However, conventionally, when an externally provided SRAM is simply moved into the programmable logic element 10 and used as an internal memory (SRAM) 40, as shown in a comparative example shown in FIG. It was necessary to provide the input / output port 42, and the area of the system could not be reduced. Here, the external changeover switches 31 and 36 for switching the external connection, and the built-in changeover switches 18 and 22 built in the programmable logic element 10 set the input / output ports 19 and 21 of the programmable logic element 10 after the definition is completed. Can be shared by switching between the unused memory 12 for defining the logic function and the other data processing circuits, etc. Since it is directly connected to the input / output port from the outside of the device, it is necessary to configure TTL etc. on the chip, so it becomes large, not only taking up space, but also causing a large delay time and causing a decrease in operation speed . SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems, and has as its object to simplify the configuration of a programmable logic element having a built-in memory and a data processing circuit that can be accessed from the outside, and to improve the operation speed. And

[Means for Solving the Problems]

The present invention relates to a programmable logic element whose logic function is determined by definition data input from the outside,
An externally accessible memory is provided in the programmable logic element, and an address bus or a data bus to which the memory is connected is at least part of an address bus or a data bus for externally inputting the definition data. The above-mentioned object has been achieved by commonality. The present invention also provides a programmable logic element having a data processing circuit accessible from the outside in the programmable logic element, and a data bus to which the data processing circuit is connected, wherein the definition data is transmitted from the outside. The above-mentioned object is also achieved by sharing at least a part of an external address or data bus for inputting.

[Action and effect]

In the present invention, at least a part of an address bus or a data bus to which a built-in memory or a data processing circuit accessible from the outside is connected is provided with an address bus or a data bus for inputting definition data from the outside, or an external address. Since at least a part of the bus and the data bus is shared, at least a part of the external changeover switch becomes unnecessary.
Therefore, an external changeover switch, which conventionally requires a large area, becomes unnecessary, and the area can be greatly reduced. Also, since the external changeover switch is connected to the input / output port from outside the programmable logic element, a large capacity is required, and the delay time is long, which has been one of the causes of a decrease in operation speed. , Because this is gone,
The operation speed can be improved. The built-in changeover switch remains, but since it is small, the operation speed is high and there is no problem. Further, conventionally, in order to reduce the number of external changeover switches, for example, 8-bit data is input as it is to the master logic element, but one bit is input to the other slave logic elements. Since transferring unnecessary data reduces useless external changeover switches and input / output ports, it takes time to define the slave logic element. In contrast, according to the present invention,
Similarly to the master logic element, the slave logic element is input from the ROM 30 or the like via the data bus.
For example, since 8-bit definition data can be transferred as it is, the time for definition can be greatly reduced. According to the present invention, the input / output port for definition and the input / output port of the built-in memory or data processing circuit are shared, so that the external connection connected to the input / output port is also shared. During normal operation after the definition is completed, the data bus from the ROM does not contain data for definition, so
There is no problem.

【Example】

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In an embodiment in which the present invention is applied to a programmable logic element having a built-in memory, basically, as shown in FIG. 1, an address generation circuit 11 and an access to the ROM 30 from the address generation circuit 11 via an address bus 34 are performed. A logic function defining memory 12 for storing definition data taken from the ROM 30 via the data bus 32, an internal memory 40 accessible from the outside, and a connection to the data bus 32, which can be switched. Thus, a common input / output (I / O) circuit 50 for selectively inputting data to the logic function defining memory 12 and the built-in memory 40, and the address bus 34
The input / output circuit 52 for partially outputting data from the internal memory 40 and the address generation circuit 11 is selectively connected to the input / output circuit 52 and another normal input / output (I / O) ports 54, 56 and 58. As shown in detail in FIG. 2, the input / output circuits 50 and 52 have input / output ports 50A and 52A,
It consists of 50B and 50B. In this embodiment, the address is 16 bits, which covers more than 8 bits of the normal data, so that the unshared portion of the input / output circuit 52 is connected to the external logic circuit (functional block) 37. For example, half of the conventional 8
External changeover switches 60 corresponding to bits are left. The overall configuration of the main part in this embodiment is as shown in FIG. 3, and part of the data bus 32 and the address bus 34 are shared by the circuit definition data and the SRAM external data. In the figure, 60 is a central processing unit (CPU), and 62 is a control bus. In the present embodiment, when the power is turned on, the control bus 62 accesses the ROM 30 under control of the CPU 60 to call the definition data. The recalled data is sent to the data bus 32
After that, the data is stored in the logic function definition memory 12 through the shared input / output circuit 50. On the other hand, during normal operation after the end of the definition, the input / output circuits 50 and 52 are switched to
Data is input and output from the SRAM 40 to the outside.
Further, under the control of the CPU 60, general data is called from the ROM 30. In the present embodiment, since the present invention is applied to the programmable logic element 10 in which the SRAM 40 is built, not only the input / output circuit 50 on the input side but also a part of the input / output circuit 52 on the output side can be shared. , The effect is great. The application of the present invention is not limited to this. The present invention can be similarly applied to a case where a general data processing circuit is built in instead of the SRAM 40 and the data processing circuit is to be accessible from outside. Note that, depending on the data processing circuit, the input / output circuit on the output side is not required, and therefore the input / output circuit 52 does not need to be shared with the logic function defining memory 12.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a schematic configuration of an embodiment of a programmable logic element according to the present invention, FIG. 2 is a circuit diagram showing a detailed configuration of the embodiment, and FIG. 3 contains the embodiment. FIG. 4 is a block diagram schematically showing an overall configuration of the system, FIG. 4 is a circuit diagram showing an example of a conventional programmable logic element, and FIG. 5 is a block showing an example of a system including a plurality of programmable logic elements. FIG. 6 is a circuit diagram showing a configuration of a comparative example in which an SRAM is incorporated by improving the conventional example. 10: Programmable logic element, 11: Address generation circuit (counter), 12: Memory for logic function definition, 30:
Read-only memory (ROM), 32 Data bus, 34
…… Address bus, 40 …… Built-in memory (SRAM), 50, 52
…… I / O circuit, 50A, 52A …… I / O ports, 50B, 52B
... Built-in changeover switch.

Claims (2)

(57) [Claims] 1. A programmable logic device whose logic function is determined by definition data input from the outside, comprising a memory accessible from outside in the programmable logic device, and an address bus to which the memory is connected. A programmable logic element, wherein a data bus is shared with at least a part of an address bus or a data bus for externally inputting the definition data. 2. A programmable logic element whose logic function is determined by definition data input from the outside, comprising a data processing circuit accessible from outside in the programmable logic element, wherein the data processing circuit is connected. And a data bus shared by at least a part of an external address or a data bus for inputting the definition data from outside.