Deprecated: The each() function is deprecated. This message will be suppressed on further calls in /home/zhenxiangba/zhenxiangba.com/public_html/phproxy-improved-master/index.php on line 456
JP2773087B2 - Electronic component mounting method - Google Patents
[go: Go Back, main page]

JP2773087B2 - Electronic component mounting method - Google Patents

Electronic component mounting method

Info

Publication number
JP2773087B2
JP2773087B2 JP3062162A JP6216291A JP2773087B2 JP 2773087 B2 JP2773087 B2 JP 2773087B2 JP 3062162 A JP3062162 A JP 3062162A JP 6216291 A JP6216291 A JP 6216291A JP 2773087 B2 JP2773087 B2 JP 2773087B2
Authority
JP
Japan
Prior art keywords
solder
reflow
electronic component
qfp
paste
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP3062162A
Other languages
Japanese (ja)
Other versions
JPH04297090A (en
Inventor
隆 薄葉
Original Assignee
アイワ株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by アイワ株式会社 filed Critical アイワ株式会社
Priority to JP3062162A priority Critical patent/JP2773087B2/en
Publication of JPH04297090A publication Critical patent/JPH04297090A/en
Application granted granted Critical
Publication of JP2773087B2 publication Critical patent/JP2773087B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistors
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3421Leaded components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistors
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3465Application of solder

Landscapes

  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は電子部品の実装方法、特
にQFP(Quad Flat Package)、SOP(Single
Outline Package)等のプリント基板への電子部品実
装方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for mounting an electronic component, in particular, a QFP (Quad Flat Package) and an SOP (Single).
(Outline Package) and the like.

【0002】[0002]

【従来の技術】近年、電子機器の軽薄短小化の進展に伴
い面実装技術が普及しており、様々なICチップ部品の
ような面実装電子部品が使用されるようになった。
2. Description of the Related Art In recent years, as electronic devices have become lighter, thinner and smaller, surface mounting technology has become widespread, and surface mounting electronic components such as various IC chip components have been used.

【0003】ICチップ部品特に上記ICパッケージの
プリント基板への実装方法としては、リフローハンダ
付、浸漬(dip)ハンダ付、コテハンダ付などが用い
られるが、最近では高密度実装が可能なリフローハンダ
付けが主流となっている。
[0003] As a method of mounting IC chip parts, especially the above-mentioned IC package, on a printed circuit board, reflow soldering, dip soldering, iron soldering, and the like are used. Recently, reflow soldering capable of high-density mounting is used. Is the mainstream.

【0004】ところで、面実装電子部品の中で半導体I
C電子部品では高集積化によりリード(ピン)数が増大
しており、リードピッチの狭小化が進んでいる。
[0004] By the way, among the surface mount electronic components, semiconductor I
The number of leads (pins) of C electronic components is increasing due to higher integration, and lead pitches are becoming narrower.

【0005】[0005]

【発明が解決しようとする課題】これらの半導体IC電
子部品をプリント基板に実装する方法は、ペースト状ハ
ンダを用いたリフローハンダ付工法が用いられるが、各
リード間のピッチが狭くなっているため、ハンダ付工程
で各リード間でハンダブリッジなどの欠陥が発生しやす
くなっている。
As a method of mounting these semiconductor IC electronic components on a printed circuit board, a reflow soldering method using paste solder is used, but the pitch between the leads is narrow. In the soldering process, defects such as solder bridges are easily generated between the leads.

【0006】図5はこの欠陥であるハンダブリッジを説
明するための工程断面図である。まず、図5(a1)お
よび(a2)に示すように、面実装電子部品例えばQF
Pを実装するプリント基板10上に形成された銅(C
u)からなるCuボンディングパッド(以下、Cuパッ
ドと記す)11上に図5(b1)および(b2)に示す
ようにペースト状ハンダ12を印刷する。
FIG. 5 is a process sectional view for explaining a solder bridge which is this defect. First, as shown in FIGS. 5A1 and 5A2, a surface mount electronic component such as QF
Copper (C) formed on the printed circuit board 10 on which P is mounted
As shown in FIGS. 5 (b1) and (b2), a paste solder 12 is printed on a Cu bonding pad (hereinafter, referred to as Cu pad) 11 made of u).

【0007】次に、図5(c1)および(c2)に示す
ように、QFPのリード13をプリント基板10に装着
する。このQFPの装着ではQFPのリード13をプリ
ント基板10のCuパッド11上のペースト状ハンダ1
2にセットする。次に、QFPを装着したプリント基板
10をリフロー炉(図示せず)内に搬送し、リフロー炉
内の高温雰囲気(183℃以上)で加熱してペースト状
ハンダを溶融(図5(d1)および(d2))して溶融
ハンダ14を形成し、その後プリント基板10を炉から
搬出することによりプリント基板10を冷却する。この
冷却により、リフロー工程で溶融したハンダが固化さ
れ、QFPのリード13がプリント基板10のCuパッ
ド11に接合される。
[0007] Next, as shown in FIGS. 5 (c 1) and (c 2), the leads 13 of the QFP are mounted on the printed circuit board 10. In mounting the QFP, the lead 13 of the QFP is connected to the paste solder 1 on the Cu pad 11 of the printed circuit board 10.
Set to 2. Next, the printed circuit board 10 on which the QFP is mounted is transported into a reflow furnace (not shown), and heated in a high-temperature atmosphere (183 ° C. or higher) in the reflow furnace to melt the paste solder (see FIG. 5 (d 1)). (D2)) to form the molten solder 14, and thereafter, the printed board 10 is cooled by unloading the printed board 10 from the furnace. By this cooling, the solder melted in the reflow step is solidified, and the leads 13 of the QFP are joined to the Cu pads 11 of the printed circuit board 10.

【0008】しかし、上記リフロー炉内の温度分布は一
様でなく、リフロー炉を通過する面実装電子部品も各部
位により温度差を生じ、ハンダの溶融状態にばらつきを
生じると、図5(e1)および(e2)に示すように、
ある隣り合うリード13間でハンダ同士が接合する、い
わゆるハンダブリッジ15を生じる。16は固着ハンダ
である。従来ハンダ接合するプリント基板上のペースト
状ハンダの材質とリードのメッキ等の被覆材質としては
同質の例えばSn−Pb(7:3)ハンダ共晶合金を用
いていた。
However, if the temperature distribution in the reflow furnace is not uniform, and the surface-mounted electronic components passing through the reflow furnace also generate a temperature difference at each part and the molten state of the solder varies, FIG. ) And (e2),
A so-called solder bridge 15, in which solder is joined between adjacent leads 13, is generated. Reference numeral 16 denotes a fixed solder. Conventionally, the same material, eg, Sn-Pb (7: 3) solder eutectic alloy, has been used as the material of the paste solder on the printed circuit board to be soldered and the coating material such as lead plating.

【0009】上記ハンダブリッジ対策として、 (1)ペースト状ハンダの供給量を減らす。 (2)ハンダ粒径の均一化、微粒化により印刷精度を向
上させる。 等があるが、上記ハンダブリッジを一掃することは不可
能であった。
As a measure against the above-mentioned solder bridge, (1) The supply amount of the paste solder is reduced. (2) Improve printing accuracy by making the solder particle size uniform and fine. However, it was impossible to wipe out the solder bridge.

【0010】そこで、本発明は、上記リフローハンダ付
工程において、電子部品の接続端子であるリード間で生
ずる欠陥の1つであるハンダブリッジを防止できる電子
部品の実装方法を提供することを目的とする。
SUMMARY OF THE INVENTION It is an object of the present invention to provide a method of mounting an electronic component capable of preventing a solder bridge which is one of defects generated between leads which are connection terminals of the electronic component in the reflow soldering step. I do.

【0011】[0011]

【課題を解決するための手段】上記課題は本発明によれ
ば、基板上にペースト状ハンダを供給し、リフローハン
ダ付法によって電子部品を接合実装するに際し、前記ペ
ースト状ハンダとして前記電子部品の接合部表面材料の
融点より高い融点のハンダを用いることを特徴とする電
子部品の実装方法によって解決される。
According to the present invention, a paste solder is supplied onto a substrate, and when the electronic component is bonded and mounted by a reflow soldering method, the paste solder is used as the paste solder. The problem is solved by a method for mounting an electronic component, characterized in that solder having a melting point higher than the melting point of the surface material of the joint is used.

【0012】本発明では、プリント基板上に実装される
電子部品のリードの表面材料としては、例えばSn−P
b−Bi系ハンダ(固相線温度(ST):120〜13
0℃、液相線温度(LT):152〜168℃)が好ま
しく、プリント基板上に設ける上記リード表面材料の融
点より高い融点のペースト状ハンダとしてはSn−Pb
系の共晶ハンダ(融点183℃)が好ましい。本発明で
はプリント基板に被着させるペースト状ハンダの融点は
リードの表面材料の融点より10〜30℃程度高いこと
が共晶ハンダ粒が一挙に溶融凝集する力を緩和するのに
好ましい。
According to the present invention, the surface material of the lead of the electronic component mounted on the printed board is, for example, Sn-P
b-Bi solder (solidus temperature (ST): 120 to 13)
0 ° C., liquidus temperature (LT): 152-168 ° C.). Sn-Pb is a paste solder having a melting point higher than the melting point of the lead surface material provided on the printed circuit board.
Eutectic solder (melting point 183 ° C.) is preferred. In the present invention, it is preferable that the melting point of the paste solder to be applied to the printed circuit board is higher by about 10 to 30 ° C. than the melting point of the surface material of the lead in order to alleviate the force at which the eutectic solder particles melt at once.

【0013】[0013]

【作用】本発明によれば、プリント基板1のハンダ接合
部に形成されるペースト状ハンダ3の融点が実装される
電子部品のリード4の表面材料の融点より高く選択され
ている。従って、リフロー工程のプリヒートの昇温工程
(約100〜170℃)において、リード4表面の低溶
融ハンダの溶融部へ共晶ハンダ粒子が徐々に拡散せしめ
られて本加熱時(183℃以上)に共晶ハンダ粒が一挙
に溶融凝集する力が緩和される。この溶融凝集力の緩和
によって、従来問題であった実装密度高低による部分的
温度不均一が起因して高温度リード部へのハンダが集中
することにより生ずるブリッジ現象が防止される。
According to the present invention, the melting point of the paste solder 3 formed at the solder joint of the printed circuit board 1 is selected to be higher than the melting point of the surface material of the lead 4 of the electronic component to be mounted. Therefore, in the preheating temperature raising step (about 100 to 170 ° C.) of the reflow step, the eutectic solder particles are gradually diffused into the molten portion of the low melting solder on the surface of the lead 4, and during the main heating (183 ° C. or higher) The force at which the eutectic solder particles are melted and aggregated at once is reduced. The relaxation of the melt cohesion prevents the bridging phenomenon caused by the concentration of solder on the high-temperature lead portion due to the partial temperature nonuniformity due to the high or low mounting density, which has been a problem in the past.

【0014】[0014]

【実施例】以下、本発明の実施例を図面に基づいて説明
する。
Embodiments of the present invention will be described below with reference to the drawings.

【0015】図1は本発明に係る電子部品実装方法の実
施例を示す断面図である。図2は本発明に係る実施例に
使用された電子部品QFP(Quad Flat Package)の
一例を示す斜視図であり、図2で示したQFP7のリー
ド本数はわかりやすくするため16本となっているが、
実際は48本のものを使用した。
FIG. 1 is a sectional view showing an embodiment of an electronic component mounting method according to the present invention. FIG. 2 is a perspective view showing an example of an electronic component QFP (Quad Flat Package) used in the embodiment according to the present invention. The number of leads of the QFP 7 shown in FIG. 2 is 16 for easy understanding. But,
Actually, 48 pieces were used.

【0016】本実施例では、まず図1(a)に示すよう
に、プリント基板1にランドとして形成されたCuボン
ディングパッド(以下、Cuパッドと記す)2の上に例
えば融点が183℃のSn−Pb(7:3)系合金ハン
ダ状ペーストを予め印刷被着しておき、従来技術で説明
した工程と同様の方法で、QFP7をプリント基板1に
接合実装する。
In this embodiment, first, as shown in FIG. 1A, a Cu bonding pad (hereinafter, referred to as a Cu pad) 2 formed as a land on a printed circuit board 1 is, for example, Sn having a melting point of 183 ° C. A Pb (7: 3) alloy solder paste is printed and applied in advance, and the QFP 7 is bonded and mounted on the printed circuit board 1 in the same manner as the process described in the related art.

【0017】すなわち、QFP7のセラミックICパッ
ケージ6に具備され、材質が42合金で表面に上記Sn
−Pb系合金ハンダより融点が低いSn−Pb−Bi系
合金を約10μmの厚さにメッキしたリード4を図1
(a)のCuパッド2上のSn−Pb系のペースト状ハ
ンダ部に装着させ、リフロー炉に装入した。
That is, it is provided in the ceramic IC package 6 of the QFP 7 and is made of 42 alloy and has
FIG. 1 shows a lead 4 plated with a Sn—Pb—Bi alloy having a melting point lower than that of a Pb alloy solder to a thickness of about 10 μm.
(A) was mounted on a Sn-Pb based solder paste on the Cu pad 2 and charged into a reflow furnace.

【0018】本実施例で使用したリード表面材料用のS
n−Pb−Bi3元合金組成は表1に示す通りA,B,
CおよびDの4種類とした。なお、それぞれの合金の固
相線温度(ST)および液相線温度(LT)も表1に示
す。
S for the lead surface material used in this embodiment
As shown in Table 1, the n-Pb-Bi ternary alloy composition is A, B,
C and D were selected. Table 1 also shows the solidus temperature (ST) and liquidus temperature (LT) of each alloy.

【0019】[0019]

【表1】[Table 1]

【0020】 [0020]

【0021】図4に使用ペースト状ハンダの共晶点と共
に上記リード表面材料のA,B,C,DのST,LT温
度の関係を示す。
FIG. 4 shows the relationship between the eutectic point of the solder paste used and the ST and LT temperatures of A, B, C and D of the lead surface material.

【0022】本実施例で用いたQFP7は、0.5mm
ピッチの48本のリード(ピン)のものでリフロー工程
によるハンダ付工程ではリード表面材料として上記A,
B,C,Dの他に、従来例としてペースト状ハンダと同
一のSn−Pb(7:3)合金を使用した。
The QFP 7 used in this embodiment is 0.5 mm
In the soldering process by the reflow process with 48 leads (pins) of pitch, the above A,
In addition to B, C, and D, the same Sn—Pb (7: 3) alloy as the paste solder was used as a conventional example.

【0023】本実施例及び従来例を用いたリフローハン
ダ付工程のリフロー温度プロファイルを図3に示す。
FIG. 3 shows a reflow temperature profile in the reflow soldering process using the present embodiment and the conventional example.

【0024】図3に示すように、100〜170℃をプ
リヒート域とし、210〜240℃をリフロー域とし、
リフローピーク温度は230〜240℃であった。
As shown in FIG. 3, 100-170 ° C. is a preheat zone, 210-240 ° C. is a reflow zone,
Reflow peak temperature was 230-240 ° C.

【0025】リフローハンダ付工程の結果をQFPリフ
ローハンダブリッジ発生率について、(A)QFPの個
数当り及び(B)QFPのリードギャップ当りのリフロ
ーハンダブリッジ発生率をそれぞれ表2に示す。
The results of the reflow soldering process are shown in Table 2 with respect to the QFP reflow solder bridge occurrence rate and (A) the reflow solder bridge occurrence rate per number of QFPs and (B) the read gap per QFP.

【0026】尚、QFPの試料数は200個であり、Q
FPの個数当りのリフローハンダブリッジ発生率(A)
及びQFPのリードギャップ当りのリフローハンダブリ
ッジ発生率(B)は次式によりそれぞれ与えられる。 (A)QFPの個数当りのリフローハンダブリッジ発生
率(%)=(ハンダブリッジが発生したQFPの個数/
200個)×100% (但し、同一QFPにおいて複数箇所のブリッジが発生
したとしても、1個としてカウントする。) (B)QFPのリードギャップ当りのリフローハンダブ
リッジ発生率(%)=(ブリッジの発生した箇所/20
0個×44)×100% 図1(b)には、ハンダブリッジを起していないリード
4とCuパッドとのハンダ接合状態を示す。5はその固
着ハンダである。
The number of QFP samples is 200,
Reflow solder bridge occurrence rate per number of FPs (A)
And the reflow solder bridge occurrence rate (B) per read gap of the QFP is given by the following equations, respectively. (A) Occurrence rate of reflow solder bridges per number of QFPs (%) = (Number of QFPs with solder bridges /
(200 pieces) × 100% (However, even if a plurality of bridges occur in the same QFP, they are counted as one.) (B) Reflow solder bridge occurrence rate per read gap of QFP (%) = (number of bridges) Occurrence location / 20
0 × 44) × 100% FIG. 1B shows a solder bonding state between the lead 4 and the Cu pad where no solder bridge is caused. Reference numeral 5 denotes the fixing solder.

【0027】[0027]

【表2】[Table 2]

【0028】 [0028]

【0029】表2に示すように、リード表面材料A,
B,C,D合金を用いた本発明の場合は、通常のSn−
Pb(3:1)合金を用いた従来例の場合よりリフロー
ブリッジ発生数が非常に低下した。
As shown in Table 2, the lead surface materials A,
In the case of the present invention using B, C, and D alloys, the ordinary Sn-
The number of reflow bridges generated was much lower than in the conventional example using a Pb (3: 1) alloy.

【0030】[0030]

【発明の効果】以上説明したように、本発明によれば、
リフローハンダ付において、リードへのハンダの偏在化
が防止され、各リード間で発生するハンダブリッジの発
生が防止される。
As described above, according to the present invention,
In the reflow soldering, the uneven distribution of the solder to the leads is prevented, and the occurrence of a solder bridge between the leads is prevented.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明に係る電子部品の実装方法の実施例を示
す図である。
FIG. 1 is a view showing an embodiment of a method for mounting an electronic component according to the present invention.

【図2】本発明に係る実施例に使用されたQFP(Qua
d Flat Package)の一例を示す斜視図である。
FIG. 2 shows a QFP (Qua) used in the embodiment according to the present invention.
FIG. 4 is a perspective view showing an example of (Flat Package).

【図3】実施例で用いたリフローハンダ付工程のリフロ
ー温度プロファイルを示す図である。
FIG. 3 is a diagram showing a reflow temperature profile in a reflow soldering step used in the example.

【図4】使用リードの表面材料(メッキ材)の融点と使
用ペースト状ハンダの融点との関係を示す図である。
FIG. 4 is a diagram showing the relationship between the melting point of the surface material (plating material) of the lead used and the melting point of the solder paste used.

【図5】従来技術の説明図である。FIG. 5 is an explanatory diagram of a conventional technique.

【符号の説明】[Explanation of symbols]

1,10 プリント基板 2,11 Cuボンディングパッド 3 ペースト状ハンダ(Sn−Pb系) 4 リード(表面にSn−Pb−Bi系合金メッキ) 5,16 固着ハンダ 6 セラミックICパッケージ 7 QFP(Quad Flat Package) 12 ペースト状ハンダ(Sn−Pb系) 14 溶融ハンダ 15 ハンダブリッジ(欠陥) 1,10 Printed circuit board 2,11 Cu bonding pad 3 Paste solder (Sn-Pb-based) 4 Lead (Sn-Pb-Bi-based alloy plating on the surface) 5,16 Fixed solder 6 Ceramic IC package 7 QFP (Quad Flat Package) ) 12 Paste solder (Sn-Pb) 14 Melting solder 15 Solder bridge (defect)

───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.6,DB名) H05K 3/34 505 H05K 3/34 507──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. 6 , DB name) H05K 3/34 505 H05K 3/34 507

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 基板上にペースト状ハンダを供給し、リ
フローハンダ付法によって電子部品を接合実装するに際
し、前記ペースト状ハンダとして前記電子部品の接合部
表面材料の融点より高い融点のハンダを用いることを特
徴とする電子部品の実装方法。
When supplying paste solder to a substrate and bonding and mounting an electronic component by a reflow soldering method, a solder having a melting point higher than a melting point of a bonding surface material of the electronic component is used as the paste solder. A method for mounting an electronic component, comprising:
JP3062162A 1991-03-26 1991-03-26 Electronic component mounting method Expired - Fee Related JP2773087B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3062162A JP2773087B2 (en) 1991-03-26 1991-03-26 Electronic component mounting method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3062162A JP2773087B2 (en) 1991-03-26 1991-03-26 Electronic component mounting method

Publications (2)

Publication Number Publication Date
JPH04297090A JPH04297090A (en) 1992-10-21
JP2773087B2 true JP2773087B2 (en) 1998-07-09

Family

ID=13192147

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3062162A Expired - Fee Related JP2773087B2 (en) 1991-03-26 1991-03-26 Electronic component mounting method

Country Status (1)

Country Link
JP (1) JP2773087B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0870173A (en) * 1994-08-30 1996-03-12 Matsushita Electric Ind Co Ltd Circuit board
CN101976659B (en) * 2010-09-03 2013-12-11 中兴通讯股份有限公司 Outer package-free crystal device and manufacturing method thereof

Also Published As

Publication number Publication date
JPH04297090A (en) 1992-10-21

Similar Documents

Publication Publication Date Title
US7145236B2 (en) Semiconductor device having solder bumps reliably reflow solderable
US4740252A (en) Solder paste for electronic parts
CN101208174B (en) Lead-free solder alloy
KR101014756B1 (en) How to Mount Electronic Devices and Electronic Components
KR100776114B1 (en) Paste for soldering and soldering method using the same
JPWO2005072906A1 (en) Soldering flux and soldering method
US6596094B2 (en) Solder paste and electronic device
JP4799997B2 (en) Method for manufacturing printed circuit board for electronic device and electronic device using the same
JP2773087B2 (en) Electronic component mounting method
JP2794644B2 (en) Surface mount electronic components
JP4008799B2 (en) Lead-free solder paste composition and soldering method
JPH09295184A (en) Solder, circuit board on which electronic components are mounted using the solder, and solder paste
JPH07118498B2 (en) Electrical junction
JP3086086B2 (en) How to join lead pins to circuit terminals
JP2002076605A (en) Circuit board connecting semiconductor module and semiconductor device
JP2000332403A (en) Electronic component mounting structure and electronic component mounting method
JP5652689B2 (en) Manufacturing method of electronic component bonded structure and electronic component bonded structure obtained by the manufacturing method
JP3422135B2 (en) Soldering of electronic components to printed circuit boards
JPH0596396A (en) Cream solder
JP3460442B2 (en) Lead-free solder and mounted products using it
JP2000176678A (en) Cream solder and mounting products using it
JP2895855B2 (en) Electronic component mounting method
JP2795535B2 (en) Electronic component mounting method on circuit board
JPH06216507A (en) Solder precoated circuit board
JPH01102946A (en) Mounting of electronic component by reflow soldering

Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees