JP2773589B2 - Computer system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a computer system,
In particular, the present invention relates to a computer system using a power source having a limited life, such as a battery.

[0002]

2. Description of the Related Art The configuration of a conventional computer system is shown in FIG. As shown in FIG. 1, the conventional computer system generates an output signal having a constant output frequency by a digital computer 41 and a fixed frequency oscillator 42 (a) such as a crystal oscillator. , And a power supply 43 for supplying power thereto. The power supply 43 supplies the voltage obtained from the battery 43 (a) to the entire computer system via the stabilizer 43 (b) to supply the voltage V _CC . Reference numeral 44 denotes a read-only memory (hereinafter, referred to as a ROM), 45 denotes a random access memory (hereinafter, referred to as a RAM), 46 denotes an input device, and 47 denotes an output device, which are connected to the digital computer 41.

In such a conventional computer system, when a battery 43 (a) or the like having a limited life is used as the power supply 43, the battery 4 is used as the power supply 43 is used.
The voltage of 3 (a) decreases. The power supply voltage is kept constant by the stabilizing device 43 (b) until the battery voltage drops to a certain level.
_CC also starts to decline. On the other hand, the clock oscillator 42 always outputs a signal having a constant oscillation frequency determined by the fixed frequency oscillator 42 (a) such as a crystal oscillator, regardless of a change in the power supply voltage.

However, the digital computer 4
1. Digital devices constituting the entire computer system such as the ROM 44 and the RAM 45 are supplied with the supplied voltage V _CC.
When the power supply voltage starts dropping due to the discharge of a battery used as a power supply in a computer system, the digital computer 4 suddenly stops without notice.
There is a possibility that the first system or the like becomes inoperable and the whole system stops.

In order to solve such a problem, a change in the power supply voltage is detected, and based on the change, a fixed oscillation frequency obtained from a frequency oscillator is divided by a frequency divider or the like to change the frequency. A configuration corresponding to a change in power supply voltage has been proposed (eg, Japanese Patent Application Laid-Open Nos. 1-255021 and 61-6721).

[0006]

However, in such a configuration, the frequency output from the frequency oscillator, which is the source of the clock frequency, is always constant as in the prior art, and is divided by the configuration after the clock frequency generation source. Since the frequency is selected by the frequency divider, an additional configuration such as software control means for selecting the frequency is additionally required, and it is inevitable that the configuration of the entire system becomes complicated. When a frequency divider is used, the selectable frequency values are usually about two or three types. If it is attempted to select a plurality of types of frequencies, the configuration becomes more complicated.

The present invention focuses on the problem that when a computer system is operated using a power supply having a limited life such as a battery, the voltage drops when the life of the battery is reduced, and the power supply voltage is reduced with a simpler configuration. The power consumption is reduced by lowering the clock frequency in accordance with the decrease of the clock frequency to slow down the operation of the computer system, thereby increasing the operating time of the entire system and slowing down the operation of the computer system before the system operation stops. Accordingly, it is an object of the present invention to provide a computer system that allows a user to know in advance a decrease in power supply voltage.

[0008]

In order to achieve this object, a computer system according to the present invention senses a voltage change of a power supply without having a fixed frequency oscillator such as a crystal, and generates a clock corresponding to the voltage change. It is characterized by comprising a variable frequency clock generating means for generating a frequency, and a digital device such as a digital computer operated by a clock oscillated by the variable frequency clock generating means.

[0009]

According to the above arrangement, a change in the power supply voltage is sensed,
Since the output clock frequency is changed by the frequency variable clock generator, the clock frequency given to the digital computer decreases in accordance with the decrease in the power supply voltage, and the operation and response of the entire computer system gradually decrease.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIGS.

FIG. 1 shows a battery-driven personal computer.
FIG. 3 is a block diagram showing the configuration of FIG. In the figure, 1 is 8
Bit or 16 bit digital computer,
In addition to the storage devices such as the ROM 2 and the RAM 3, the input device 4 and the output
The data input / output device of the input device 5 is connected. Input device
The device 4 is, for example, a keyboard of a personal computer.
And the output device 5 is, for example, a CRT or the like.
Using the display. These digital computers
1, ROM 2, RAM 3, input device 4, and output device
5 is an 8-bit or 16-bit data bus 8
And each is electrically grounded.
I have. Reference numeral 6 denotes a power supply, and a voltage obtained from the battery 6 (a).
Is supplied to the entire system via the stabilizing device 6 (b).
Pressure V _CCSupply). Thus, the stabilizing device 6 (b)
, Regardless of battery voltage changes
The whole system operates stably. The battery 6 (a)
Voltage obtained from_INThe frequency variable clock generation directly
It is supplied to the device 7. This variable frequency clock generator 7
And the output voltage V of the power supply 6_INSenses the change in_INIs low
Lowers the oscillation frequency accordingly,
Decrease the clock frequency supplied to the system.

The variable frequency clock generator 7 will be described in more detail. FIG. 2 shows an embodiment of the variable frequency clock generator 7. In the figure, 11 and 12 are operational amplifiers,
13 is a transistor, 14 is a logic IC, 15 to 25
Is a resistor, and 26 and 27 are capacitors.

The variable frequency clock generator 7 comprises a noise removing section (a) and a variable frequency generating section (b). The noise removing section (a) is composed of a resistor 25 and a capacitor 27, and serves to remove ripples (pulsations of the power supply voltage) and noise components from the power supply and to stabilize the operation of the next variable frequency generating section (b). Have.

The variable frequency generator (b) is divided into a transistor 13 acting as an electronic switch, an integrator and a comparator. Of these, the integrators are resistors 22 to 2
4, the capacitor 26, and the operational amplifier 12. The resistance of the resistors 22 and 23 must be the resistance value (22)
= Resistive value (23), and has the role of keeping the voltage value at point B at 1/2 of point C. The comparator includes an operational amplifier 11, a logic IC 14, and resistors 16 to 19. This comparator realizes a comparator having hysteresis by a positive feedback circuit including a logic IC 14 and resistors 17 to 19.

The operation of the variable frequency generator (b) will be described.
Will be explained. When transistor 13 is off (ie,
When the gate voltage of the transistor 13 is low),
Current does not flow to the transistor side, only to the capacitor 26 side
As the capacitor flows, the capacitor 26 is charged and the potential at the point A is
Goes up. When the potential at the point A rises, the operational amplifier 12
Since the potential of the eggplant-side input rises, the output of the operational amplifier 12
, The potential at point D decreases. Further, the potential at point D drops
And the negative input of the operational amplifier 11 decreases,
The potential at the output point F of the amplifier 11 rises. This output point F
When the potential becomes high, the transistor 13 is turned on.
Become. When the transistor 13 is turned on, the transistor
Since current flows to the transistor 13 side, the charged capacitor
The capacitor 26 discharges via the resistor 21. Due to this discharge
The potential at point A drops, and the output of operational amplifier 12 is D
Since the potential at the point rises, the potential at the output F point eventually falls
Low level. Then again the transistor 13 is turned off.
State. By repeating such operation, point F
Of the output terminal F repeats high level and low level.
_OUTMore clock frequency output is obtained.

In order to change the output clock frequency, the resistance values of the resistors 22 to 24 and the capacitance of the capacitor 26 may be changed. For example, in order to lower the frequency (extend the period), increase the capacitance of the capacitor 26, increase the resistance of at least one of the resistors 22 to 24, or increase both values. I just need. Conversely, if you want to increase the frequency,
The capacity and / or the resistance value may be reduced.

The relationship between the clock frequency and the capacitor 26 and the resistors 22 to 24 will be further described with reference to FIG. FIG. 3 is a timing chart showing a potential change at point D in FIG. In the figure, the potential V D at the point _D , the time Δt, and the clock frequency f have the relationship shown in the following equation.

F∝1 / Δt = I / (C × V _D ) = V _IN /
(V _D × R × C) Here, C is the capacitance of the capacitor 26, I is the current value, R is the resistance value of the resistor 24, and V _IN is the battery voltage. That is, the value of the clock frequency f increases as the input voltage V _IN increases, and as the resistance value, the capacitance of the capacitor, and the current value decrease.

Next, the operational amplifier 11, the logic IC 14
The operation of the positive feedback circuit including the resistors 17 to 19 will be described with reference to FIG. FIG. 4 (a), (b), (c)
3 is a timing chart showing potentials at points D, F and E in the circuit of FIG. FIG rising potential at point D is progressively (a), the output point F upon reaching a threshold voltage V ₁ of the upper, the potential at the point E the figure (b),
The potential becomes low as shown in FIG. On the other hand, when the potential at the point D drops and drops to the lower threshold voltage V ₀ , the outputs F and E become high level potentials. The reason for such behavior is that a comparator having hysteresis is realized by the positive feedback circuit. Also,
By providing the logic IC 14 and the resistors 18 and 19, the potential at the point E fluctuates to ± V ₂ around the middle point O, and the value of V ₂ becomes smaller than the amplitude at the point F. Can be stable.

The operation of the entire computer system of the present embodiment configured as described above will be described below.

The power supply 6 composed of a battery keeps a predetermined voltage or more for a predetermined time after the start of discharging. However, as the battery life becomes shorter, its output voltage gradually decreases. When the power supply voltage decreases, the value of the current flowing into the frequency variable clock generator 7 decreases from the above relationship, so that the clock frequency also decreases. The characteristics of the change are shown in FIG.
As shown in (1), when the power supply voltage decreases, the output clock frequency linearly decreases accordingly. As described above, when the system clock frequency decreases, the power consumption of the entire system decreases and the operation (response) of the computer system also slows, so that the user can know in advance that the battery life is approaching. In particular, if the frequency characteristic with respect to the power supply voltage is made linear as shown in FIG. 5, the operation (response) of the computer system is also linearly delayed according to the change in the power supply voltage, so that the battery life can be kept longer. . Note that the slope of the voltage-frequency characteristic shown in FIG. 5 is determined by the relationship between the resistance value of the resistor 24 and the capacitance of the capacitor 26 in FIG.

In the above embodiment, the case where the characteristic of the power supply voltage versus the output clock frequency realized by the variable frequency clock generator 7 is linear has been described. Is not limited to this relationship, and as shown in FIG. 6, a constant clock frequency is generated if the power supply voltage is equal to or higher than the constant value Va, and the voltage value Va is set in accordance with the characteristics of the digital equipment of the entire computer system. In the following, the characteristics may be such that the clock frequency is gradually reduced. Va in this case is preferably set to a value slightly larger than the threshold voltage at which the digital computer does not operate. For example, if the threshold voltage of the digital device is 3.0 V, it is preferable to keep Va at 3.5 V or more for safety.

FIG. 7 shows a configuration for obtaining the characteristics shown in FIG. 2A and 2B respectively correspond to the noise removing section (a) and the variable frequency generating section (b) in FIG. The difference from the circuit configuration shown in FIG.
The Zener diode 28 is provided between the noise removing section (a) and the variable frequency generating section (b). In general, a Zener diode has a characteristic that when a voltage higher than a certain value is applied, a current suddenly starts flowing, and conversely, at a voltage lower than a certain value, almost no current flows. A diode 28 is used. That is, by using the Zener diode 28, if the voltage V _IN is equal to or more than a predetermined value while the battery is still new, the current flowing from the noise removing unit (a) to the variable frequency generating unit (b) is smaller than that of the Zener diode 28. Therefore, only a constant voltage is applied to the variable frequency generator (b). That is, even if the voltage V _IN changes, only a fixed clock frequency is output from the frequency variable clock generator 7. However, when the voltage of the battery decreases with the passage of time, that is, when the voltage V _IN becomes lower than a predetermined value, it becomes difficult for the current to flow toward the Zener diode 28, and thus a circuit without the Zener diode 28 (the circuit of FIG. 2) ), The current from the noise removing section (a) almost flows to the variable frequency generating section (b), and the voltage V _IN is applied to the variable frequency generating section (b) as it is. Thus, the voltage-frequency characteristics shown in FIG. 6 are obtained.

As described above, since the frequency was conventionally changed by using the frequency divider, the frequency to be selected was selected by the software of the digital computer. The frequency can be selected (changed) without any intervention, and new functions can be provided without changing existing software. Also, conventionally, when trying to change the frequency in multiple stages, a large number of frequency dividers were required, and the configuration was inevitably complicated,
In the present invention, the frequency can be changed continuously (infinitely many steps) with a simple configuration according to the setting conditions of the frequency variable clock generator.

In particular, a computer system constructed using the CMOS-LSI technology is sensitive to a change in power supply voltage, and the power consumption depends on the operating clock frequency. Is obtained.

[0026]

According to the present invention, the system clock frequency is reduced in accordance with a decrease in the output voltage of a finite power supply such as a battery with a simpler configuration, so that the operation time of the entire system can be extended. . As a result, a fatal trouble such that the digital signal processing portion of a computer system using a battery (for example, a portable device such as a handy personal computer or a notebook personal computer) is stopped and suddenly cannot be used at all is avoided. In addition, the delay in the operation response due to the decrease in the clock frequency makes it possible for the user to be aware of the time to replace the battery, thereby preventing a sudden system shutdown.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment in a computer system of the present invention.

FIG. 2 is a block diagram showing a configuration of an embodiment of a variable frequency clock generator in the computer system of the present invention.

FIG. 3 is a timing chart showing a potential change on a circuit of the variable frequency clock generator of the present invention.

FIG. 4 is a timing chart showing a potential change on a circuit of the variable frequency clock generator of the present invention.

FIG. 5 is a characteristic diagram showing an embodiment of a relationship between an output clock frequency and a power supply voltage of the variable frequency clock generator according to the embodiment of the present invention.

FIG. 6 is a characteristic diagram showing another example of the relationship between the output clock frequency and the power supply voltage of the variable frequency clock generator according to the embodiment of the present invention.

FIG. 7 is a diagram showing a circuit configuration according to another embodiment of the present invention.

FIG. 8 is a block diagram showing a configuration of a conventional computer system.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Digital computer 2 ROM 3 RAM 4 Input device 5 Output device 6 Power supply 7 Frequency variable clock generator 8 Data bus

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-2-23411 (JP, A) JP-A-2-287603 (JP, A) JP-A 61-189327 (JP, U) JP-A 58- 179532 (JP, U) Jpn. Sho 62-175331 (JP, U) (58) Fields investigated (Int. Cl. ⁶ , DB name) G06F 1/26-1/32 G06F 1/04

Claims (1)

(57) [Claims] A power supply voltage generating means for detecting a power supply voltage and corresponding to a change in the power supply voltage;
Frequency variable clock generating means for generating a clock frequency , and a clock generated from the frequency variable clock generating means.
The frequency variable clock generating means operates as a filter for removing noise of the input voltage.
Noise removing unit, and the output of the noise removing unit
And a variable frequency generator that converts
Between the noise removing unit and the variable frequency generating unit.
A voltage filter, wherein the voltage filter has an input voltage
When the voltage is equal to or higher than a certain voltage value, the certain voltage value is changed to the variable frequency.
A computer system for transmitting the information to a generator .