JP2776321B2 - Logic analyzer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic analyzer, and more particularly, to a logic analyzer capable of setting a complicated trigger condition.

[0002]

2. Description of the Related Art A logic analyzer is a measuring device capable of storing the history of changes in signal waveforms at various parts of a circuit in order to analyze the operation of a logic circuit and displaying the history of the change.

FIG. 3 shows an outline of the configuration of a conventionally used logic analyzer. The logic analyzer 101 includes a probe 103 for inputting a signal under measurement requiring waveform observation among the circuit under measurement 102 formed by a logic circuit. The signal under test is input to the logic analyzer through the probe 103. Each signal under test is a digital signal that takes one of two values. Logic analyzer 101
Comprises a trigger condition setting unit 104 for setting a trigger condition;
A trigger detection circuit 105 is provided to detect whether the value of the signal under measurement matches the trigger condition.

The signal to be measured from the probe 103 is input to a trigger detection circuit 105 and a waveform storage memory 106. The waveform storage memory 106 is a memory that stores the waveform of the signal under measurement for a certain period of time before and after the time when the signal under measurement matches the trigger condition by the trigger detection circuit. The display unit 107 includes a waveform storage memory 106
And a CRT display (not shown).

The trigger condition is set by combining conditions such as the value of each signal to be measured, the rise of the signal to be measured, and the fall of the signal to be measured as AND conditions. The trigger condition is set by the operator from the trigger condition setting unit 104 prior to the start of the measurement.
The trigger detection circuit 105 is a circuit that outputs a pulse-like trigger signal 108 when the signal under measurement satisfies the set trigger condition. The trigger detection circuit 105 is a combination of an AND circuit. Trigger condition setting unit 10
4 supplies a gate signal to each AND circuit of the trigger detection circuit according to the set trigger condition, and sets the trigger signal 108 to be output when the signal under measurement matches the trigger condition.

[0006] The waveform storage memory 106 constantly updates its storage content from the start of measurement, and stores the history of changes in the signal under measurement from the present time to a certain time before. When the waveform of the signal under measurement is stored for a certain period before and after the trigger signal 108 is input, the updating of the stored content is stopped and the waveform is held.

Japanese Patent Laid-Open Publication No. Hei 3-4177 discloses a logic analyzer capable of setting a trigger condition by combining both an AND condition and an OR condition. In this logic analyzer, a trigger detection circuit is constituted by an AND array and an OR array whose wiring can be electrically changed. Thus, the trigger condition can be set by arbitrarily combining the AND condition and the OR condition.

[0008]

In these conventional logic analyzers, a trigger condition can be set by combining a signal under measurement with an AND condition or an OR condition.
However, since there is no means for storing the fact that the trigger condition has been met or a means for counting the number of times the condition has been met, a fixed period based on the time when the signal under measurement first meets the trigger condition after the start of the measurement. Can only be recorded. For example, a complex trigger condition such as recording a waveform for a certain period based on a time when the trigger condition is matched three times or a time when the first trigger condition is matched a predetermined number of times and then the second trigger condition is used as a reference. There is a problem that cannot be set. Further, in order to set such a complicated trigger condition with a conventional logic analyzer, it is necessary to provide an external trigger circuit in the logic analyzer, and there is a problem that a waveform measurement operation becomes complicated. .

An object of the present invention is to provide a logic analyzer capable of setting a trigger condition including a change history of a signal under measurement such as the number of times that a predetermined condition is met.

[0010]

According to the first aspect of the present invention, there is provided: (a) a signal for storing a history of changes of a plurality of signals to be measured having any one of two values during a predetermined time. a history storage unit, a trigger condition setting means for setting a plurality of trigger conditions represented by any combination of the values of (b) a plurality of signals to be measured, (c) each trigger conditions set by the trigger condition setting means detecting a match count setting means the value of the signal under measurement is <br/> set the number should correspond at least to each trigger condition that a value of (d) a plurality of measured signal matches each trigger conditions With
The number of times set by the number-of-matches setting means
A trigger condition coincidence detecting means for detecting that the Kutomo matched, (e) a plurality of values of these trigger conditions of the measured signal one
Match all trigger conditions by the match detection means.
Signal history storage means for storing, in the signal history storage means, the history of the change of the signal under measurement for a certain period of time based on the detected time, and (f) a plurality of data stored in the signal history storage means. And a display means for displaying the change history of the signal under measurement.

[0011] That is, in the first aspect of the present invention, a plurality of trigger conditions in any combination of the values of a plurality of <br/> measured signal
And set one for each trigger condition.
Set the number of times to match. And each of these
Match at least the number of times set in the trigger condition
Is detected as a trigger condition match, and
The waveform of the signal under measurement is stored on the basis of the point in time when all the conditions are detected . Thus, for example, each trigger
The value of the signal under test is the same at any time when the condition occurs
Can set a complicated trigger condition, for example, when the trigger condition may match the set number of times or more .

[0012]

[0013]

[0014]

[0015]

[0016]

[0017]

[0018]

FIG. 1 shows an outline of a configuration of a logic analyzer according to an embodiment of the present invention. The probe 11 is an input circuit for taking in signals in each part of the circuit under test 12 into the logic analyzer 13. The circuit under test 12 is composed of a logic circuit, and the signal of each section is a digital signal that takes one of "0" and "1". The waveform recording memory 14 is a memory for storing the history of the change of the value of the signal under measurement during a certain time. Waveform recording memory 14
Is configured to sequentially store the value of the signal under measurement in accordance with a predetermined sampling clock.

The trigger condition setting section 15 is a circuit portion for setting a trigger condition, and includes various operation buttons and an operation panel on which a rotary encoder is arranged. The programmable logic array 16 is a circuit that detects that the signal to be measured matches the set trigger condition. The programmable logic array is set to output a pulse-like trigger signal 17 when detecting a match with a trigger condition. The waveform storage memory 14 constantly updates its storage content from the start of the measurement, and always stores a history of changes in the signal under measurement from the present time to a certain time before. Then, the waveform of the signal under measurement for a certain period before and after the trigger signal 17 is input is finally stored.

The display section 18 is a section for displaying the waveform of the signal under measurement stored in the waveform storage memory 14. The display unit 18 includes a CRT display (not shown) and a display control circuit.

As the trigger condition, a plurality of pre-trigger conditions combining the value of the signal to be measured and the rising and falling of the signal to be measured can be set. Also,
It is possible to arbitrarily set the number of times the value of the signal under measurement should match the pre-trigger condition and the order of the pre-trigger conditions for detecting the match with the signal under measurement.

For example, the following trigger conditions can be set based on the first to eighth signals to be measured. First, the values of the first to eighth signals under measurement are “1”.
A condition that is a combination of “0011011” is set as a first pre-trigger condition. Next, a condition that a value of the first to eighth signals under test is a combination of “00101110” is set as a second pre-trigger condition. And
“1” is set as the number of matches of the first pre-trigger condition,
"3" is set as the number of times the pre-trigger condition matches. Finally, the first pre-trigger condition is set next to the second pre-trigger condition as an order for determining the pre-trigger condition.

As a result, the value of the signal under measurement becomes "001".
After the state of the combination of “01110” arrives three times, a trigger is activated when the value of the signal under measurement becomes the combination of “10011011”.

In addition, by utilizing the storage function of the sequential circuit, for example, each of the first signal under test, the second signal under test, and the third signal under test is at least once in the state of "0". After that, the trigger condition may be set such that the combination of the first to eighth signals to be measured becomes "11100111". In this case, the timing at which the first to third signals to be measured become “0” is arbitrary, and may be “0” at different timings, or two or more signals become “0” simultaneously. Is also good. Further, the same signal under measurement may become “0” twice or more. Since the programmable logic array includes the flip-flop circuit, it is possible to individually store that each of the first to third signals to be measured has become “0”. By taking the logical product of the outputs of these flip-flop circuits, it is possible to easily detect that the first to third signals to be measured have become "0". However, when a sequential logic circuit such as a flip-flop circuit is not provided, it is impossible to determine whether the same signal to be measured has become “0” a plurality of times, and such a trigger condition cannot be set.

FIG. 2 shows an example of the configuration of the programmable logic aire. The programmable logic array includes AND circuits 31 _{1 to} 31 _N ,
A flip-flop circuit 32 ₁ to 32 _N, and a selector circuit 33 ₁ ~ 33 _N and a selector circuit 34 ₁ ~34 _N. The output of the AND circuit 31 is
_{1 to} 33 _N are input. Selector circuits 33 _{1 to} 3
The _3N output is connected to the data terminal and clock terminal of the corresponding flip-flop circuit. Selector circuit 3
4 The ₁ to 34C _N, the output of the AND circuit 31 ₁ to 31 _N, the output signal of the flip-flop circuit 32 ₁ to 32 _N is inputted.

The AND circuits 31 _{1 to} 31 _N each have M
(M> N) and an AND circuit an input, an output of the input selector circuit 34 ₁ to 34C _N of the AND circuit is connected to an array. In addition, the AND circuits 31 _{1 to} 31 _N include:
An arbitrary signal to be measured can be input. In the programmable logic array, whether to connect or not to connect the connection points in the form of an eye can be electrically and arbitrarily changed. Further, it is possible to arbitrarily set in advance which signal is to be selected by each selector circuit. These settings can be arbitrarily changed any number of times. In addition, the programmable logic array is provided with a not-not circuit or an OR circuit (not shown), and the wiring between them is array-like and electrically arbitrarily changeable as in the case of the AND circuit. ing.

When the trigger condition is set by the operator,
The trigger condition setting unit 15 changes the connection state of the wiring in the programmable logic array so as to satisfy the set trigger condition. For example, the first,
A logic circuit that outputs “1” when the second pre-trigger condition is satisfied is formed by combining an AND circuit and a knot circuit. In addition, a counter for counting the number of “1” output from the logic circuit corresponding to the pre-trigger condition is formed by combining a flip-flop circuit and an AND circuit.

In this manner, the history of the change of the waveform of the signal under measurement for a predetermined time before and after the trigger signal 17 is output from the programmable logic array 16 to which the wiring is set is stored in the waveform storage memory 14. To memorize.
After the measurement is completed, the stored waveform is displayed on the display unit 18.

The count of the number of times that matches the pre-trigger condition is:
This is performed for each sampling cycle of the signal under measurement. For example, when a state where the value of the signal under measurement becomes a combination of “00101110” continues for three periods of the sampling clock, it is counted that the pre-trigger condition has arrived three times. In addition, the value of the signal under measurement is “0010111
Regardless of the number of cycles of the sampling clock, the period during which the state of the combination of “0” continues, the signal under measurement may be counted as one as long as the state of the signal under measurement does not change. Is input when a signal output when the value of the combination becomes "00101110" is input as a clock of a counter circuit composed of a flip-flop circuit, such counting can be easily performed.

In the embodiment described above, a logic circuit for detecting a trigger condition is formed by a programmable logic array. However, a combinational logic circuit such as an AND circuit or an OR circuit and a circuit for detecting a trigger condition by a counter circuit are provided. You may comprise. In this case, the connection state of the wiring between each logic circuit and the counter circuit can be changed depending on whether or not the two-input AND circuit provided between each element is gated.

[0031]

As described above, according to the first aspect of the present invention, any combination of the values of a plurality of signals to be measured is triggered.
As a condition, at least the number of times
Detected a match and met all trigger conditions
Since the waveform is stored based on the time point,
If you want to observe in the state consisting of the signal under test
Can you to set up complex trigger conditions such as can be quickly observed.

According to the second aspect of the present invention, the timing for taking in the signal to be measured can be set by combining a plurality of trigger conditions in an arbitrary order and an arbitrary number of times, so that more complicated trigger conditions can be obtained. Can capture the waveform of the signal under measurement.

According to the third aspect of the present invention, a logic circuit for detecting a trigger condition set by combining a combinational logical operation and a sequential logical operation is provided by a plurality of combinational logical operation means and a plurality of sequential logical operation means. Are formed in combination. Since the sequential logic operation means can be combined with the combination logic operation means, it is possible to arbitrarily set various trigger conditions that require the sequential logic operation in addition to the number of times that the trigger condition is matched.

According to the fourth aspect of the present invention, a logic circuit for detecting a trigger condition is constituted by using a programmable logic array, so that a detection circuit corresponding to the set trigger condition can be easily formed. Can be changed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an outline of a configuration of a logic analyzer according to an embodiment of the present invention.

FIG. 2 is a circuit diagram illustrating an example of an outline of a configuration of a programmable logic element.

FIG. 3 is a block diagram showing an outline of a configuration of a conventionally used logic analyzer.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 Probe 12 Circuit under test 13 Logic analyzer 14 Waveform storage memory 15 Trigger condition setting unit 16 Programmable logic array 17 Trigger signal 18 Display unit 31 AND circuit 32 Flip-flop circuit 33, 34 Selector circuit

Claims (1)

(57) [Claims] 1. A signal history storage unit for storing a history of changes of a plurality of signals under test taking any one of two values during a predetermined time period, and an arbitrary value of the plurality of signals under test. Trigger condition setting means for setting a plurality of trigger conditions represented by a combination of the following; and trigger conditions set by the trigger condition setting means.
A number-of-matches setting means for setting, for each trigger condition, at least the number of times that the value of the signal under test should match at least for each trigger condition; and detecting that the values of the plurality of signals under test match for each trigger condition , The coincidence count setting means
Therefore, at least the set number of matches
A trigger condition match detecting means for outputting the trigger condition match
That all of the plurality of trigger conditions are met by means
Signal history storage means for storing the history of the change of the signal under measurement for a certain period of time based on the detected time in the signal history storage means, and the plurality of data stored in the signal history storage means A display means for displaying a history of changes in the signal under measurement.