JPH0670650B2 - Logic analyzer - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic analyzer used for an oscilloscope or the like having a function of repeatedly executing a series of operations for sampling an input digital signal and displaying it on a display device.

2. Description of the Related Art A conventional logic analyzer has a single measurement in which a series of operations such as sampling of an input digital signal, detection of a trigger event, storage of sampled data, display of stored data, etc. Repeated measurement (hereinafter referred to as repeat measurement)
It is configured to be able to. Therefore, during repeat measurement, there is no need to perform a measurement start operation for each measurement, and the measurement data is updated and displayed on the display device after each measurement, so that the optimum measurement can be performed while observing the state change of the input digital signal. Conditions and measurement data display conditions can be specified.

In addition, the speed of the display circuit and the efficiency of the data processing algorithm are configured to shorten the time from the end of measurement to the start of the next measurement, which speeds up the display data update cycle and ensures efficient measurement. Can be done.

However, in the above-described conventional logic analyzer, at the time of repeat measurement, the next measurement starts immediately after the data is displayed after the measurement is completed, so that the input digital signal for each measurement is displayed on the data display screen. However, there is a problem that it is difficult to visually observe the state of and the difference between the signals. Also, while observing the measurement data every time, when the measurement data reaches a certain state, the measurement is stopped, and when the measurement data is analyzed in detail, the measurement data is recognized,
Since the repeat measurement interval is faster than the time until the repeat measurement stop operation, there is a problem that the repeat measurement cannot be surely stopped after the end of the corresponding measurement.

The present invention solves such a conventional problem, and at the time of repeat measurement, after displaying the data after the measurement is finished, a logic analyzer having a function of setting and changing the time until the start of the next measurement is provided. The purpose is to provide.

Means for Solving the Problems In order to achieve the above object, the present invention repeatedly performs a series of measurements such as sampling of an input digital signal, detection of a trigger event, storage of sampled data, display of stored data, etc. Measuring means to perform, means for setting the time from the end of measurement to the start of the next measurement at the time of the repeated measurement, and means for counting the set time,
The logic analyzer was designed so that the repeated measurement interval time in the repeated measurement was set or changed to observe the display data and stop the repeated measurement when a specific display state was reached.

Effect According to the present invention, at the time of repeat measurement, by setting the time (t) until the next measurement start after displaying the data after the end of each measurement, the measurement interval is changed while executing the repeat measurement. Since the measurement data can be operated at an optimum measurement interval while observing the measurement data of each time on the data display screen, the display data can be identified and the repeat measurement stop operation in a specific state can be accurately performed.

Further, by setting the time (t) to 0,
It is also possible to improve the efficiency of measurement and the display data update cycle at the time of repeat measurement that the conventional logic analyzer has.

Embodiment FIG. 1 shows the configuration of an embodiment of the present invention. A digital signal input to a probe 1 is compared with a threshold voltage sent from a D / A converter 2 by a comparator in the probe 1. , High level, and low level are logically shaped and sent to the sample / latch circuit 3. The clock selection circuit 4 selects whether to use an external clock sent from the probe 5 or an internal clock generated by the clock generator 6 as the sampling clock. Sample / latch circuit 3
The signal sent to is sampled by the sampling clock from the clock selection circuit 4. The glitch detection circuit 7 detects a glitch between sampling clocks,
The detection signal is sent to the trigger detection circuit 8. Iodine detection circuit 9
Is a preset word and sample / latch circuit 3
The signals sampled in 1 are compared, and if they match, a detection signal is sent to the trigger detection circuit 8. The edge detection circuit 10 rises the signal sampled by the sample / latch circuit 3,
Alternatively, a falling edge is detected and a detection signal is sent to the trigger detection circuit 8. The trigger detection circuit 8 combines the detection signals from the sample / latch circuit 3, the word detection circuit 9, and the edge detection circuit 10 in a preset combination, and sends the trigger detection signal to the delay counter 11. The delay counter 11 starts its operation by the trigger detection signal and stops when it counts the preset number of delays. When the delay counter 11 stops, the memory address counter 12 also stops at the same time, and the operation of storing the signal sampled by the sample / latch circuit 3 in the buffer memory 13 ends. When the above storage operation is completed, all the signals stored in the buffer memory 13 are transferred to the acquisition memory 14. The data in the acquisition memory 14 is processed according to the display format (slat display, timing display, graph display, etc.) and transferred to the video RAM 15. The display control circuit 16 constantly reads the contents of the video RAM 15 and displays the video signal for display on the display device 17, horizontal
Generates a vertical sync signal.

The series of operations described above are controlled by the CPU 18 by monitoring the information from the keyboard 20 and the logical state of the hardware according to the program stored in the ROM 19.

21 is a reference memory, which is an acquisition memory
Temporarily store by transferring 14 contents. 22 is CP
Work RAM required when the U18 performs a series of processing
Is.

At the time of repeat measurement, the above series of operations are repeated.

FIG. 2 is a timing display screen according to this embodiment, and FIG. 3 is a block diagram of the counting unit at the time (t). When the repeat measurement execution key is input from the keyboard 20, the repeat measurement setting field 23 is displayed, and the CPU 18 displays the repeat measurement interval setting field 24 for setting the time (t) according to the program of the ROM 19. 25 is timing display data. The time set in the field 24 by key input is read by the CPU 18 and set in the timer 29.

In FIG. 3, reference numeral 26 denotes a time setting signal, and the CPU 18 sends a display end signal 27 to the timer 29 when the measurement ends and the display of the measurement data ends. The timer 29 starts counting when receiving the display end signal 27 from the CPU 18. When the timer 29 finishes counting the preset time, it sends a count end signal 28 to the CPU 18. The CPU 18 receives the counting end signal 28 from the timer 29 and outputs the next measurement start command.

Thus, according to the above embodiment, by setting the time in the repeat measurement interval setting field 24 by the keyboard 20, it is possible to change the repeat measurement interval, recognition display data of the display data at the time of repeat measurement The repeat measurement stop operation can be performed accurately and easily when a specific state is reached.

In the above embodiment, the time (t) is set by a numerical value and a unit, but it may be a relative time as shown in FIG. 4, and the length of the bar display 30 is the above time. (T)
Corresponding to.

Effect of the Invention Since the present invention has the above-mentioned configuration, the time is set from the end of each measurement to the start of the next measurement at the time of repeat measurement, data observation at the time of repeat measurement, and repeat measurement in a specific state. Accurate and easy stop operation.
And because the setting change of the above time can be performed while performing data observation by repeat measurement,
The effect is that the optimum time can be set according to the observation state.

[Brief description of drawings]

FIG. 1 is a block diagram of a logic analyzer showing an embodiment of the present invention, FIG. 2 is a timing display diagram by the logic analyzer, FIG. 3 is a time counting block block diagram, and FIG. 4 is another diagram by the logic analyzer. It is a timing display figure. 23 …… Repeat measurement setting field 24 …… Repeat measurement interval setting field 25 …… Timing display data

Claims (1)

[Claims] 1. A measuring means for repeatedly executing a series of measurements such as sampling of an input digital signal, detection of a trigger event, storage of sampled data, display of stored data, and measurement during the repeated measurement. Means for setting the time from the end to the start of the next measurement, and means for counting the set time, set or change the repeated measurement interval time in repeated measurement, observation of display data, and a specific display state The logic analyzer is characterized in that the repeated measurement stop operation is performed when it is reached.