JP2776885B2 - Semiconductor integrated circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, for example, a technique particularly effective when used for a bipolar CMOS (hereinafter abbreviated as BiCMOS) gate array. It is.

[Conventional technology]

A Bi / CMOS composite logic gate circuit in which a pair of output bipolar transistors in a totem pole form and a CMOS (complementary MOS) logic gate circuit are combined has a relatively large driving capability and low power consumption.

Therefore, Bi.CMOS logic gates have been applied to various semiconductor devices, for example, gate array devices and microcomputers of memory devices.

Meanwhile, Japanese Patent Application Publication No. 59-139724 discloses a gate array using a Bi-CMOS logic gate.

Regarding a basic cell used in a Bi.CMOS gate array device, Japanese Patent Publication No. 61-171150,
Japanese Patent Publication No. 59-193627, Bernard C.
Electronics (Bernard C. Cole)
Fovary, 4,1988 (Electronics / February 4,1988) .p
“AMCC's BiCMOS ARRAY HITS RECODE GATE UTILIZATIO” published on p65-66
N), and Nakasiba et al.
39NO.10 / 1986pp138-143 "Low power, high speed Bi
・ CMOS gate array (Low Power High Speed BiCMOS Ga
te-Array) ".

Note that a gate array can realize a multi-type semiconductor integrated circuit device by performing only a wiring process for each type on a large number of master wafers made in advance. Called. This method has advantages such as cost reduction by mass production of master wafers, automatic design of wiring, and shortening of development period by a manufacturing process in which only wiring is short.

[Problems to be solved by the invention]

The conventional Bi-CMOS gate array as described above has the following problems.

That is, as shown in FIG. 7, when a relatively large load capacitance CL is coupled to the output terminal of the Bi-CMOS logic gate circuit, its transmission delay time tpd is smaller than that of the CMOS logic gate circuit. Becomes smaller. However, when a relatively small load capacitance CL is coupled, the transmission delay time tpd becomes longer as compared with the CMOS logic gate circuit.

On the other hand, the transmission delay circuit tpd of the Bi-CMOS logic gate circuit
Has a similar load dependency according to its driving capability, that is, the emitter size ES of the output transistor, as shown in FIG. That is, when the emitter size ES of the output transistor is increased and its driving capability is increased, the transmission delay time tpd becomes smaller as compared with the case where the emitter size ES is reduced in a region where the load capacitance CL is large. Conversely, the load capacitance CL increases in a small area.

In other words, the logic circuit responds to the load capacitance CL coupled to the output terminal of each logic gate circuit, that is, the fanout,
By selectively combining a CMOS logic gate circuit or a Bi-CMOS logic gate circuit and optimizing the driving capability of each logic gate circuit, its transmission delay time tpd
Is minimized.

However, the basic cell of a conventional BiCMOS gate array is
It does not include a bipolar transistor for substantially increasing the emitter size ES of the output transistor of the Bi-CMOS logic gate circuit and increasing its driving capability. Further, the layout arrangement of each basic cell has not been devised so that the emitter size of the output bipolar transistor can be substantially increased. For this reason, it is difficult to optimize the driving capability of each logic gate circuit according to the load capacitance, so that the total transmission delay time tpd of the logic circuit constituted by the gate array is
It cannot be reduced as desired, and as a result, it has been found that the high-speed operation of the logic circuit is hindered.

An object of the present invention is to provide a CM according to a required driving capability.
An object of the present invention is to provide a basic cell of a gate array and a layout method thereof that can efficiently configure an OS logic gate circuit and a Bi / CMOS composite logic gate circuit.

Another object of the present invention is to achieve high integration of a gate array and increase the speed of a logic circuit constituted by the gate array.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for solving the problem]

The outline of a typical invention disclosed in the present application will be briefly described as follows. That is,
The gate array includes, at a predetermined ratio, a first cell used basically for forming a CMOS logic gate circuit and a second cell basically used for forming a Bi-CMOS logic gate circuit. Further, it includes a pair of bipolar transistors selectively used when a large driving capability is required for the Bi-CMOS logic gate circuit, and is constituted by a plurality of basic cells arranged in a lattice.

That is, a representative embodiment of the present invention is a multi-logic gate circuit (N1, NAG1, N2, BNA1, BNO1, N3, NO
G1, NAG2) (see FIG. 3), wherein, among the plurality of logic circuits, a logic gate circuit (N1, NAG1, N2, N3, NOG1, NAG2), the load is constituted by a CMOS gate circuit (see FIGS. 4 and 5) driven by a P-channel MOSFET and an N-channel MOSFET, and a logic gate circuit (BNA1, BNO
For 1), the input section is a P-channel MOSFET and an N-channel M
The output section includes a Bi-CMOS gate circuit (No. 6) including a bipolar transistor for driving the load.
(See FIG. 6A and FIG. 6B). Among the Bi-CMOS gate circuits, a logic gate circuit whose output load capacitance is equal to or less than a predetermined value (Cc) is effectively an emitter. A Bi-CMOS gate circuit (Bi-CMOS (ES:
1) For a logic gate circuit configured by Bi-CMOS (ES: 2) and having an output load capacitance larger than the predetermined value (Cc), a bipolar transistor having a large emitter size is effectively included in the output section. (Bi-CMOS (ES: 4)) (see FIG. 7).

Further, a specific embodiment of the present invention is characterized in that the bipolar transistor having an effective large emitter size of the Bi-CMOS gate circuit is realized by a parallel connection of a collector-emitter path of a plurality of transistors. (See FIG. 6 (b)).

Further, in a more specific embodiment of the present invention, the parallel connection mode of the plurality of bipolar transistors includes a bipolar transistor and a Bi-CMOS gate circuit inside a first basic cell capable of forming a Bi-CMOS gate circuit. It is realized by connecting a configurable second basic cell in parallel with an unused bipolar transistor inside the cell (see FIG. 13 (a)).

Further, in a more specific embodiment of the present invention, the first basic cell and the second basic cell are each formed as a square, and the first basic cell (BC1) and the second basic cell ( BC2) and a bipolar transistor (B1, B2) inside the first basic cell with respect to one side (X) of the first basic cell (BC1) in the close arrangement. The bipolar transistors (B3, B4) inside the second basic cell (BC2) refer to the first basic cell (B2).
C1) is arranged at a mirror-symmetric position close to the one side (X) (see FIG. 10).

A more specific embodiment of the present invention is characterized in that the bipolar transistor is a totem pole transistor (T1, T2) at the output of a Bi-CMOS gate circuit (see FIG. 6 (a)). .

(Operation)

According to the above means, the first cell included in the basic cell is
By optimizing the ratio of the second cell and the ratio of the second cell, a CMOS logic gate circuit and a Bi-CMOS logic gate circuit optimized according to the required driving capability can be efficiently configured without waste. Thereby, the use efficiency of the gate included in the gate array is improved. Since the gate use efficiency is improved, the number of circuit elements in the gate array can be reduced, and the gate array can be highly integrated.

Further, the logic circuit formed in the gate array includes a CMOS circuit, a first Bi-CMOS circuit including an output bipolar transistor having an emitter size of, for example, 3 μm ^2, and a first Bi-CMOS circuit according to the output load capacitance value. Including an output bipolar transistor having an emitter size larger than the emitter size of the output bipolar transistor of
It is selected from 2Bi CMOS circuits. That is, the logic circuit has a circuit form capable of charging and discharging the output load capacitance at the fastest. As a result, the operating speed of the logic circuit formed in the gate array is increased by employing the above-described design technique.

〔Example〕

FIG. 2 is a layout diagram of a gate array to which the present invention is applied. FIG. 1 shows a layout diagram of an embodiment of the basic cell BC of the gate array shown in FIG. In the present application, a basic cell is defined as a basic unit on a layout including a plurality of semiconductor elements. The basic cells BC constituting the gate array of FIG. 2 and the circuit elements of FIG.
Although not particularly limited, it is formed over one semiconductor substrate such as single crystal silicon.

In FIG. 2, although not particularly limited, the gate array is a signal input / output terminal arranged on the periphery of a square semiconductor substrate SUB. A plurality of external connection terminals pad, an internal logic circuit regularly arranged at the center of the semiconductor substrate SUB, including a plurality of basic cells BC, and an internal logic circuit disposed between the internal logic circuit and the external terminal pad; And an input / output buffer circuit I / O. FIG. 2 exemplarily shows a wiring channelless type gate array. The basic cells BC included in the gate array are not particularly limited, but all have the same configuration. For example, as shown in FIG.
It includes PMOS regions PM1 to PM3, five NMOS regions NM1 to NM5, and four bipolar transistor regions BT1 to BT4. Of these, the PMOS regions PM1 to PM3 include three P-channel MOSFETs each having a relatively large conductance.
The NMOS regions NM1 to NM3 include three N-channel MOSFETs each having a relatively large conductance, respectively.
The NMOS region NM4 includes three N-channel MOSFETs having relatively small conductance. Furthermore, the NMOS region NM
5 includes one N-channel MOSFET which is made relatively small in conductance. The bipolar transistor regions BT1 to BT4 have a predetermined emitter size, for example, 1 ×
One bipolar transistor of 3 μm ² is included.

In each basic cell BC, each of the Ps constituting the PMOS region PM1
A gate G made of polysilicon is formed between the source S and the drain D of the channel MOSFET. These gates G are connected to the NMOS regions NM1
Extending between the source and the drain of the corresponding N-channel MOSFET. As a result, each P-channel MOSFET in the PMOS region PM1 and a corresponding N-channel MOSFET in the NMOS region NM1 are
The gates of T are commonly coupled. Three P-channel MOSFETs provided in the PMOS region PM1 and the NMOS region NM1
The N-channel MOSFET and the N-channel MOSFET are regarded as the first cell of the basic cell BC, and a three-input CMOS logic gate circuit composed of three sets of CMOS or a corresponding two-input CMOS logic gate circuit and a CMOS inverter circuit (in other words, , One input
CMOS logic gate circuit).

Similarly, the gate G of each P-channel MOSFET in the PMOS region PM2 is commonly coupled to the gate G of the corresponding N-channel MOSFET in the NMOS region NM2. These PMOS regions
Three P-channel MOs provided in PM2 and NMOS area NM2
The SFET and N-channel MOSFET are also
Can be used to form a three-input logic gate circuit composed of three sets of CMOS or a corresponding two-input logic gate circuit and a CMOS inverter circuit.

On the other hand, the gates G of the P-channel MOSFETs in the PMOS region PM3 are commonly coupled to the gates G of the corresponding N-channel MOSFETs in the NMOS region NM4, respectively, and further commonly coupled to the gates G of the corresponding N-channel MOSFETs in the NMOS region NM3. Is done. Three P-channel MOSFETs provided in the PMOS region PM3 and six N-channel MOSFETs provided in the NMOS regions NM3 and NM4
The channel MOSFET includes one N-channel MOSFET provided in the NMOS region NM5 and a bipolar transistor region BT.
Along with the four bipolar transistors provided in 1 to BT4, this is regarded as the second cell of the basic cell BC, and is a 2-input or 3-input Bi-CMOS logic gate circuit or Bi-CM.
It can be used to construct an OS inverter circuit (in other words, a one-input Bi-CMOS composite logic gate circuit).

In the PMOS regions PM1 to PM3, each P channel MO
The SFET is formed by introducing 1 boron into a semiconductor substrate using each gate as an impurity introduction mask. In the NMOS regions NM1 to NM5, each N-channel MOSFET
Each gate is formed by introducing phosphorus or arsenic into a semiconductor substrate using an impurity introduction mask.

In the gate array of this embodiment, the Bi-CMOS logic gate circuit can selectively have two-stage driving capability, although not particularly limited. That is, when a relatively small driving capability is required for the Bi-CMOS logic gate circuit,
2 formed in the bipolar transistor regions BT1 and BT2
The bipolar transistors are output transistors. On the other hand, when relatively large driving capability is required for the Bi-CMOS logic gate circuit, the bipolar transistor region BT
A pair of bipolar transistors formed in 3 and BT4 are respectively connected in parallel to the output stage bipolar transistors formed of the bipolar transistors formed in regions BT1 and BT2. FIG. 8 schematically shows circuit elements included in the basic cell BC of FIG.

FIG. 3 partially shows a circuit diagram of an example of a logic circuit constituted by the gate array of FIG. FIGS. 4 to 6 (a) and (b) show the CMOS inverter circuit N1, the CMOS NAND gate circuit NAG1 and the Bi / CMOS NAND gate circuits BNA1 and Bi included in the logic circuit of FIG.
The circuit diagrams of the CMOS NOR gate circuit BNO1 are shown respectively. In these figures, the channel (back gate)
The MOSFETs to which arrows are added are P-channel MOSFETs, and are distinguished from N-channel MOSFETs to which no arrows are added. The illustrated bipolar transistors are all NPN transistors. In FIG. 3,
The specific operation conditions of the logic circuit and the logic conditions of each input signal and output signal are not directly related to the present invention.
A detailed description is omitted.

In FIG. 3, an input signal A supplied from a logic circuit (not shown) of the logic circuit is supplied to a first input terminal of a CMOS NAND gate circuit NAG1 after being inverted by a CMOS inverter circuit N1. Input signals B and C are supplied to the second and third input terminals of the CMOS NAND gate circuit NAG1, respectively, from a circuit (not shown) of a logic circuit. After the output signal of the CMOS NAND gate circuit NAG1 is inverted by the CMOS inverter circuit N2,
It is supplied to the first input terminal of the CMOS NAND gate circuit BNA1. The second and third of this Bi-CMOS NAND gate circuit BNA1
Are supplied with an input signal D and an input signal E from a circuit (not shown) of a logic circuit. The output signal F of the Bi-CMOS NAND gate circuit BNA1 is supplied to the first input terminal of the Bi-CMOS NOR gate circuit BNO1 and to another circuit of the logic circuit. The output signal F of the Bi-CMOS NAND gate circuit BNA1 is supplied to the input terminals of a total of three logic gate circuits, and the fan-outs fo are three. Note that the fan-out is defined as the number of inputs to the next-stage circuit that is coupled to the output terminal of one circuit and is driven by that circuit.

Here, as shown in FIG. 4, the CMOS inverter circuit N1 includes a P-channel MOSFET Q1 and an N-channel MOSFET Q11 whose source and drain paths are provided in series between the power supply voltage V _CC and the ground potential GND of the circuit. . The gates of these MOSFETs Q1 and Q11 are commonly coupled and used as the input terminal i of the CMOS inverter circuit N1. In addition, the above MOSFET
The commonly coupled drain of Q1 and Q11 is used as the output terminal o of the CMOS inverter circuit N1. As a result, the output signal o of the CMOS inverter circuit N1 is at a low level such as the ground potential of the circuit when the input signal i is at a high level, and when the input signal i is at a low level, the power supply voltage V _CC of the circuit is reduced. High level like this.

The CMOS inverter circuit N2 is a CMOS inverter circuit N1.
And the same circuit configuration.

In this embodiment, the MO of the CMOS inverter circuit N1 is
Although not particularly limited, the SFET Q1 is configured by a first P-channel MOSFET provided in the PMOS region PM1 of the basic cell BC1, and the MOSFET Q11 is configured by a first N-channel MOSFET provided in the NMOS region NM1. Similarly, the MOSFET Q1 of the CMOS inverter circuit N2 is, although not particularly limited, constituted by a second or third P-channel MOSFET provided in the PMOS region PM1 of the basic cell BC, and the MOSFET Q11 is provided in the NMOS region NM1. It is constituted by a second or third N-channel MOSFET, respectively.

Next, as shown in FIG. 5, the CMOS NAND gate circuit NAG1 includes a P-channel MOSFET Q2 and N-channel MOSFETs Q12 to Q14 whose source / drain paths are provided in series between the power supply voltage V _CC and the ground potential GND of the circuit. Including. MO
In the source / drain path of SFETQ2, additional P channel
The source and drain paths of MOSFETs Q3 and Q4 are provided in parallel. The gate of the MOSFET Q2 is commonly coupled to the gate of the MOSFET Q12, and serves as a first input terminal i1 of the CMOS NAND gate circuit NAG1. Similarly, the gates of the MOSFETs Q3 and Q4 are commonly coupled to the gates of the MOSFETs Q13 and Q14, respectively, and serve as the second and third input terminals i2 and i3 of the CMOS NAND gate circuit NAG1, respectively. As a result, the output signal o of the CMOS NAND gate circuit NAG1 is set to a low level such as the ground potential GND of the circuit when all of the input signals i1 to i3 are set to the high level, and any of the input signals i1 to i3 is set to the low level. At the same time as the power supply voltage V _CC of the circuit.

In this embodiment, the P of the CMOS NAND gate circuit NAG1 is
Although there is no particular limitation on the channel MOSFETs Q2 to Q4, the first to third P MOSFETs provided in the PMOS region PM2 of the basic cell BC1 are provided.
It is composed of a channel MOSFET. Further, the N-channel MOSFETs Q12 to Q14 are configured by first to third N-channel MOSFETs provided in the NMOS region NM2 of the basic cell BC1.

Bi · CMOS NAND gate circuit BNA1, as shown in FIG. 6 (a), the output bipolar transistor of the totem-pole form the collector-emitter paths connected in series between the power supply voltage V _CC of the circuit and the ground potential GND Includes T1 and T2. The common-coupled node of the emitter of the output transistor T1 and the collector of the output transistor T2 is a BiCMOS
This is the output terminal o of the NAND gate circuit BNA1. Between the base of the output transistor T1 and the power supply voltage V _{CC of the} circuit,
Three P-channel MOSFETs Q5 to Q7 whose source drain paths are arranged in parallel are provided. Further, between the base of the output transistor T1 and the ground potential GND of the circuit, three N-channel MOSFETs Q15 to Q17 whose source / drain paths are in series are provided. These MOSFETs Q5
-Q7 and Q15-Q17 are the same 3-input CMOS as in FIG.
Configure a NAND gate circuit. Meanwhile, the output transistor
Three N-channel MOSFETs whose source / drain paths are connected in series between the base of T2 and the output terminal o.
Q18 to Q20 are provided. Further, an N-channel MOSFET Q21 whose gate is commonly coupled to the output terminal o is provided between the base of the output transistor T2 and the ground potential GND of the circuit. The gates of MOSFETs Q18 to Q20 are
The gates of the SFETs Q15 to Q17 are commonly coupled to the first to third input terminals i1 to i3 of the Bi-CMOS NAND gate circuit BNA1, respectively. Thus, the output signal o of the Bi-CMOS NAND gate circuit BNA1 when the input signal i1~i3 are both high level, the base-emitter voltage of only low high level of the output transistor T1 than the power supply voltage V _CC of the circuit When any of the input signals i1 to i3 is at a low level, the output transistor T2 is higher than the ground potential of the circuit.
Is set to a low level that is higher by the base-emitter voltage.

In this embodiment, a Bi-CMOS NAND gate circuit BNA1
Although the output transistors T1 and T2 are not particularly limited,
The bipolar transistor region BT1 of the basic cell BC1 and
Each is constituted by a bipolar transistor provided in BT2. Further, the P-channel MOSFETs Q5 to Q7 and the N-channel MOSFETs Q15 to Q17 are respectively constituted by first to third P-channel MOSFETs and N-channel MOSFETs provided in the PMOS region PM3 and the NMOS region NM3 of the basic cell BC1. Further, the N-channel MOSFETs Q18 to Q20 are
The first to third N provided in the NMOS region NM4 of the basic cell BC1
Each N-channel MOSFET Q21 is constituted by one N-channel MOSFET provided in its NMOS region NM5.

By the way, in the embodiment of FIG. 3, since the fan-out fo of the Bi-CMOS NAND gate circuit BNA1 is set to 3,
The output stage of the CMOS NAND gate circuit BNA1 is composed of a pair of transistors T1 and T2, respectively. When a relatively large driving capability is required for the Bi-CMOS NAND gate circuit BNA1, that is, when the fan-out fo is, for example, 7 or more, as shown by a dotted line in FIG. The output transistor T3 is connected to T1 and T2.
And T4 are each provided in a parallel configuration. Although not particularly limited, these output transistors T3 and T4 are respectively constituted by a pair of bipolar transistors provided in the bipolar transistor regions BT3 and BT4 of the basic cell BC1.

In FIG. 3, the second circuit of the Bi-CMOS NOR gate circuit BNO1 is shown.
The third input terminal is supplied with an input signal G and an inverted signal of the input signal H by a CMOS inverter circuit N3 from a circuit (not shown) of a logic circuit. The output signal K of the Bi-CMOS NOR gate circuit BNO1 is the CMOS NAND gate circuit NAG2
, And to a logic circuit (not shown) of the logic circuit. Bi-CMOS NOR gate circuit
The output signal K of BNO1 is supplied to the input terminals of a total of eight logic gate circuits, and the fan-outs fo are eight.
The second input terminal of the CMOS NAND gate circuit NAG2 includes:
An input signal I is supplied from a circuit (not shown) of a logic circuit, and a third input terminal thereof is connected to a CMOS NOR gate circuit NOG1.
Are supplied. This CMOS NOR gate circuit NOG1
The first input terminal is supplied with an output signal of the CMOS inverter circuit N3, and the second input terminal thereof is supplied with an input signal J from a logic circuit (not shown).

Here, the CMOS inverter circuit N3 has the same circuit configuration as the above-described CMOS inverter circuits N1 to N2, and is not particularly limited, but is not limited to the first P1 provided in the PMOS region PM1 of the basic cell BC2.
It comprises a channel MOSFET and a first N-channel MOSFET provided in the NMOS region NM1. at the same time,
The CMOS NAND gate circuit NAG2 is based on the NAND gate circuit NA.
The circuit configuration is the same as that of G1, and although not particularly limited, three P-channel MOs provided in the PMOS region PM2 of the basic cell BC2
It is composed of an SFET and three N-channel MOSFETs provided in its NMOS region NM2.

Then, CMOS NOR gate NOG1, as can be inferred from the NAND gate circuit NAG1 and NAG2, provided in series between the power supply voltage V _CC and the ground potential of the circuit, two P-channel MOSFET is in series form And two N-channel MOSFETs arranged in parallel. In this embodiment, the two P-channel MOSFETs that constitute the CMOS NOR gate circuit NOG1 are not particularly limited, but the basic cell BC2
And the second and third N-channel MOSFETs provided in the NMOS region NM1.

Bi · CMOS NOR gate BNO1, as shown in FIG. 6 (b), 2 pieces of output transistor provided in totem pole form between the power supply voltage V _CC and the ground potential of the circuit
Let T1 and T2 be the basic configuration. In the preceding stage of the output transistor T1, three P-channel MOSFETs Q22 to Q24 and three N-channel MOSFETs Q2 constituting a CMOS NOR gate circuit are provided.
5 to Q27 are provided, and between the collector and base of the output transistor T2, three N-channel MOSFETs Q28 to Q30 whose source / drain paths are arranged in parallel are provided. One N-channel MOSFET whose gate is coupled to the collector of the output transistor T2 is provided between the base of the output transistor T2 and the ground potential GND of the circuit.
Q31 is provided. These transistors T1 and T2 and each of the MOSFETs Q22 to Q31 are connected to the PMOS region PM3 of the basic cell BC2.
It is constituted by respective circuit elements provided in the NMOS regions NM3 to NM5 and the bipolar transistor regions BT1 and BT2. In the embodiment shown in FIG. 3, since the fan-out fo of the Bi-CMOS NOR gate circuit BNO1 is 8, a pair of output transistors T3 and T4 are connected to the output transistors T1 and T2.
Are provided in parallel form. Needless to say, these transistors T3 and T4 are constituted by a pair of bipolar transistors provided in the bipolar transistor regions BT3 and BT4 of the basic cell BC2. Fig. 9
The logic circuit of FIG. 3 is replaced with the basic cell BC shown in FIG.
This figure shows a connection state in the case of using a plurality of components. The power supply wirings V _CC and GND shown in the figure can be formed by a first-layer aluminum wiring. The connection between circuit elements is
It can be formed using a first layer aluminum wiring, a second layer aluminum wiring, or the like.

In the above, the bipolar transistors T1 and T3 (T2 and T3
4), the example in which each is formed individually and connected in parallel has been described, but can be changed as shown in FIG. 6 (c). That is, two emitters E1 and E2 may be provided and connected to one bipolar transistor BiP.

FIG. 6 (a) shows an example of a layout diagram of the bipolar transistor BiP of FIG. 6 (c). As can be seen from the figure, the bipolar transistor BiP has a P-type base region B formed in an N-type collector region C and two N ⁺ -type emitter regions E1, E2 formed separately in the base region B. Can be formed.

As described above, the gate array of this embodiment includes a plurality of basic cells BC arranged in a lattice. These basic cells BC are composed of two sets of three-input CMOS logic gate circuits or equivalent two-input CMOS logic gate circuits or CMOS inverter circuits (in other words, one-input CMOS logic gate circuits). A first cell and a set of second cells that can constitute a two-input or three-input Bi-CMOS logic gate circuit or a Bi-CMOS inverter circuit (in other words, a one-input Bi-CMOS composite logic gate circuit) Include each. Further, the Bi-CMOS logic gate circuit includes a pair of bipolar transistors which are selectively used when relatively large driving capability is required.

As shown in FIG. 7, the transmission delay time tpd of the CMOS logic gate circuit has a small fan-out fo and a small load capacity.
When CL is made relatively small, it is made smaller as compared with the Bi-CMOS logic gate circuit, and when its load capacitance CL is made relatively large, conversely, it is made larger as compared with the Bi-CMOS logic gate circuit. On the other hand, the transmission delay time tpd of the Bi-CMOS logic gate circuit depends on the emitter size ES of the output transistor.
Exhibit a similar load dependency as is reduced.
For this reason, in the logic circuit of FIG.
N3 and NAND gate circuits NAG1 to NAG2 and nonagate circuit NO
A logic gate circuit such as G1 which requires only one or two fan-outs whose load capacitance CL is smaller than Ca, for example, is constituted by the first cell of each basic cell BC, A logic gate circuit such as the NAND gate circuit BNA1 and the NOR gate circuit BNO1 which requires a relatively large number of fanouts whose load capacitance CL exceeds, for example, Cb is constituted by the second cell of each basic cell BC. You. Further, for a Bi / CMOS composite logic gate circuit such as the NOR gate circuit BNO1 which requires eight fan-outs whose load capacitance CL exceeds Cc, the output transistors in the totem pole form are each in a parallel form. , And the driving capability is enhanced by increasing the emitter size ES.

That is, the transmission delay time tpd (M
OS) is expressed as shown below.

_{tpd (MOS) = t 0 +} V LT · C L / I D ...... (1) V LT: logical threshold I _D: MOS drain current t _0: the delay time independent of the load capacitance C _L, X / Including _ID functions. X indicates a positive real number.

Average propagation delay time tpd (BiC
MOS) [= (t _PHL + t _PLH ) / 2] is expressed as in the following equation.

_{tpd (BiCMOS) = t 1 +} V LT · C L / (nβ · I D) ...... (2) V LT: logical threshold I _D: MOS drain current beta: grounded emitter current amplification factor of the bipolar transistor t ₁ : the delay time independent of the load capacitance _{C L Y (n) / 2I} D
It is expressed by the sum of Z (n) / n · β · _ID .

n: Emitter area, for example, emitter area ratio when 1 × 3 μm ^{2 is set} to 1. Incidentally, Y (n) and Z (n) are expressed by the following equations.

_{Y (n) = V BE (} 2nC CB + 2nC BE + C NS + C PD) + V LT (4nC CB + 2C PD) Z (n) = V LT (nC sub + C ND) V BE: base-emitter of the bipolar transistor Voltage, C _CB : Collector-base capacitance of bipolar transistor, C _BE : Collector-base capacitance of bipolar transistor, C _sub : Collector-substrate capacitance of bipolar transistor, C _PD : Drain capacitance of PMOSFET, C _ND: drain capacitance of NMOSFET, C _NS: source capacitance of the NMOSFET, these capacitance C _CB -C _NS corresponds to the parasitic capacitance C _CB1 -C _NS shown in FIG. 12 to be described later. In the above,
The capacity C _CB corresponds to C _CB = C _CB1 = C _CB2 , and the capacity C _BE corresponds to C _BE = C _BE1 = C _BE2 .

The condition is that the ambient temperature is Ta = 25 ° C. and the power supply V _{CC is} 5V. The MOSFET is formed by, for example, a 1.3 μm process and has a gate length of 1.2 μm and a gate width of 30 μm.
m. On the other hand, the bipolar transistor has an emitter area of 1 × 3 μm ³ , a shut-off frequency of 7 GHz, and a grounded emitter current amplification factor of 100.

As can be understood from the above equation (1), transmission delay time of the CMOS circuit tpd (MOS), that the drain current I _D, the conductance gm increases its inclination _{(V LT · C L / I} D) decreases. On the other hand, as can be understood from equation (2), Bi · CMOS
Transmission delay time of the circuit tpd (Bi · CMOS), when the emitter area ratio n of the bipolar transistor increases, the inclination _{(V LT · C L / n} · β · I D) decreases. By the way, n =
In the case of 2 (Bi.CMOS (ES: 2)), the inclination is 1/2 of that in the case of n = 1, and in the case of n = 4 (Bi.CMOS (ES: 4))
Is assumed to be 1/4 that of n = 1.

Furthermore, in the equation (1), the load capacitance C _{L-independent} delay time t ₀ is reduced by an increase in the drain current I _D. In equation (2), the delay time t ₁ independent of the load capacitance C _L increases as the emitter area ratio n increases, as shown in FIG.

Therefore, in the gate array according to the present invention, the type of logic circuit used depends on the device parameters of the P-channel and N-channel MOSFETs built in the gate array and the device parameters of the bipolar transistor. circuit,
Emitter area ratio is the 1Bi · CMOS circuit and the emitter area ratio of 1 is determined by one or more graphs of the transmission delay time tpd versus load capacitance C _L of the 2Bi · CMOS circuit. In other words, the load capacitance C _L charging fastest to and Naruden possible types of logic circuits of the logic circuit of each, CMOS circuits, among the first 1Bi · CMOS circuit and the 2Bi · CMOS circuit, transmission delay time versus load Capacity C _L
Referring to the graph of FIG.

In the actual design of the gate array, a CMOS circuit that implements a corresponding logic circuit for each logic circuit such as an inverter circuit, a two-input NOR circuit, a two-input NAND circuit, a three-input NOR circuit, and a three-input NAND circuit, includes relationship CMOS circuit and the 2Bi · CMOS circuit transmission delay time of tpd versus load capacitance C _L is obtained. Then, from the value of the relationship and the calculated load capacitance C _L of the transmission delay time tpd versus load capacitance C _L of the corresponding logic circuit and with the value of the load capacitance C _L of the logic circuit is noted is calculated, The optimal circuit configuration is selected.

As a result, in the gate array of this embodiment, the circuit element of each basic cell BC is used without waste, the element use efficiency is increased, and as a result, high integration is achieved. In addition, the CMOS logic gate circuit or the Bi-CMOS logic gate circuit is efficiently selected according to the driving capacity required for each logic gate circuit, and the driving capacity of the Bi-CMOS logic gate circuit is switched in steps. Thus, the transmission delay time tpd is optimized. As a result, the operation of a logic circuit or the like constituted by the gate array is speeded up.

As shown in the present embodiment, by applying the present invention to a gate array, the following effects can be obtained.
That is, (1) The basic cell of the gate array is basically a first cell used for forming a CMOS logic gate circuit and a second cell basically used for forming a Bi-CMOS logic gate circuit. It includes cells in a predetermined ratio and includes a pair of bipolar transistors that are selectively used when relatively large driving capability is required for the Bi-CMOS logic gate circuit. As a result, there is an effect that the CMOS logic gate circuit and the Bi-CMOS logic gate circuit can be efficiently configured without waste according to the driving capability required for each logic gate circuit.

(2) In the above item (1), the bipolar transistor is connected in parallel to the output transistor thereof in accordance with the driving capability required for the Bi-CMOS logic gate circuit, whereby the configuration of the Bi-CMOS composite logic gate circuit is achieved. In addition, the effect that the driving capability can be optimized can be obtained.

(3) According to the above items (1) and (2), the effect is obtained that the number of circuit elements in the gate array can be substantially reduced and the degree of integration can be increased.

(4) According to the above items (1) and (2), an effect is obtained that the transmission delay time of a logic circuit or the like constituted by the gate array can be reduced and the operation thereof can be speeded up.

In the above embodiment, one basic cell BC including four bipolar transistors BT1 to BT4 has been mainly described. However, the present invention is not limited to this, and the layout of one basic cell including two bipolar transistors BT1 to BT4 is not limited thereto. By devising the above, the same effect can be achieved. It should be noted that reference numerals in the drawings described below are:
It should be understood that some of the reference numbers in FIGS. 1 to 9 overlap, but are different.

FIG. 10 shows another embodiment of the present invention, and shows an optimum layout diagram of four basic cells BC1 to BC4 each including two bipolar transistors. Before describing the layout features of the basic cells BC1 to BC4 shown in FIG. 10, the features of the basic cell BC1 shown in FIG. 10 will be described first.

The basic cell BC1 includes two bipolar transistors B1 and B2, a P-channel MOSFET region P1 and an N-channel MOSFET disposed between the bipolar transistors B1 and B2.
It includes a region N1, P-channel MOSFET regions P2 and P3, and N-channel MOSFET regions N2 to N6. In the region P1, a gate electrode G made of two polysilicons is formed, and the gate electrode G extends over the region N1. As a result, two PMOSFETs are provided in the region P1, and two NMOs are provided in the region N1.
An SFET is formed. Further, a gate electrode made of three polysilicons is formed in each of the regions P2 and P3, and the gate electrodes are formed in the regions N2 and N4 and the regions N3 and N3.
Extended over N5. As a result, three PMOSFETs are formed in the regions P2 and P3, respectively, and three NMOSFETs are formed in the regions N2, N3, N4, and N5. Further, a gate electrode G made of one polysilicon is formed in the region N6, and one NM is formed.
An OSFET is formed. FIG. 11 shows an equivalent diagram of the basic cell BC1.

The MOSFETs formed in the regions P1 and N1 have a gate length of 1.2 μm and a gate width of 15 μm, respectively, and the regions P2, P3, N2 and N3
Each of the MOSFETs has a gate length of 1.2 μm and a gate width of 30 μm. Therefore, the driving capabilities of the P and N channel MOSFETs in the regions P1 and N1 are equal to those of the regions P2 and N2 or
And the drive capability of the P and N channel MOSFETs of N3 and N3. For example, the MOSFs indicated by Q100 to Q105 in FIG.
Let us consider a case where a circuit as shown in FIG. 12 is formed using bipolar transistors represented by ET and B1 and B2. CMOS inverter INV is a PMO with reduced gate width
It is constituted by an SFET Q100 and an NMOSFET Q101. on the other hand,
The input of the bipolar CMOS inverter circuit BINV is driven by the output of the CMOS inverter INV. This bipolar CMOS inverter BINV is a totem-pole type bipolar output transistor B1 and B2, and a PMOSFET Q10 for driving the base of the bipolar transistor B1.
2 and NMOSFET Q103, a CMOS inverter, and NMOSFET Q10 driving the base of bipolar transistor B2
4 and Q105 included.

PMOSFET whose source / drain bus is connected between the power supply terminal V _CC and the base of the bipolar transistor B1
Uses a PMOSFET Q102 having a wide gate width. This PMO
Since the driving capability of the SFET Q102 is high, the capacitance parasitic on the base electrode of the bipolar transistor B1, the capacitance C _CB1 between the base and the collector C _BE1 and the capacitance C _BE1 between the base and the emitter of the bipolar transistor B1 and the PMOSFET Q102
The drain capacitance C _PD , charge at high speed. Bipolar C
The output rise delay time t _PLH of the MOS circuit is determined by the common emitter current gain β of the bipolar transistor B1 and the PMOSFET Q10.
2 is inversely proportional to the product of the drain current I _PD and the load capacitance C _L
Term proportional to And a term inversely proportional to the drain current I _PD (A / I _PD , A: positive real number). Therefore, output rise delay time t _PLH
It is by increasing the drain current I _PD of PMOSFETQ102, i.e., by increasing the gate width of PMOSFETQ102, smaller.

On the other hand, an NMOS whose source / drain bus is connected between the output terminal out and the base of the bipolar transistor B2
As the FET, an NMOSFET Q104 having a wide gate width is used. this
Since the NMOSFET Q104 has high driving capability, the parasitic capacitance at the base electrode of the bipolar transistor B2, the base-collector capacitance C _CB2 , the base-emitter capacitance C _BE2 and the NMOSFET
Charge the source capacitance C _{NS of} Q104 at high speed. bipolar·
The output fall delay time t _PHL of the CMOS circuit is (Β: gain of grounded emitter current of bipolar transistor B2, I _ND : drain current of NMOSFET Q104) and B / I
_ND (B: positive real number). Therefore, output fall delay time t _PHL decreases as drain current I _{ND of} NMOSFET Q104 increases, that is, as the gate width of NMOSFET Q104 increases. A and B are the parasitic capacitances C _CB1 , C _BE1 , C _PD , C _NS , C _CB2 , C _BE2 , the logic threshold V _LT , the emitter ground current amplification factor β, and the collector substrate of the bipolar transistor B2. It is expressed as a function of the inter-capacitance C _SUB and the drain capacitance C _ND of the NMOSFET Q104.

On the other hand, the NMOSFET Q103 provided between the base electrode of the bipolar transistor B1 and the ground potential GND and the NMOSFET Q105 provided between the base electrode of the bipolar transistor B2 and the ground potential GND have the parasitic capacitance of each base electrode. Since it is provided to perform discharge,
The gate width may be reduced.

As can be understood from the figure, the output o of the CMOS inverter INV only drives the input of the bipolar CMOS inverter BINV formed in the same basic cell BC1, so that the output load capacitance CL1 is Assuming that the output load capacitance CL2 of the CMOS inverter BINV is a large value, it is regarded as a value smaller than the value of the capacitance CL2. Accordingly, since the load capacitance CL1 of the CMOS inverter INV is low, transmission delay time tpd of the CMOS inverter INV can load capacitance C _L shown in FIG. 7 is considered to be determined by the CMOS characteristics of Ca smaller portion . In other words, since the output load capacitance CL1 of the CMOS inverter INV is reduced, even if the drive capability of the P and N-channel MOSFETs constituting the CMOS inverter INV is reduced, that is, even if the gate width is reduced, The propagation delay time tpd of the CMOS inverter INV is considered to be an acceptably small value. In other words, the above area
CMOS circuit composed of a small MOSFET having a gate formed width P1 and N1 is by performing a circuit designed to be actively applied to a small circuit portion of the output load capacitance C _L,
The transmission delay time characteristic of the CMOS circuit is effectively used.

In this way, by optimally incorporating a plurality of MOSFETs having narrow gate widths inside the basic cell BC1 and specifying the application of the CMOS circuit formed from these MOSFETs, an optimum design for the transmission delay time is performed. Further, by arranging a MOSFET having a narrow gate width in a region between the bipolar transistors B1 and B2 in the basic cell BC1, the area occupied by the basic cell BC1 is effectively used.

Since the basic cell BC1 is formed so as to be suitable for a wiring channelless gate array, as shown in FIG. 11, a wiring area WA indicated by a dotted line is provided in the basic cell BC1. It is preferable that the wiring provided in the basic cell BC1 mainly use the first-layer aluminum wiring (AL1) and / or the polysilicon wiring. Because the tenth
As shown, the power supply voltage line V _CC and the ground potential line GND formed in the first layer aluminum interconnection (AL1) is because is extended above and below the basic cell BC1. further,
When a signal input line to the basic cell BC1 and a signal output line from the basic cell BC1 cross the power supply voltage line V _CC or the ground potential line GND, those input / output lines are formed by the second layer aluminum wiring. You. If the input / output lines do not intersect the V _CC line or the GND line, that is, if they are provided so as to be orthogonal to the polysilicon gate electrode formed in the basic cell BC1, those input / output lines are the first layer of aluminum. It is formed of wiring and / or polysilicon wiring.

Next, the layout of each element in the basic cell B1 will be described with reference to FIG. The bipolar transistors B1 and B2 are arranged above and below the basic cell BC1, so that they can be easily connected to the power supply line _VCC and the ground line GND. As a result, the connection between the collector C of the bipolar transistor B1 and the power supply line _Vcc and the connection between the emitter E of the bipolar transistor B2 and the ground line GND are made over a short distance, so that the collector parasitic of the bipolar transistor B1 due to the connection wiring is formed. The resistance and the parasitic resistance of the emitter of the bipolar transistor B2 are reduced. Similarly, the regions P2 and P3 and the regions N2 and N3 where the MOSFETs having the increased gate width are provided are also arranged near the power supply line _Vcc and the ground line GND. Thereby, when a CMOS circuit is formed using MOSFETs in the regions P2, P3, N2 and N3, the connection between the source region of those MOSFETs and the power supply line _Vcc or the ground line GND can be made over a short distance. Therefore, the source resistance is reduced. Further, the area P2 (P3) and the area N4
The layout of (N5), area N2 (N3) and area N6 is the second
It will be noted that the connections are similar to the connections of transistors Q102-Q105 of the bipolar CMOS inverter BINV shown in the figure. Thereby, bipolar CMOS
CAD (computer aided desig) for configuring logic circuits
The wiring design according to n) is facilitated. Furthermore, the wiring area WA substantially corresponds to the PMOSFET formation areas P1, P2, and P3.
The distance between the NMOSFET formation regions N1 to N6 is increased. Therefore, the latch-up phenomenon can be prevented. Further, a wiring region WA is provided between the bipolar transistor B1 and the regions P1 and P2 and between the bipolar transistor B2 and the regions N1, N2 and N6. Bipolar transistors B1 and B2
Even if minority carriers are injected into the substrate due to the saturation of the substrate, the presence of the wiring region WA reduces the influence on the MOSFET.

The base electrodes B of the respective bipolar transistors B1 and B2 are provided in the direction in which the regions P3 (P2), N6 and N3 (N2) exist so that the connection with the MOSFETs coupled thereto is easy.

Next, the layout of the basic cells BC1 to BC4
This will be described with reference to FIG. That is, the basic cells BC1 and BC2 are mirror-symmetric with respect to the two-dot chain line X in the figure. As a result, the bipolar transistors B1 and B2 in the basic cell BC1 and the bipolar transistors B2 and
B3 and B4 are arranged close to each other. Furthermore, the above basic cell BC
1, BC2 and the basic cells BC3, BC4 are mirror-symmetric with respect to the two-dot chain line Y in the figure. These four basic cells BC1 to BC4 are
It is considered as a unit cell block UCB. The unit cell blocks UCB are regularly laid out in a grid pattern in the internal logic circuit forming region on the semiconductor substrate SUB, and a master chip of the gate array is manufactured. Basic cells BC1 and BC2 and basic cells BC3 and B
By making C4 mirror symmetric with respect to the two-dot chain line Y,
MOSFET to be connected to ground line GND in each basic cell
And the bipolar transistor is a unit cell block UC
They are gathered at the center of B, that is, along the two-dot chain line Y. Therefore, as shown in the figure, when the ground line GND is formed along the line Y, one ground line GND can be commonly used for the two basic cells BC1 and BC3 (BC2 and BC4). The required number of ground lines GND is reduced. The power supply lines V _CC1 and V _CC2 are arranged above and below the unit cell block UCB, respectively, as shown in the figure. Thereby, it is possible to prevent a decrease in the transconductance gm that occurs when the power supply wiring passes over the MOSFET. These power lines V _CC1 and V _CC2 and the ground line G
ND is formed by the first-layer aluminum wiring AL1.

Next, an example of usage of the basic cells BC1 and BC2 shown in FIG. 10 will be described based on FIGS. 13 (a) and 13 (b).

FIG. 13 (a) shows an example in which the circuit of FIG. 13 (b) is realized by using P- and N-channel MOSFETs and bipolar transistors built in the basic cells BC1 and BC2. In the figure, the parts shown by dotted lines indicate aluminum wiring and / or polysilicon wiring. The black circles indicate the connection between the gate and the wiring, and the connection between the source, drain, base, emitter and collector of the MOSFET or bipolar transistor and the wiring (including the _VCC and GND lines). Further, white circles with reference symbols A, B, C, D, E, F, G, and out indicate signal input / output terminals. Note that, in FIG. 13 (b), specific operation conditions of the logic circuit and logic conditions of each input signal and output signal are not directly related to the present invention, and thus detailed description thereof is omitted. Also,
FIG. 13 (a) corresponds to the respective formed portions of the CMOS inverter circuits CIV1, CIV2, CIV3, the CMOS NAND circuit CND, the CMOS NOR circuits CNR1, CNR2 and the BiCMOS NAND circuit BND shown in FIG. 13 (b). The detailed description will not be given because the reference symbols are attached. The features are described below.

As understood from FIG. 13 (a), the input terminals A to F and G are connected to the gate electrodes in the basic cells BC1 and BC2 on the wiring area WA of the basic cells BC1 and BC2 (see FIG. 10). It is to be connected. The output terminal out is taken out from the wiring formed in the wiring area WA.
As a result, the signal delay time due to the input / output wiring resistance can be minimized. The input wiring is not described for the input CD in order to prevent the drawing from becoming complicated.

Furthermore, a CMOS inverter circuit CIV is included in the basic cell BC2.
1 ~ CIV3 and CMOS NAND circuit CND are configured,
The bipolar transistors B3 and B4 in the basic cell BC2 are not used for the CMOS circuits CIV1 to CIV3 and CND formed in the basic cell BC2. However, since the basic cells BC1 and BC2 are mirror-symmetric with respect to the line X as shown in FIG. 10, the bipolar transistors B1 and B3 (B2 and B4) in both the basic cells BC1 and BC2 Are arranged close to each other, and as shown in FIG. 13A, the parallel connection of the bipolar transistors B1 (B2) and B3 (B4) is made possible by a short wiring length. Although FIG. 7A assumes that the number of fanouts of the BiCMOS NAND circuit BND is large, if the number of fanouts is small, the bipolar transistors B1 (B2) and B3
The connection with (B4) may not be connected in parallel.

Therefore, the layout arrangement of basic cells BC1 and BC2 shown in FIG.
A semiconductor element such as an ET bipolar transistor can be used for a part of a circuit configured in another basic cell. In other words, a semiconductor element in one basic cell and a semiconductor element in another basic cell can form one logic circuit. Thereby, the semiconductor elements in the basic cell can be effectively used. In the above description, the bipolar transistors B1 to B4 have been described, but the regions P1, N1, P1 ^▲ , N1
^The same applies to the MOSFET formed in the triangle. One example is shown in FIG. 13 (c). The figure shows regions P1, N1,
Using P1 ^▲ and N1 ^▲ P and N channel MOSFETs, 3 input C
This shows a case where a MOS NOR circuit CRN is formed.

Referring again to FIG. 13 (a), the output of the CMOS inverter CIV1 drives the input of the CMOS NOR circuit CNR2 of the basic cell BC1. That, and the output wiring of the CMOS inverter CIV1 is extended from the right end of the base cell BC2 to the left edge of the base cell BC1, the output load capacitance C _L is is considered to be relatively large, the CMOS inverter CIV1 the wide gate width PMOSFET And the NMOSFET, the transmission delay time can be made relatively small. MOSFET with wide gate width
Can also be used for such applications.

FIG. 14 is a diagram showing the basic cell BC3 shown in FIG.
FIG. 3 shows a cross-sectional view along Z ′.

As shown in the figure, this structure has a gate 32, an N ^- well 50 and a P ^- well 52, a PMOSFET made of polycrystalline silicon.
P ⁺ type diffusion layer 35 as the source / drain of NMOSFET, N ⁺ type diffusion layer 36 as the source / drain of the NMOSFET, N type diffusion layer 40 forming the emitter of NPN bipolar transistor B5, and forming the base of bipolar transistor B5 P-type diffusion layer 41
And an N-type diffusion layer 42 constituting the collector thereof.

This structure can be formed by utilizing well-known semiconductor manufacturing technology. For example, the P-type isolation regions 102 and ^▲ can be formed in the semiconductor substrate 100 by diffusing (introducing) boron into the semiconductor substrate 100. On the other hand, the N ⁺ type buried regions 101, 101 'and 101 "
It can be formed by diffusion (introduction) of antimony into the inside. 1200 ° C. These dopants of 40 minutes diffusion, for example, those regions 101, 101 ^▼, 101 ^▼▼, can be utilized to initially form the 102 and 102 ^▲. Then N
^- -type epitaxial layer, by a typical epitaxial deposition John step (e.g. 970 ° C., 10 min), the areas
It can be formed on the semiconductor substrate 100 so as to cover 101, 102 and the like. Next, N-type well regions 50 and 103 and P-type well region 31 can be formed in the epitaxial layer by phosphorus and boron ion implantation, respectively. For example, the implantation of P-type ions is performed by using a SiO ₂ film formed by a LOCOS technique as a mask for ion implantation, and performing boron ion implantation at a dose of 4.0 × 10 Battoms / cm ² using a nitride film ( Si
125 KeV, dose 3 using ₃ N ₄ ) as a mask for ion implantation
It can be achieved by × 10 ¹¹ atoms / cm ² . This ion implantation step is performed, for example, at 1000 ° C. × 30
A 0 minute diffusion step can be followed, so that the respective regions 101, 102 etc. and the well regions 50, 51 and
Inflating 103 provides the structure shown in FIG. Following this, each of the MOS and bipolar transistors are formed in a general transistor formation techniques region drilled with the SiO ₂ layer 70 with. Finally, a phosphor-silicate glass (PSG) film 80 is deposited over the device for protection at 480 ° C. for 10 minutes.

Reference numeral 42 denotes an N ⁺ -type layer connecting the aluminum wiring 60 as a collector electrode and the N ⁺ -type buried layer 101 with low resistance. Reference numeral 90 denotes N ⁺ -type polysilicon, which is used to form an N ⁺ -type emitter region. PMOS and NMOS
The aluminum wiring 60 formed at this time is used as a source / drain electrode. FIG. 14 corresponds to a cross-sectional view in which the aluminum wiring 60 has been provided. Although the base electrode of the bipolar transistor B5 is not shown in the figure, it actually exists.

Although the invention made by the inventor has been specifically described based on the embodiments, the invention is not limited to the above-described embodiments, and various changes can be made without departing from the gist of the invention. Nor. For example, in FIG. 1, the basic cells BC need not all have the same circuit configuration. The ratio of the first cell provided in each basic cell BC, that is, the PMOS regions PM1 and PM2 and the NMOS regions NM1 and NM2, and the second cell, that is, the PMOS region PM3 and the NMOS regions NM3 to NM5 and the bipolar transistor regions BT1 to BT4, It can be changed appropriately according to the ratio of the CMOS logic gate circuit and the bipolar logic gate circuit included in the logic circuit constituted by the gate array. The number of P-channel MOSFETs and N-channel MOSFETs included in each PMOS region and NMOS region is, for example, two or four, for example, the average number of inputs of a logic gate circuit included in a logic circuit constituted by this gate array. Can be changed accordingly. The NMOS region NM5 may be, for example, a resistance means, or a BiCMOS
If a greater driving capability is required for the composite logic gate circuit, the number of bipolar transistor regions may be increased. In FIG. 2, the basic cells BC need not be particularly arranged in a lattice. Further, the gate array may partially include the basic cell BC as described above. In FIG. 3, the second cell of each basic cell BC is Bi
If CMOS logic gate circuits are not required, they may be used to construct CMOS logic gate circuits. Further, various embodiments such as the configuration of the basic cell BC shown in FIG. 1 and the specific circuit configuration of the Bi.CMOS logic gate circuit shown in FIGS. 6 (a) and 6 (b) can be adopted.

In the above description, the case where the invention made by the present inventor is mainly applied to a logic circuit constituted by a BiCMOS gate array which is a field of use as a background has been described, but the invention is not limited thereto. For example, the present invention can be applied to various digital devices such as a microcomputer including a similar gate array. INDUSTRIAL APPLICABILITY The present invention can be widely applied to a gate array integrated circuit having at least a CMOS logic gate circuit and a Bi.CMOS logic gate circuit as a basic configuration, or a digital device constituted by such a gate array integrated circuit.

〔The invention's effect〕

The effects obtained by the representative inventions among the inventions disclosed in the present application will be briefly described as follows. In other words, a gate array integrated circuit is basically
A first cell used to form an OS logic gate circuit and a second cell basically used to form a Bi / CMOS composite logic gate circuit in a predetermined ratio;
The Bi-CMOS logic gate circuit includes a pair of bipolar transistors that are selectively used when relatively large driving capability is required, and is composed of a plurality of cell masters arranged in a grid. And optimized CMOS logic gate circuit and Bi / CMOS composite logic gate circuit can be efficiently configured without waste. As a result, the number of circuit elements of the gate array integrated circuit can be reduced, the degree of integration can be increased, and the transmission delay time of a logic circuit or the like constituted by the gate array integrated circuit can be reduced.
The operation can be speeded up.

[Brief description of the drawings]

FIG. 1 is a layout diagram showing an embodiment of a basic cell included in a gate array to which the present invention is applied. FIG. 2 is a plan view showing an embodiment of a gate array including the basic cell of FIG. FIG. 3 is a circuit diagram partially showing an embodiment of a logic circuit constituted by the gate array of FIG. 2, and FIG. 4 is an embodiment of a CMOS inverter circuit included in the logic circuit of FIG. FIG. 5 is a circuit diagram showing one embodiment of a CMOS NAND gate circuit included in the logic circuit of FIG. 3, and FIG. 6 (a) is a circuit diagram of Bi included in the logic circuit of FIG.・ CMOS
FIG. 6 (b) is a circuit diagram of the Bi-CMOS NOR circuit BNO1 of FIG. 3, and FIG. 6 (c) is a modified diagram of a bipolar transistor. FIG. 6 (d) shows a plan view of the device of FIG. 6 (c), and FIG. 7 shows the relationship between the load capacitance and the transmission delay time of the CMOS logic gate circuit and the Bi-CMOS composite logic gate circuit. FIG. 8 shows an equivalent diagram of the basic cell BC of FIG. 1, and FIG. 9 shows a case where the circuit shown in FIG. 3 is formed using the equivalent diagram shown in FIG. FIG. 10 shows a plan view, FIG. 10 shows a layout diagram of the basic cells BC1 to BC4, FIG. 11 shows an equivalent view of the basic cell BC1 of FIG. 10, FIG. 12 shows FIGS. FIG. 13A is an explanatory diagram showing an example of use of each MOSFET and the bipolar transistor in the basic cell BC1 shown in FIG. 13. FIG. 13 (a) shows the basic cell shown in FIG. FIG. 13 (b) shows an example of a connection diagram of the base cells BC1, BC2 shown in FIG. 13 (a).
FIG. 13 (c) shows a circuit diagram formed by BC2, FIG. 13 (c) shows a connection diagram showing an example of how to use MOSFETs in the basic cells BC1 and BC2, and FIG. 14 shows ZZ of FIG. ′ Is a device cross-sectional view. BC, BC1, BC2 …… Basic cells, PM1 to PM3 …… PMOS region, NM1
NM5: NMOS region, BT1 to BT4: Bipolar transistor region, G: Gate, SUB: Semiconductor substrate. N1 to N4 CMOS inverter circuit, NAG1 to NAG2 CMOS NAND gate circuit, NOG1 CMOS NOR gate circuit, BNA1
… Bi-CMOS NAND gate circuit, BNO1… Bi-CMOS NOR gate circuit. Q1-Q7: P-channel MOSFET, Q11-Q21: N-channel MOSFET, T1-T4: NPN bipolar transistor.

Claims (5)

(57) [Claims] 1. A semiconductor integrated circuit comprising a plurality of logic gate circuits, wherein, among the plurality of logic circuits, a logic gate circuit having a small output load capacity is connected to a P-channel MOSFET and an N-channel MOSFET.
It consists of a CMOS gate circuit driven by a channel MOSFET,
For a logic gate circuit having a large output load capacitance, the input section includes a P-channel MOSFET and an N-channel MOSFET, and the output section includes a Bi-CMOS gate circuit including a bipolar transistor for driving the load. Among the Bi-CMOS gate circuits, the logic gate circuit whose output load capacitance is equal to or less than a predetermined value is effectively constituted by a Bi-CMOS gate circuit including a bipolar transistor having a small emitter size in an output portion, A semiconductor integrated circuit comprising a logic gate circuit whose output load capacitance is larger than the above-mentioned predetermined value, which is constituted by a Bi-CMOS gate circuit including a bipolar transistor having a large emitter size in an output portion thereof. . 2. The Bi-CMOS gate circuit according to claim 1, wherein said bipolar transistor having an effective large emitter size is realized by a parallel connection of collector-emitter paths of a plurality of transistors.
A semiconductor integrated circuit according to the item. 3. A parallel connection mode of the plurality of bipolar transistors, wherein a bipolar transistor inside a first basic cell capable of forming a Bi-CMOS gate circuit and a second basic cell capable of forming a Bi-CMOS gate circuit are provided. 3. The semiconductor integrated circuit according to claim 2, wherein said semiconductor integrated circuit is realized by parallel connection with an unused bipolar transistor inside said cell. 4. The first basic cell and the second basic cell are each rectangular, and the first basic cell and the second basic cell are arranged close to each other. A bipolar transistor inside the first basic cell and a bipolar transistor inside the second basic cell with respect to one side of the first basic cell are mirror-finished near the one side of the first basic cell. 4. The semiconductor integrated circuit according to claim 3, wherein the semiconductor integrated circuit is arranged at a symmetrical position. 5. The semiconductor integrated circuit according to claim 1, wherein said bipolar transistor is a totem-pole transistor at an output of a Bi-CMOS gate circuit. .