JP2778028B2 - Fault handling device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a fault processing device, and more particularly, to a fault process of a memory access address operation circuit provided in a processing device constituting an information processing system. 2. Description of the Related Art Conventionally, in an information processing system of this type, even if a failure occurs in a memory access address operation circuit (hereinafter, referred to as an address operation circuit) in each processing device, the processing device operates in the same manner as a failure in other circuits in the device. The obstacle was. In this case, depending on the hardware structure of the address operation circuit and the range of the failure, it is not possible to detect the occurrence of the failure by one memory access address operation, and as a result, the contents of the memory may be destroyed. Was. Further, even if a failure in the address operation circuit is detected after the destruction of the contents of the memory, the failure is regarded as a failure of the processing device. At this time, the destruction of the contents of the memory which has occurred earlier is detected retroactively. I never did. For example, as shown in FIG.
And the selector circuit 7 and the failure detection circuits 8 to 10 constitute an address operation circuit, and if the select signal 201 to the selector circuit 7 fails, the failure detection circuit 8 of the selector circuit 7 Failure may not be detected. That is, when the address “04” is input to the input signals 204 to the address calculators 5 and 6 and the selector circuit 7 selects the input signal 202 and attempts to add “06” to the address “04”, When the select signal 201 fails and the input signal 203 is selected and “02” is added to the address “04”, the data is output to the address “0A” of the memory (not shown) by the address operation circuit output signal 205. Is supposed to be written, but the data is written to address “06” of the memory,
The contents of the address "06" of the memory may be destroyed. In such a conventional information processing system, it is not possible to detect the occurrence of a failure in the address arithmetic circuit in each processing device, and as a result, the contents of the memory may be destroyed. Even if a failure is detected, the failure is regarded as a failure of the processing device, so that the destruction of the content of the memory is not repaired, and the use of the memory with the destructed content may cause the entire failure processing system to go down. There is a disadvantage that. In the case of a failure that would cause the contents of the memory to be destroyed, the failure rates in the failure detection circuits 8 to 10 and the address operation circuits 5 and 6 were examined and ignored when the failure rate was low. When it occurs, it affects the entire information processing system, and since the memory access is performed by many processing devices due to the increase in the scale of the information processing system, the failure cannot be ignored. SUMMARY OF THE INVENTION The present invention has been made in order to eliminate the above-mentioned drawbacks of the related art, and provides a failure processing apparatus capable of reducing the system down in the information processing system and improving the efficiency of the information processing system. Aim. A fault processing device according to the present invention is a fault processing device for an information processing system including a plurality of processing devices and a plurality of memory devices, wherein each of the plurality of processing devices has an access address to the memory device. Holding means for holding
Notification means for notifying the occurrence of a failure on the access address in its own device, and responding to the notification of the occurrence of the failure from one notification means of the processing device to one holding means of the processing device Specifying means for specifying a memory device specified by the held access address; and one of the processing devices in response to the notification of the occurrence of the failure.
And a memory for separating the memory device specified by the specifying device from the information processing system, and an erasing device for erasing the contents of the memory device separated by the separating device. Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of one embodiment of the present invention. In the figure, an information processing system according to one embodiment of the present invention includes a memory device 1-i (i = 1, 2, 3,..., N),
The processing device 2-j (j = 1, 2, 3,..., M), the fault processing device 3, and the disconnection and built-in circuits 4-1 and 4-2, these memory devices 1-i And the processing device 2-j are connected via the disconnection and built-in circuits 4-1 and 4-2. Consecutive addresses are assigned to the memory devices 1-i, respectively. That is, from the address 0 to the memory device 1-1,
The address is assigned, and the memory device 1-2 is assigned 20 addresses from 1001.
Address 00 is assigned. The processing device 2-j includes an address operation circuit 21-j, a failure detection circuit 22-j, and an access address holding circuit 23-j, respectively.
And an address fault notification circuit 24-j. The processing device 2-j and the fault processing device 3 are connected by a connection path 101, respectively. It should be noted that in FIG.
Only the configuration of -1 is shown. Further, the address operation circuit 21-j and the failure detection circuit 22
The configuration of -j is the same as that of the conventional address operation circuit shown in FIG. 2, and its operation is also the same. The fault processing device 3 includes a disconnection built-in circuit 31, an access address holding circuit reference circuit (hereinafter referred to as a reference circuit) 32,
A memory device indexing circuit (hereinafter referred to as an indexing circuit) 33;
And a memory clear circuit 34. The failure handling operation according to one embodiment of the present invention will be described with reference to FIGS. Here, it is assumed that a failure occurs in which the select signal 201 to the selector circuit 7 of the address arithmetic circuit 21-1 is stacked during the execution of the memory access from the processing device 2-1 to the memory device 1-1. When the occurrence of the failure is not detected by the failure detection circuit 8, the memory access to the memory device 1-1 is executed by the access address calculated by the address calculator 5, and the access address is stored in the access address holding circuit.
23-1 holds the access order. If a failure is detected by the failure detection circuit 8 during the execution of the memory access in sequence, the failure notification circuit 24-1 of the processing device 2-1 transfers the connection path 101 to the failure processing device 3.
Through the occurrence of obstacles through. Since the failure is an access address failure of the processing device 2-1, the failure processing device 3 disconnects the processing device 2-1 in which the failure has occurred and uses the embedded circuits 31, 4-1 and 4-2 to process the information processing system. Disconnect from Next, the contents of the access address holding circuit 23-1 inside the processing device 2-1 are read out by the reference circuit 32, and the contents are sent to the indexing circuit 33. In the indexing circuit 33, the reference circuit 32
When the memory device 1-1 is determined from the content sent from the memory device 1-1, the memory device 1-1 is separated and the built-in circuits 31, 4-1 and
Disconnect from the information processing system using 4-2. Since the separated memory device 1-1 has only been destroyed by the processing device 2-1, when the memory clear by the memory clear circuit 34 is completed, the memory device 1-1 is destroyed.
Are re-incorporated into the information processing system by the disconnection incorporation circuits 31, 4-1 and 4-2. Further, the occurrence of this failure is not detected by the failure detection circuit 8, and an access address exceeding the address assigned to the memory device 1-1 is calculated by the address calculator 5, and the memory access is executed with this access address. Then, the memory device 1-1 outputs an error reply indicating that there is no corresponding address to the processing device 2-1. That is, in FIG.
00 "is input, and the input signal 2
02 is selected and “10” should be added to the address “800” in the address calculator 5. However, a stack fault occurs such that the selector circuit 7 selects the input signal 203 in the select signal 201, and the address calculation is performed. It is assumed that "50" is added to the address "800" in the unit 5. Then, this failure is not detected by the failure detection circuit 8 and the memory access is continued at an incorrect access address. This incorrect access address “850”, “900”, “950”,
"1000" is sequentially connected to the access address holding circuit 23-1. However, when the next access address “1050” is output to the memory device 1-1, an error reply indicating that there is no corresponding address is sent from the memory device 1-1.
1 will be output. Upon receiving the error reply from the memory device 1-1, the processing device 2-1 notifies the failure processing device 3 of the occurrence of a failure from the address failure notification circuit 24-1 to the failure processing device 3 via the connection path 101. Since the failure is an access address failure of the processing device 2-1, the failure processing device 3 disconnects the processing device 2-1 in which the failure has occurred and uses the embedded circuits 31, 4-1 and 4-2 to process the information processing system. Disconnect from Next, the contents (access addresses "850", "900", "950", "1000", "1050") of the access address holding circuit 23-1 inside the processing device 2-1 are read out by the reference circuit 32, and are read. The contents are sent to the indexing circuit 33. In the indexing circuit 33, the memory devices 1-1, 1-1 are read from the contents sent from the reference circuit 32.
When -2 is determined, the memory devices 1-1 and 1-2 are separated and separated from the information processing system using the built-in circuits 31, 4-1 and 4-2. Thus, even if data is written to an incorrect address of the memory device 1-1, the other processing devices 2-2 to 2-
m can be prevented from accessing the memory device 1-1, and a system down caused by the memory device 1-1 in the information processing system can be avoided. Here, the memory device 1-2 is also disconnected from the information processing system. However, this is because data is erroneously written to the memory device 1-2 by the output of the access address “1050” from the processing device 2-1. This is due to consideration of the case. The separated memory devices 1-1 and 1-2 are connected to the processing device 2-1.
When the memory clear by the memory clear circuit 34 is completed, the memory devices 1-1 and 1-2 are separated and incorporated into the information processing system again by the incorporation circuits 31, 4-1 and 4-2. It is. As described above, when a failure occurs in the access address from the processing device 2-1 to the memory device 1-1, the occurrence of the failure is notified from the address failure notification circuit 24-1 to the failure processing device 3, and the notification is made. The processing device 2-1 is disconnected from the information processing system by the failure processing device 3
The reference circuit 32 separates the memory device 1-1 determined by the indexing circuit 33 by the access address read from the access address holding circuit 23-1 of the processing device 2-1 from the information processing system. In addition, it is possible to reduce the system down of the information processing system caused by the memory device 1-1 in which data is written to an incorrect address, to improve the availability (effectiveness) of the information processing system, and to improve the efficiency. Can be improved. In addition, by clearing the contents of the separated memory device 1-1 by the memory clear circuit 34 and then incorporating the same again into the information processing system, the memory device 1 in which data is written at an incorrect address is written. 1 can be used again in the information processing system, so that the availability of the information processing system can be improved and the efficiency thereof can be improved. Effects of the Invention As described above, according to the present invention, when a failure occurs in an access address to a memory device in its own processing device, the failure processing device that has been notified of the failure has By disconnecting the device and the memory device specified by the access address held in the processing device from the information processing system, erasing the content of the separated memory device and incorporating it again into the information processing system, There is an effect that the system down in the information processing system can be reduced and the efficiency of the information processing system can be improved.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a configuration of one embodiment of the present invention, and FIG. 2 is a block diagram showing a configuration of a conventional address operation circuit. Explanation of reference numerals of main parts 1-1 to 1-n memory devices 2-1 to 2-m processing device 3 fault processing devices 21-1 to 21-m memory access address arithmetic circuit 22- 1 to 22-m failure detection circuits 23-1 to 23-m access address holding circuits 24-1 to 24-m address failure notification circuits 31, 4-1 and 4-2 disconnection built-in circuits 32: Access address holding circuit reference circuit 33: Memory device indexing circuit 34: Memory clear circuit

Claims (1)

(57) [Claims] A failure processing device of an information processing system including a plurality of processing devices and a plurality of memory devices, wherein a holding unit that holds an access address to the memory device in each of the plurality of processing devices; Notification means for notifying the occurrence of a failure on the access address,
A specifying unit that specifies a memory device specified by the access address held in one holding unit of the processing device in response to a notification of the occurrence of the failure from one notification unit of the processing device; A disconnecting unit that disconnects one of the processing devices and the memory device specified by the specifying unit from the information processing system in response to the notification of the occurrence of the failure, and a content of the memory device separated by the disconnecting unit. An error processing device, comprising: an erasing means for erasing.