JPH0766339B2 - Fault handling method - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a failure processing method, and more particularly, to failure processing of a memory access address arithmetic circuit provided in a processing device constituting an information processing system.

2. Description of the Related Art Conventionally, in this type of information processing system, even a failure in a memory access address operation circuit (hereinafter referred to as an address operation circuit) in each processing device is the same as a failure in another circuit in the device. Had been an obstacle.

In this case, depending on the hardware structure of the address operation circuit and the range of the failure, the occurrence of the failure cannot be detected by the address operation for one memory access, and as a result, the contents of the memory may be destroyed. It was Further, even if a failure in the address operation circuit is detected after the destruction of the contents of the memory, since the failure is regarded as a failure of the processing device, at this time, the destruction of the contents of the memory occurring before that is detected retroactively. It never happened.

For example, as shown in FIG.
If the selector circuit 5 and the fault detection circuits 6 to 8 constitute an address operation circuit, and the select signal 201 to the selector circuit 5 fails, the fault detection circuit 6 of the selector circuit 5 Sometimes the failure cannot be detected.

That is, when the address "04" is input to the input signals 204 to the address calculators 3 and 4, the selector circuit 5 selects the input signal 202 and tries to add "06" to the address "04", If the select signal 201 fails and the input signal 203 is selected, and "02" is added to this address "04",
Originally, data should be written to the address "0A" of the memory (not shown) by the address calculation circuit output 205,
Data may be written to the memory address "06" and the contents of the memory address "06" may be destroyed.

In such a conventional information processing system, it may not be possible to detect the occurrence of a failure in the address operation circuit in each processing device, and as a result, the contents of the memory may be destroyed. Even if the failure is detected, the failure is regarded as a failure of the processing device, so that the destruction of the contents of the memory is not repaired, and the use of the destroyed memory may cause a system failure of the entire failure processing system. There is a drawback that.

For the failure that causes the contents of the memory to be destroyed, the failure rate in the failure detection circuits 6 to 8 and the address operation circuits 3 and 4 was examined, and when the failure rate was low, it was ignored. When it occurs, it affects the entire information processing system, and since memory access is being performed by many processing devices due to the large scale of the information processing system, the failure cannot be ignored.

An object of the present invention is to eliminate the above-mentioned drawbacks of the conventional ones, and to provide a failure processing method capable of reducing system down in an information processing system and improving the efficiency of the information processing system. To aim.

A failure processing method according to the present invention is a failure processing method for an information processing system including a plurality of processing devices and a plurality of memory devices to which consecutive addresses are assigned,
Each of the plurality of processing devices has holding means for holding an access address to the memory device, and notifying means for notifying another device of the occurrence of a failure on the access address in the own device, and the plurality of processing devices. One of the plurality of processing devices and a memory device specified by the content of the holding means of the processing device are processed by the processing device that has received the notification when the notification of the occurrence of the failure is notified from one notification device of the device. It is characterized in that it is separated from the information processing system.

Embodiment Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In the figure, an information processing system according to an embodiment of the present invention includes a memory device 1-i (i = 1, 2, 3, ..., N) and a processing device 2-j (j = 1, 2, 3, .., m), and the memory device 1-i and the processing device 2-j are connected by a connection path 101.

A continuous address is assigned to each of the memory devices 1-i. That is, addresses 0 to 1000 are assigned to the memory device 1-1, and addresses 1001 to 2000 are assigned to the memory device 1-2.
The address is assigned.

The processing device 2-j includes an address calculation circuit 21-j, a failure detection circuit 22-j, and an access address holding circuit 23-j, respectively.
And the address fault notification circuit 24-j, and the processing devices 2-j are connected to each other by a connection path 102. Note that FIG. 1 shows only the configuration of the processing device 2-1.

Further, the address calculation circuit 21-j and the fault detection circuit 22-
The configuration of j is the same as that of the conventional address operation circuit shown in FIG. 2, and its operation is also the same.

The fault handling operation according to the embodiment of the present invention will be described with reference to FIGS. 1 and 2.

Here, it is assumed that a failure occurs in which the select signal 201 to the selector circuit 5 of the address operation circuit 21-1 is stacked during the memory access from the processing device 2-1 to the memory device 1-1.

When the occurrence of this fault is not detected by the fault detection circuit 6, the memory access to the memory device 1-1 is executed by the access address calculated by the address calculator 3,
The access address is the access address holding circuit 23-
1 is held in the order of access.

When a failure is detected by the failure detection circuit 6 while the memory access is being sequentially executed, the failure notification circuit 24-1 of the processing apparatus 2-1 connects the processing paths to the processing apparatuses 2-2 to 2-m. The occurrence of a failure is notified via 102.

For example, when the processing device 2-2 receives the notification of the occurrence of this failure, the processing device 2-2 scans the access address holding circuit 23-1 of the processing device 2-1 and holds it in the access address holding circuit 23-1. The memory device 1-1 is specified from the access address that has been set.

When the processing device 2-2 identifies the memory device 1-1, the memory device 1-1 and the failed processing device 2-1 are used by other processing devices 2-3 to 2-m of the information processing system. Notify, and the memory device 1-1 and the processing device 2-
1 and are separated from the information processing system.

Further, the occurrence of this failure is not detected by the failure detection circuit 6,
When the address arithmetic unit 3 calculates an access address that exceeds the address assigned to the memory device 1-1 and a memory access is executed at this access address, the memory device 1-1 returns an error reply indicating that there is no corresponding address. Is output to the processing device 2-1.

That is, in FIG.
0 "is input, and the input signal 20 is originally input by the selector circuit 5.
2 is selected and the address calculator 3 sets “1” to the address “800”.
Although 0 "should be added, a stack failure occurs such that the selector circuit 5 selects the input signal 203 as the select signal 201, and the address calculator 3 adds" 50 "to the address" 800 ". Then, the fault is not detected by the fault detection circuit 6 and the memory access is continued at the wrong access address.

This incorrect access address "850", "900", "950", "1"
000 "is sequentially held in the access address holding circuit 23-1. However, when the next access address" 1050 "is output to the memory device 1-1, there is no corresponding address from the memory device 1-1. Will be output to the processing device 2-1.

When the processing device 2-1 receives the error reply from the memory device 1-1, the address failure notification circuit 24-1 notifies the other processing devices 2-2 to 2-m of the occurrence of the failure.

When the processing device 2-2 receives this notification, the access address holding circuit 23-1 of the processing device 2-1 in which the failure has occurred is scanned and the access addresses "850" and "900" are received as in the case of the above-described failure processing. , "950", "1000", "1050" are read, the memory devices 1-1 and 1-2 are specified from these access addresses, and the memory devices 1-1 and 1-2 and the processing device 2-1 are identified. Disconnect from the information processing system.

As a result, even if the data is written in the wrong address of the memory device 1-1, the other processing devices 2-2 to 2-m are processed.
The memory access to the memory device 1-1 can be prevented, and the system down caused by the memory device 1-1 in the information processing system can be avoided.

Here, the memory device 1-2 is also disconnected from the information processing system, but this is because the output of the access address “1050” from the processing device 2-1 causes the data to be written in the memory device 1-2 by mistake. This is because the case where it has happened is taken into consideration.

Thus, when a failure occurs in the access address from the processing device 2-1 to the memory device 1-1, the occurrence of the failure is notified from the address failure notification circuit 24-1 to the other processing device 2
-2 to 2-m, and is specified by the access address read from the access address holding circuit 23-1 of the processing device 2-1 by the other processing devices 2-2 to 2-m that received the notification. By disconnecting the memory device 1-1 and the processing device 2-1 from the information processing system, the memory device 1 in which data is written at an incorrect address
The system down of the information processing system caused by -1 can be reduced, the availability (effectiveness) of this information processing system can be improved, and the efficiency thereof can be improved.

As described above, according to the present invention, when a failure occurs in the access address to the memory device in the own processing device, the occurrence of the failure is notified to another processing device, and the notification is received. By disconnecting the processing device in which the processing device has failed and the memory device specified by the access address held in the processing device from the information processing system, system down in the information processing system is reduced, There is an effect that the efficiency of the information processing system can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, and FIG. 2 is a block diagram showing the configuration of a conventional address arithmetic circuit. Description of symbols of main parts 1-1 to 1-n ... Memory device 2-1 to 2-m ... Processing device 21-1 to 21-m ... Memory access address arithmetic circuit 22-1 to 22-m ... ... Fault detection circuit 23-1 to 23-m ... Access address holding circuit 24-1 to 24-m ... Address fault notification circuit

Claims (1)

[Claims] 1. A failure processing method for an information processing system comprising a plurality of processing devices and a plurality of memory devices to which consecutive addresses are assigned, and a holding method for holding an access address to the memory device. Each of the plurality of processing devices, and means for notifying other devices of the occurrence of a failure on the access address in the device itself,
A memory identified by one of the plurality of processing devices and the content of the holding means of the plurality of processing devices by the processing device that has received the notification when the notification of the occurrence of the failure is given from the one notification means of the plurality of processing devices. A failure processing method characterized in that the apparatus and the information processing system are separated from each other.