JP2778166B2 - Method and apparatus for adaptive transform coding - Google Patents

Description

Description: FIELD OF THE INVENTION The present invention relates to a band compression technique for a signal such as voice / music, and more particularly to a band compression performed after linearly converting an input signal obtained in a time domain into another domain. About technology.

(Prior Art) To efficiently transmit information included in a signal such as voice / music using a line having a limited transmission capacity, reducing the amount of information is called band compression, and is mainly adapted. Differential Pulse Code Modulation [ADPCM] (Digital Coding of Waveforms, (Digital Coding
f Waveforms, Prentice-H
all), 1984, pp. 308; hereinafter, "Document 1") and adaptive transform coding [ATC] (IEEE TRANSACTI).
ONS ON ASSP) Vol. 27, No. 1, 1979, pp. 89-95;
Hereinafter, “Reference 2”) is known. Hereinafter, the outline of ATC will be briefly described according to Reference 2.

FIG. 4 is a block diagram showing one configuration example of the ATC. In an encoder composed of linear conversion, bit allocation, and quantization, an input signal is supplied to a linear conversion circuit 3 via an input terminal 1. Generally, a discrete value is supplied to the input terminal 1,
The linear conversion circuit 3 performs N-point discrete linear conversion in units of input samples equal to a predetermined integer N. N is called the block length. The N-point discrete linear transform includes Walsh Hadamard transform (WAT), discrete Fourier transform (DFT), discrete cosine transform (DCT), and KL transform (KL
T) etc. are used. The total number N of conversion coefficients output from the linear conversion circuit 3 are quantized by the quantizer 4 according to the bit allocation described later.
, And is supplied to the multiplexing circuit 5. The quantizer 4 includes a number of quantizers equal to the block length N, and each transform coefficient is quantized by a dedicated quantizer. The bit distribution circuit 6 calculates a quantization bit allocation corresponding to the amplitude of the transform coefficient and supplies the calculated quantization bit allocation to the quantizer 4. The multiplexing circuit 5 multiplexes the quantized transform coefficient supplied from the quantizer 4 and the information used for bit allocation supplied from the bit allocation circuit 6, and sends out to the transmission line 8.

In a decoder consisting of bit allocation, inverse quantization, and linear inverse transform, the multiplexed signal from the transmission line 8 is separated by a separation circuit 9, and the signal from the quantizer 4 is subjected to bit allocation to an inverse quantizer 10. The signal from the circuit 6 is supplied to a bit distribution circuit 11. In the bit allocation circuit 11, the bit allocation circuit 6 of the encoder is used.
The bit allocation for each transform coefficient is determined in exactly the same manner as described above. In the inverse quantizer 10, the transform coefficient inversely quantized according to the bit allocation determined by the bit allocation circuit 11,
The signal is again converted into a total number N of time domain signal samples by the linear inverse conversion circuit 12 and supplied to the output terminal 14.

There are several types of allocation methods in the bit allocation circuit. Here, the method described in Reference 2 will be described with reference to FIGS. 5 (a) and 5 (b). This method
This is to minimize the quantization square error at the time of inverse quantization in the decoder. In order to reduce the amount of auxiliary information related to bit allocation, the transform coefficients are thinned out once, and then the bits are interpolated using the interpolated values. Perform number optimization. The bit distribution circuit I shown in FIG. 4 is configured as shown in FIG. The conversion coefficient obtained by the linear conversion circuit 3 shown in FIG. 4 passes through the input terminal 41 shown in FIG.
Supplied to 42. The thinning circuit 42 squares each of the N transform coefficients, and performs 1 / M thinning with an average value for each integer value M (M is a divisor of N) as a representative value. L = N / M obtained
Are sampled by a quantizer 43 and supplied to an output terminal 44 and an inverse quantizer 45. The quantizer 43 and the inverse quantizer 45 may be omitted in some cases. In the interpolation circuit 46, after taking a logarithm with a base of 2, linear interpolation of M times is performed in a logarithmic domain. The bit distribution in the quantizer 4 in FIG. 4 is performed by the bit number optimizing circuit 47 according to the following equation using the interpolated signal.

Here, R _i is the number of allocated bits for the i-th transform coefficient (i = 1, 2,... ‥ N), is the average number of allocated bits per transform coefficient, and σ _i ² is the approximate value obtained by interpolation in the interpolation circuit 46. Is the square value of the i-th transform coefficient restored to The result is transmitted to the output terminal 48 and supplied to the quantizer 4. By performing the bit allocation using equation (1), it is possible to minimize the quantization squared error. IEEE Transactions on ISSP (IEEE TRANSACTIONS)
ON ASSP), Vol. 25, No. 4, 1977, pages 299-309;
(Hereinafter, “Reference 3”). The decimated signal obtained at the output terminal 44 is sent to the transmission line 8 as auxiliary information via the multiplexing circuit 5 shown in FIG. On the other hand, the bit distribution circuit 11 in FIG. 4 is configured as shown in FIG. 5 (b). The signal from the separation circuit 9 in FIG. 4 is supplied to the interpolation circuit 46 via the input terminal 49. When the bit allocation circuit 6 in the encoder has a quantizer 43 and an inverse quantizer 45, the bit allocation circuit 11 in the decoder also has an inverse quantizer 45 correspondingly. The interpolation circuit 46 and the bit number optimization circuit 47 perform the same interpolation and bit number optimization as the interpolation circuit 46 and the bit number optimization circuit 47 in the encoder described above. Therefore, the output terminal 48 of FIG.
A signal for exactly equal bit allocation is obtained at the output terminal 50 of the, and the corresponding quantization / dequantization is performed on the encoder side and the decoder side.

In the description so far, the signal supplied as auxiliary information from the bit distribution circuit 6 to the multiplexing circuit 5 has been the square value of the thinned conversion coefficient obtained at the output terminal 44 in FIG. 5 (a). However, the purpose of transmitting this signal to the decoder is to share the approximate value of the transform coefficient used for bit allocation between the encoder and the decoder. As a method for transmitting auxiliary information for this purpose, a method using a PARCOR coefficient, ADPCM, vector quantization, and the like are known in addition to the square value of the thinned transform coefficient.

In the encoder, the input signal can be normalized in order to obtain a conversion coefficient whose amplitude does not depend on the power of the input signal at the output of the linear conversion circuit 3 in FIG. In this case, as shown in FIG. 6, the input signal is normalized by the normalization circuit 2 and then supplied to the linear conversion circuit 3. In the decoder, the output of the linear inverse transform circuit 12 is subjected to processing opposite to that of the normalization circuit 2 by the inverse normalization circuit 13, and then transmitted to the output terminal 14. The reference value used for normalization is multiplexed by the multiplexing circuit 5 with the signals from the quantizer 4 and the bit allocation circuit 6,
The signal is transmitted to the decoder via the transmission line 8. On the decoder side, the signal is separated by the separation circuit 9 from the signal supplied to the inverse quantizer 10 and the bit distribution circuit 11, and then transmitted to the inverse normalization circuit 13. FIGS. 7A and 7B show the configurations of the normalization circuit 2 and the denormalization circuit 13, respectively. An input signal sample is supplied to the input terminal 61 in FIG. 7A from the input terminal 1 in FIG. After the input signal samples are temporarily stored in the buffer 62, they are collectively scaled by the multiplier 63 every N samples, and supplied to the output terminal 65. The output signal from the output terminal 65 is supplied to the linear conversion circuit 3 shown in FIG. The multiplier of the multiplier 63 is the reciprocal of the average value of one block of the power of the input sample. This value is the reciprocal of the variance for an input signal having a mean of zero, and can be calculated from the variance value obtained by the variance calculation circuit 64. The variance value obtained by the variance calculation circuit 64 is used by the multiplier 63 for normalization of the input sample, and at the same time, is supplied to the multiplexing circuit 5 of FIG. It is transmitted to the decoder as auxiliary information. On the other hand, in the inverse normalization circuit shown in FIG. 7B, the signal from the linear inverse transformation circuit 12 shown in FIG. 6 is supplied to the multiplier 68 via the input terminal 67. The multiplier 68 denormalizes the output signal using the variance value obtained via the input terminal 69 and accumulates the output signal in the buffer 70. The variance obtained at the input terminal 69 is transmitted from the encoder via the multiplexing circuit 5, the transmission line 8, and the demultiplexing circuit 9 shown in FIG. Buffer 70 is N
The decoded sample values are sequentially transmitted to the output terminal 14 of FIG. 6 via the output terminal 71.

(Problems to be Solved by the Invention) The number of blocks N affects the resolution of the operations performed by the linear conversion circuit 3 and the linear inverse conversion circuit 12 shown in FIGS. 4 and 6, and the higher the N, the higher the resolution. In other words, errors due to encoding and decoding are reduced. The auxiliary information related to bit allocation is inversely proportional to the number of blocks included in a certain period of time. The larger the value of N, the smaller the amount of auxiliary information. This means that more main information can be sent for a given transmission capacity, which leads to improved coding quality. On the other hand, a large N does not always give a small error to an unsteady signal. This is because the same processing is performed on input samples in the same block, but if the block is long, the characteristics of an unsteady signal may change in the same block. Therefore, it is better to perform encoding that follows a change in the properties of the input signal with a small block length N for a signal having a strong non-stationary property. Conventional ATC
However, since the block length N was fixed, it was not possible to respond to the conflicting demands of following the resolution and the change in the properties of the input signal.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a method and apparatus for adaptive transform coding which can improve the coding quality by compressing the amount of auxiliary information while satisfying conflicting requirements of resolution and following changes in the properties of an input signal. It is in.

(Means for Solving the Problems) According to the present invention, when a block length is specified, linear conversion is performed with the specified block length, otherwise, input signal samples are stored in a buffer. Performing a linear transformation with a plurality of block lengths, storing the obtained transformation coefficients and auxiliary information independently of each other, and obtaining an inter-block difference of the transformation coefficients corresponding to the plurality of block lengths, and calculating the plurality of block lengths. An optimal block length is determined using the ratio of the inter-block difference corresponding to two adjacent block lengths and the inter-block difference when arranged in the order of size, and the stored transform corresponding to the optimal block length is determined. A coefficient and auxiliary information are selected, quantization is performed on the selected transform coefficient by bit allocation calculated using the transform coefficient, and the quantized output and bit allocation information are obtained. And transmitting / accumulating the information and the selected auxiliary information together with the optimum block length.

The present invention also provides a buffer for storing input samples,
A linear conversion circuit for performing a linear conversion with a plurality of block lengths and a first block for storing the obtained conversion coefficient;
Storage device, a second storage device for storing the obtained auxiliary information, and difference detection for receiving the transform coefficient corresponding to a plurality of block lengths and outputting an optimal block length using an inter-block difference of the transform coefficient. A first selector for receiving an optimum block length supplied from the difference detection circuit and a block length designating signal supplied from outside, and selecting an output according to the block length designating signal; A second selector that receives the output of the storage device and selects a value corresponding to the output of the first selector; and receives the output of the second storage device and sets a value corresponding to the output of the first selector. A third selector for selecting, a bit allocation circuit for calculating a bit allocation for a transform coefficient based on an output of the second selector, and a second selector for selecting the second selector according to the bit allocation obtained by the bit allocation circuit. A quantizer for quantizing the transform coefficient selected in step (a), multiplexing the output of the first selector, the output of the quantizer, the output of the bit distribution circuit, and the output of the third selector to transmit / At least a multiplexing circuit for accumulating, the difference detection circuit includes a switch for switching an input transform coefficient according to a plurality of block lengths, a plurality of storage devices connected to a plurality of output terminals of the switch, A selector for selecting one of the outputs of the plurality of storage devices, a subtracter for subtracting the output of the selector from the input transform coefficient, a multiplier for squaring the output of the subtractor, and an output of the multiplier Accumulator, a third storage device for storing the output of the accumulator, a maximum value detection circuit for obtaining a maximum value from a plurality of outputs of the third storage device, Fourth storage device for storing the output of the circuit When the divider determining the ratio of the two data of the plurality of outputs of said fourth storage device, and a fifth storage device that stores the output of 該除 adder,
An optimal block length selection circuit for determining an optimal block length using the output of the fifth storage device; and a sudden block for receiving a plurality of outputs from the third storage device and detecting a remarkable change between the plurality of outputs. A fluctuation detecting circuit, and a fifth selector for selecting and outputting one of the output of the optimum block length selecting circuit and the output of the sudden fluctuation detecting circuit according to the output of the sudden fluctuation detecting circuit. Features.

(Operation) There is a correlation between the property of the signal and the distribution of the transform coefficient component, and a signal having a similar property has a similar transform coefficient component distribution. This is true for transform coefficients in a plurality of blocks extracted from the same signal. Therefore, by monitoring the difference between the transform coefficients between the adjacent blocks and using a block length that reduces the difference, the conflicting requirements of following the change in the resolution and the property of the input signal can be satisfied.

An adaptive transform coding method and apparatus according to the present invention is capable of changing a block length N by using an inter-block difference of a transform coefficient obtained by linearly transforming an input signal, so that a resolution and a change in properties of the input signal can be reduced. While compensating for the conflicting requirement of following, the encoding quality can be improved by compressing the amount of auxiliary information.

Embodiment Next, the present invention will be described in detail with reference to the drawings.
FIG. 1 is a block diagram showing one embodiment of the present invention.
In the figure, when a block length is specified, coding is performed with the specified block length, otherwise, a linear conversion is performed on the input signal, and the obtained conversion coefficient is used. The optimal block length is determined, and encoding is performed using the optimal block length. To this end, storage devices 25, 2
6, selectors 27, 28 and 29, a difference detection circuit 36 and a block length designation signal input terminal 17 are provided.

When the input signal to the block length specifying signal input terminal 17 is not supplied, the input signal supplied to the input terminal 1 is normalized by the variance value of the input signal normalization circuit 2 with a candidate N ₁ block length Be transformed into After normalized signal is subjected to N ₁ point discrete linear transformation in the linear conversion circuit 3 is supplied to the difference detection circuit 36 at the same time is stored in the storage device 25. The variance value used for the normalization is stored in the storage device 26. Then with respect to equal sample block length N ₂ in the second, normalized in the same manner as in the N _1, linear transformation is performed, the results are stored in the storage device 25 and 26, the difference detection circuit 36
Supplied to As in the case of N _1, N ₂ described above, a plurality of block length N _3, N _4, ... distributed normalized and linear conversion is performed corresponding transform coefficient by the input signal for the case of ‥ N _n The values are stored in the storage circuits 25 and 26, and the conversion coefficients are also supplied to the difference detection circuit 36. However, usually N ₁ <
N ₂ <N ₃ <N ₄ ... ‥ <N _n and 2N _i = N _{i + 1} (1 ≦ i <n). When all the calculation of the conversion coefficients for the block lengths N ₁ , N ₂ , N ₃ , N ₄ ,... ‥ N _n are completed, the difference detection circuit 36 converts each block length candidate value N _i (1 ≦ i <n). Coefficient y _j (N _i ) (j =
1 ... ‥ N _i) the sum of the inter-block difference square value of the transform coefficients that for one block previous value _{z j (N i) δ (} N i) Is calculated. The optimum block length N _m is selected using δ (N _i ) and supplied to the selector 27. The selector 27 is also supplied with a block length selection signal. Selector 27
It is the block length selection signal when the block length selection signal is supplied, otherwise selects the optimum block length N _m supplied from the difference detection circuit 36, an output signal. Selectors 28 and 29 are output by the output signal of selector 27.
Optimum block length transform coefficients and side information corresponding to N _m is selected, the transform coefficients and quantizer 4 bit allocation circuit 6, the dispersion value and the optimal block length N _m of the input signal is an auxiliary information multiplexed in Are supplied to the conversion circuit 15. Optimally block length N _m is sometimes transmitted to the multiplexing circuit 15 are quantized. The bit allocation circuit 6 performs bit allocation using the transform coefficient supplied from the selector 28, and the quantizer 4 uses the obtained bit allocation information to perform the bit allocation.
The quantization of the transform coefficient supplied from is performed. The quantized transform coefficient, the bit allocation information is a multiplexing circuit 15,
Is variance multiplexed with the optimum block length N _m and the input signal, it is sent to the transmission line 8.

When supplied the input signal to the block length specifying signal input terminal 17, the selector 27 selects the supplied block length N _s, is set to the optimum block length N _m. Therefore, the quantization of subsequent performed based on the supplied block length N _s.
Next, an actual procedure for selecting an optimum block length will be described with reference to FIG. 2 by taking as an example a case where the optimum block length is determined from n types of block lengths. Here, for the sake of simplicity, it is assumed that n = 3 (the optimum block length is selected from three block lengths) as shown in FIG.

It is assumed that time t = 0 when the encoder starts operating.
At time N ₁ T (T is a sampling period), N ₁ input signal samples are accumulated in the buffer in the normalization circuit of FIG. This situation is shown in FIG. 2A.
In the figure, an input signal sample indicated by N ₁ (1), that is, a portion indicated by I and hatched is subjected to a linear conversion with a block length N ₁ , and the conversion coefficient is stored in a storage device. At time N ₂ T, samples equal to the second block length N ₂ (N ₁ <N ₂ ) are accumulated in the buffer. This situation is shown in FIG. 2 (a) (B). At this time, N ₁
The block length N ₁ for the input signal sample indicated as (2), that is, the hatched portion indicated as II
, And the block length N for the input signal samples denoted as N ₂ (1), that is, for the hatched portion denoted as I and the hatched portion denoted as II. _The linear conversion by ₂ is performed, and each conversion coefficient is stored in the storage device. Time (N ₁ + N ₂ ) T
Accumulates samples equal to N ₁ + N ₂ in the buffer. This situation is shown in FIG. 2 (A) (C). At this time, the input signal sample indicated by N ₁ (3) in FIG.
That performs a linear transformation by the block length N ₁ against decorated portions hatched been shown to III, to store the conversion factor to the storage device. Further, at time N ₃ T, samples equal to the third block length N ₃ (N ₁ <N ₂ <N ₃ ) are accumulated in the buffer. This situation is shown in (D) of FIG. At this time, the input signal sample indicated by N ₁ (4) in the same figure, that is, a portion indicated by IV and hatched is subjected to linear conversion by the block length N ₁ and N ₂
(2) a displayed input signal sample, ie performs linear transformation by the block length N ₂ for the indicated shown a decorated portion and an IV hatches in part has been subjected to hatching with III, further N ₃ (1) and displayed input signal samples, i.e. I, II, III, performs linear conversion by block length N ₃ for the portion that has been subjected to hatching shown and IV, the respective transform coefficient storage device To be stored.
Hereinafter, N ₁ (1), N ₁ (2), N ₁ stored in the storage device
(3), transform coefficients corresponding to N ₁ (4), N ₂ (1) and N
_{2 Using} the transform coefficient corresponding to (2) and the transform coefficient corresponding to N ₃ (1), block-to-block differences δ (N ₁ ), δ () of the transform coefficients for the block lengths N ₁ , N ₂ , N ₃ N ₂ ) and δ (N ₃ ) are calculated to determine the optimum block length N _m .

FIG. 2 (b) summarizes the above processing procedure.
Taking the case of N ₃ = 2N ₂ = 4N ₁ as an example, the maximum block length N ₃ can be represented by four minimum block lengths N ₁ of I, II, III, and IV. I, II, III, respectively a linear conversion using a block length N ₁ to the input data block of IV II, II
This is performed in blocks I, IV, and I '. I + II and I
Linear transformation using the block length N ₂ for the input data of the block of II + IV is respectively performed in block III and I '. Furthermore, a linear conversion using a block length N ₃ to the input data of the block of I + II + III + IV is carried out in blocks of I '. Therefore, in the block of I ′ having the largest processing amount, the block length N _{1 with} respect to IV
, Linear transformation using block length N ₂ for III + IV, block length N ₃ for I + II + III + IV
, And the inter-block difference δ between transform coefficients
(N ₁ ), δ (N ₂ ), δ (N ₃ ) must be calculated, and the optimum block length N _m must be determined using these. That is, it is assumed that the time required for all these processes is shorter than N ₁ T.

As apparent from FIG. 2 (b), the buffer in the normalizing circuit 2 must have a capacity of at least N ₃ T, and is reset every N ₃ T. Transform coefficients corresponding to the selected optimal block length are taken out of the storage device in N ₃ samples, quantized by the quantizer 4, and then sent out to the transmission line 8 in FIG. Accordingly, the data to be transmitted to the transmission path 8, as shown in FIG. 2 (c), the same block length N ₃ as the unit is continuous. Hereinafter, this block length is called a unit block. Next, the operation of the difference detection circuit 36 will be described in detail with reference to FIG.

FIG. 3 shows the details of the difference detection circuit 36. The signal supplied from the linear conversion circuit 3 in FIG. 1 is supplied to an input terminal 301, and the signal from an output terminal 314 is transmitted to a selector 27. The conversion coefficient supplied to the input terminal 301 is a switch 302,
The signals are input to the selector 304 and the subtractor 305. The output terminals of the switch 302 are connected to storage devices 303 ₁ , 303 ₂ ,.
303 _n is connected. Storage devices 303 ₁ , 303 ₂ , ‥, 30
3 _n corresponds to the block lengths N ₁ , N ₂ ,..., N _n , and 303 _i
Stores the transform coefficient z _j (N _i-1 ) (j = 1... ‥ N _i ) of the previous block. The selector 304 selects these storage devices 30
One of the outputs of 3 ₁ , 303 ₂ ,..., 303 _n is selected and transmitted to the subtractor 306. Switch 302 and selector 304 are both
It is controlled by the conversion coefficient supplied to the input terminal 301. The output of the selector 304 is subtracted from the transform coefficient supplied to the input terminal 301 by the subtractor 305, and the result is supplied to the multiplier 306. That is, when the conversion coefficient corresponding to a certain block length N _i is supplied to the input terminal 301, corresponding to N _i 1
The transform coefficient before the block is selected by the selector 304, and is subtracted by the subtractor 305 from the transform coefficient of the current block supplied to the input terminal 301. At the same time, the current conversion coefficients are stored in the storage device 303 _i connected by the switch 302. The multiplier 306 squares the difference between blocks of the transform coefficient supplied from the subtractor 305. The calculation so far is performed for each transform coefficient. The obtained inter-block difference square value is accumulated by the accumulator 307, and the sum of all the conversion coefficients of the inter-block difference square value of the conversion coefficient is obtained. Hereinafter, this is simply called a difference between blocks of the transform coefficient. The inter-block difference of the transform coefficient output from the accumulator 307 is calculated for each unit block and stored in the storage device 308.

The maximum value detection circuit 309 detects the maximum value of the difference between blocks of the transform coefficient corresponding to each block length candidate value for each unit block, and stores it in the storage device 310. That is,
For each unit block, the storage device 310 stores the maximum difference between blocks of the transform coefficient by the number of the block length candidate values. The division circuit 316 uses these maximum values max {δ (N _i )} supplied from the storage device 310 to calculate the adjacent maximum values max ｛δ (N _i )｝ and max ｛δ (N _{i + 1} ). The ratio δ _R (i) = max ｛δ (N _i +1)｝ / max ｛δ (N _i )｝ ‥‥ (3) is calculated for 1 ≦ i ≦ n−1 and stored in the storage device 315. I do. max ｛·｝ is a maximum value operator. The optimum block length selection circuit 311 determines the optimum block length using the ratio δ _R (i) supplied from the storage device 315, and transmits it to the selector 313. In the optimal block length selection circuit 311, mi
The optimum block length N _m is determined by searching for i that gives n {δ _R (i)} for 1 ≦ i <n−1 and setting m = i. min ｛·｝ is a minimum operator.

In parallel, the sudden change detection circuit 312 detects a sudden change in the input signal characteristic using the difference between the transform coefficient blocks, and unconditionally selects the minimum block length when the sudden change is detected. This is because the sudden change detection circuit 312 selects the selector 313
Is transmitted by the selector 313 to the output terminal 314. The detection of the sudden change in the input signal characteristic is performed by comparing the value of δ (N ₁ ) obtained from the storage device 308. Since the storage device 308 stores δ (N ₁ ) of N _n / N ₁ for one unit block,
The ratio of all adjacent δ (N ₁ ), δ _{p + 1} (N ₁ ) / δ _p (N ₁ )
And δ _p (N ₁ ) / δ _{p + 1} (N ₁ ) are checked for 1 ≦ p <N _n / N ₁ , and if any one exceeds a predetermined threshold value Th, the Assume that a change has been detected. The threshold Th is determined by experience.

In the description of the embodiments up to this point, it has been assumed that the normalization circuit 2 is present. However, as already described with reference to FIGS. 4 and 6 in the description of the conventional ATC, the input signal is The process of normalizing by variance can be omitted. However, unlike the conventional example, the buffer cannot be omitted. In FIG. 1, when the input signal shown in FIG. 6 is not normalized, the storage device 26 and the selector 29 become unnecessary.

(Effects of the Invention) As described in detail above, according to the present invention, the optimal block length is selected using the difference between blocks of the transform coefficients obtained by performing the linear transformation with different block lengths, and the optimal block length is selected. An adaptive transform code that can compress the amount of auxiliary information and improve the coding quality while satisfying conflicting requirements of resolution and following changes in the properties of the input signal in order to transmit information by quantizing the transformed transform coefficients. It is possible to provide a method and an apparatus for the conversion.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, FIG. 2 is a diagram showing an example of a buffer state for storing input samples and a procedure for selecting an optimum block length, and FIG. FIG. 4 is a block diagram showing details of a detection circuit, FIG. 4 is a block diagram showing a conventional example, and FIGS. 5 (a) and (b) are diagrams showing details of a bit distribution circuit I and a bit distribution circuit II of FIG. FIG. 6 is a diagram showing another conventional example, and FIGS. 7 (a) and 7 (b) are diagrams showing details of the normalization circuit and the denormalization circuit in FIG. In the figure, 1, 17, 301 are input terminals, 2 is a normalization circuit, 3 is a linear conversion circuit, 4 is a quantizer, 6 is a bit allocation circuit, 8 is a transmission line, 15 is a multiplexing circuit, and 25 and 26. , 303 ₁ , ...
‥, 303 _n , 308, 310, 315 are storage devices, 27, 28, 29, 30
4, 313 are selectors, 36 is a difference detection circuit, 302 is a switch, 305 is a subtractor, 306 is a multiplier, 307 is an accumulator, 309 is a maximum value detection circuit, 316 is a divider, and 311 is an optimal block length selection. The circuit, 312 indicates a sudden fluctuation detection circuit, and 16 and 314 indicate output terminals, respectively.

Claims (2)

(57) [Claims] When an input signal is adaptively transformed and encoded in order to compress and transmit / store an information amount of a signal such as voice / music, if a block length is designated, the designated block is designated. Performs a linear transformation on the length, otherwise
The input signal samples are accumulated in the buffer, linear conversion is performed with a plurality of block lengths, and the obtained conversion coefficients and auxiliary information are stored independently, and at the same time, the difference between blocks of the conversion coefficients corresponding to the plurality of block lengths is calculated. Determine, determine the optimal block length using the ratio of the inter-block difference corresponding to two adjacent block lengths and the inter-block difference when the plurality of block lengths are arranged in order of size,
Selecting the stored transform coefficients and auxiliary information corresponding to the optimal block length, performing quantization on the selected transform coefficients by bit allocation calculated using the transform coefficients, and A method for adaptive transform coding, comprising transmitting / accumulating bit allocation information and the selected auxiliary information together with the optimal block length. 2. A buffer for storing input samples, a linear conversion circuit for performing linear conversion with a plurality of block lengths and a plurality of block lengths, and a first storage device for storing obtained conversion coefficients. A second storage device that stores the auxiliary information, a difference detection circuit that receives the transform coefficients corresponding to a plurality of block lengths, and outputs an optimal block length using an inter-block difference of the transform coefficients; A first selector which receives an optimum block length supplied from the controller and an externally supplied block length designating signal and selects an output according to the block length designating signal; A second selector that selects a value corresponding to the output of the first selector, and a third selector that receives an output of the second storage device and selects a value corresponding to the output of the first selector.
, A bit allocation circuit that calculates a bit allocation for a conversion coefficient based on the output of the second selector, and a conversion coefficient selected by the second selector according to the bit allocation obtained by the bit allocation circuit. At least a quantizer for quantizing, and a multiplexing circuit for multiplexing and transmitting / accumulating an output of the first selector, an output of the quantizer, an output of the bit allocation circuit, and an output of the third selector. A switch for switching an input transform coefficient according to a plurality of block lengths; a plurality of storage devices connected to a plurality of output terminals of the switch; and an output of the plurality of storage devices. Fourth to select one of
A subtractor for subtracting the output of the fourth selector from the input transform coefficient, a multiplier for squaring the output of the subtractor, an accumulator for accumulating the output of the multiplier, A third storage device for storing an output of the accumulator, a maximum value detection circuit for obtaining a maximum value from a plurality of outputs of the third storage device,
A fourth storage device for storing the output of the maximum value detection circuit;
A divider for calculating a ratio of two data among a plurality of outputs of the fourth storage device, a fifth storage device for storing an output of the divider, and an output of the fifth storage device. An optimum block length selection circuit for determining an optimum block length;
A sudden change detecting circuit for receiving a plurality of outputs from the storage device and detecting a remarkable change between the plurality of outputs; an output of the optimum block length selecting circuit and An adaptive transform coding apparatus comprising a fifth selector for selecting and outputting one of the outputs of a detection circuit.