JP3092124B2 - Method and apparatus for adaptive transform coding - Google Patents

Abstract

PURPOSE:To enable both application wherein importance is attached to encoding delay and application wherein importance is attached to an encoding/decoding error mode by providing a changeover switch, and encoding a signal on a variable block length basis when importance is attached to the error in encoding and decoding or on a short block length basis when importance is attached to an encoding delay time. CONSTITUTION:An input signal sample obtained from an input terminal 1 is supplied to (n) encoders 1001, 1002... 100n at the same time. The respective encoders encodes the sample by using mutually different block lengths N1, N2... Nn and encoding outputs and auxiliary information on bit distribution, etc., are supplied and stored in a storage device 101 independently of one another. The encoding outputs are supplied to (n) decoders 1021, 1022... 102n at the same time and their decoding outputs are transmitted to an error calculating circuit 103. When, however, a specification signal is supplied to an input terminal 108, signals which are encoded with specified block lengths are sent and stored instead of the signals which are encoded with the best block lengths.

Description

Description: FIELD OF THE INVENTION The present invention relates to a band compression technique for a signal such as voice / music, and more particularly to a band compression performed after linearly converting an input signal obtained in a time domain into another domain. About technology.

(Prior Art) To efficiently transmit information included in a signal such as voice / music using a line having a limited transmission capacity, reducing the amount of information is called band compression, and is mainly adapted. Differential Pulse Code Modulation [ADPCM] (Digital Coding of Waveforms, (Digital Coding
f Waveforms, Prentice-H
all), 1984, pp. 308; hereinafter, "Document 1") and adaptive transform coding [ATC] (IEEE TRANSACTI).
ONS ON ASSP) Vol. 27, No. 1, 1979, pp. 89-95;
Hereinafter, “Reference 2”) is known. The outline of ATC will be briefly described below according to Document 2.

FIG. 6 is a block diagram showing one configuration example of the ATC. In the encoder, an input signal is supplied to a linear conversion circuit 3 via an input terminal 1. Generally, a discrete value is supplied to the input terminal 1, and an integer N predetermined by the linear conversion circuit 3.
N-point discrete linear transformation is performed in units of input samples equal to N is called the block length. As the N-point discrete linear transformation, Walsh-Hadamard transformation (WA
T), discrete Fourier transform (DFT), discrete cosine transform (DC
T), KL transformation (KLT) and the like are used. The total number N of transform coefficients output from the linear transform circuit 3 are quantized by the quantizer 4 in accordance with bit allocation described later, and supplied to the multiplexing circuit 5. The quantizer 4 includes a number of quantizers equal to the block length N, and each transform coefficient is quantized by a dedicated quantizer. The bit allocation circuit 6 calculates a quantization bit allocation corresponding to the amplitude of the transform coefficient,
It is supplied to the quantizer 4. In the multiplexing circuit 5, the quantizer 4
Is multiplexed with the quantized transform coefficient supplied from and the information used for the bit allocation supplied from the bit allocation circuit 6,
The data is transmitted to the transmission path 12.

In the decoder, the multiplexed signal from the transmission line 12 is
The signal from the quantizer 4 is separated by an inverse quantizer 14
The signal from the bit distribution circuit 6 is
Supplied to The bit allocation circuit 15 determines the bit allocation for each transform coefficient in exactly the same way as the bit allocation circuit 6 of the encoder. The transform coefficient inversely quantized by the inverse quantizer 14 in accordance with the bit allocation determined by the bit allocation circuit 15 is again converted into a total number N of time-domain signal samples by the linear inverse conversion circuit 16, and is output to the output terminal 18. Supplied.

There are several types of allocation methods in the bit allocation circuit. Here, the method described in Reference 2 will be described with reference to FIG. This method is to minimize the quantization square error at the time of inverse quantization in a decoder, and to reduce the amount of auxiliary information by one in order to reduce the amount of auxiliary information.
The number of bits is optimized by using the interpolated value after the thinning. The bit distribution circuit I shown in FIG.
It is configured as shown in FIG. The conversion coefficient obtained by the linear converter 3 is supplied to the thinning circuit 42 via the input terminal 41 shown in FIG. The thinning circuit 42 calculates the square of the N conversion coefficients, and thins out 1 / M with the average value for each integer M (M is a divisor of N) as a representative value. L = N obtained
The sample value of / M is quantized by a quantizer 43 and supplied to an output terminal 44 and an interpolation circuit 45. The quantizer 43 may be omitted in some cases. In the interpolation circuit 45, after taking a logarithm with 2 as a base, interpolation of M times is performed in a logarithmic domain. The bit distribution in the quantizer 4 is performed by the bit number optimizing circuit 46 by the following equation using the interpolated signal, and the result is transmitted to the output terminal 47 and supplied to the quantizer 4.

Here, R _i is the number of bits allocated to the i-th transform coefficient, is the average allocated bit number per transform coefficient, and σ _i ² is the square value of the i-th transform coefficient approximately restored by interpolation in the interpolation circuit 46. It is. By performing bit allocation using equation (1), the quantization square error can be minimized. IEEE Transactions on ASSP Vol. 25, No. 4
No. 1977, pp. 299-309; (hereinafter referred to as “Reference 3”). The decimated signal obtained at the output terminal 44 is sent out as auxiliary information via the multiplexing circuit 5. On the other hand, the bit distribution circuit 15 is configured as shown in FIG. The signal from the separation circuit 13 is supplied to the interpolation circuit 45 via the input terminal 48. When the bit allocation circuit 6 in the encoder has a quantizer 43, the bit allocation circuit 15 in the decoder also has an inverse quantizer 49 correspondingly. The interpolation circuit 45 and the bit number optimization circuit 46 perform the same interpolation and bit number optimization as the interpolation circuit 45 and the bit number optimization circuit 46 in the encoder described above. Therefore, signals for exactly the same bit allocation are obtained at the output terminal 47 in FIG. 6 (a) and the output terminal 50 in FIG. 6 (b), and the corresponding signals are obtained on the encoder side and the decoder side. The quantization / inverse quantization performed is performed.

In the description so far, the signal supplied as auxiliary information from the bit distribution circuit 6 to the multiplexing circuit 5 has been the square value of the thinned-out transform coefficient obtained at the output terminal 44 in FIG. 6 (a). However, the purpose of transmitting this signal to the decoder is to share the approximate value of the transform coefficient used for bit allocation between the encoder and the decoder. Therefore, in addition to the square value of the decimated transform coefficient, a method based on the PARCOR coefficient, ADPCM, vector quantization, and the like are known.

In order to obtain a transform coefficient whose amplitude does not depend on the power of the input signal, at the output of the linear transform circuit 3 in the encoder,
The input signal can also be normalized. In this case, the seventh
As shown in the figure, the input signal is supplied to a linear conversion circuit 3 after being normalized through a normalization circuit 2. In the decoder,
The output of the linear inverse transform circuit 16 is subjected to processing opposite to that of the normalization circuit 2 by the inverse normalization circuit 17 and then transmitted to the output terminal 18. FIGS. 8A and 8B show the configurations of the normalization circuit 2 and the denormalization circuit 17, respectively. An input signal sample is supplied to the input terminal 61 in FIG. 8A from the input terminal 1 in FIG. After the input signal samples are temporarily stored in the buffer 62, they are collectively scaled by the multiplier 63 every N samples, and supplied to the linear conversion circuit 3 via the output terminal 65. The multiplier of the multiplier 63 is an average value of one block of the power of the input sample. This value becomes a variance for an input signal having an average of zero, and is obtained by the variance calculation circuit 64. The variance value obtained by the variance calculation circuit 64 is used for normalization of the input sample by the multiplier 63, and at the same time, the output terminal
It is supplied to the multiplexing circuit 5 of FIG. 7 via 66, and after multiplexing, is transmitted to the decoder as auxiliary information. On the other hand, the eighth
In the inverse normalization circuit of FIG. 7B, the linear inverse transformation circuit of FIG.
The signal from 16 is supplied to the multiplier 68 via the input terminal 67. The multiplier 68 denormalizes the output signal using the reciprocal of the variance value obtained via the input terminal 69, and accumulates the output signal in the buffer 70. The variance obtained at the input terminal 69 is transmitted from the encoder via the multiplexing circuit 5, the transmission path 12, and the demultiplexing circuit 13 in FIG. The buffer 70 sequentially transmits the N decoded sample values via the output terminal 71 to the output terminal 18 of FIG.

(Problems to be Solved by the Invention) The number of blocks N is determined by the linear conversion circuit 3 and the linear inverse conversion circuit 16.
The larger the N, the higher the resolution and the smaller the error due to encoding / decoding. On the other hand, a large N does not always give a small error to an unsteady signal. This is because the same processing is performed on input samples in the same block, but if the block is long, the characteristics of the non-stationary signal may change in the same block. Therefore, it is better to perform encoding that follows a change in the properties of the input signal with a small block length N for a signal having a strong non-stationary property.
On the other hand, as the block length N increases, the encoding delay time increases, and a short block length is desirable for applications where immediacy is more important than error due to encoding and decoding, such as communication. In the conventional ATC, since the block length N was fixed,
The conflicting demands of following the resolution and the change of the properties of the input signal could not be met. Furthermore, it was not possible to cope with both the application that emphasizes the encoding delay and the application that emphasizes the encoding / decoding error.

An object of the present invention is to satisfy the conflicting requirements of resolution and tracking of changes in the properties of an input signal when an error due to encoding / decoding is more important than the delay time, and when the encoding delay time is important. An object of the present invention is to provide a method and apparatus for adaptive transform coding, which can perform coding with a short block length and minimize coding delay.

(Means for Solving the Problems) According to the present invention, when a block length is designated, encoding is performed with the designated block length, otherwise, encoding is performed independently with a plurality of block lengths. And independently store the encoded signal and the accompanying information, respectively, and simultaneously decode the encoded signal independently with a block length corresponding to the encoding, using the decoded signal and the input signal. A plurality of errors corresponding to the respective block lengths, and comparing the plurality of errors to determine an optimal block length that gives a minimum error, and determining the stored encoded signal corresponding to the optimal block length and the associated And transmitting / accumulating the information together with the optimum block length.

Also, the present invention performs encoding with the specified block length when the block length is specified, and otherwise stores the input signal samples in the buffer, and sets a set of predetermined predetermined lengths. The encoding device performs encoding with the minimum number of the blocks as the block length, further performs decoding on the encoded output, and obtains an error using the obtained decoded output and the input signal sample to obtain a storage device. And the above operation is performed in order from the smallest number for all of the set of predetermined numbers using time division multiplexing of the encoder and the decoder, and the value stored in the storage device is stored. And determining an optimal block length that gives the minimum error among the set of predetermined numbers, selecting the coded signal corresponding to the optimal block length and associated information, Transmission / storage with block length Characterized in that it.

Also, the present invention performs encoding with the specified block length when the block length is specified, and otherwise stores the input signal samples in the buffer, and sets a set of predetermined predetermined lengths. Perform encoding including at least linear transformation and quantization with the minimum number of numbers as the block length,
Further, performing a linear inverse transformation on the linear transformation output,
An error is obtained by using the output obtained by the linear inverse transformation and the input signal sample and stored in a storage device, and the above operation is performed by using the encoder and the decoder in a time-division multiplex manner. Are performed in ascending order from the smallest number to all of the predetermined numbers, comparing the values stored in the storage device, and determining the optimum block length that gives the minimum error among the set of predetermined numbers. Is determined, the coded signal corresponding to the optimal block length and associated information are selected, and transmitted / stored together with the optimal block length.

The present invention also provides a plurality of encoders for independently encoding with a plurality of block lengths, a storage device for independently storing encoded signals and associated information, and a method for simultaneously encoding with the encoder. A plurality of decoders for independently decoding the coded signal with a block length corresponding to the encoding, and a plurality of decoders corresponding to the respective block lengths using the signal decoded by the decoder and the input signal. An error calculation circuit that determines the error of the error, an error comparison circuit that determines the optimal block length that gives the minimum error by comparing the plurality of errors, and the encoded signal corresponding to the optimal block length and the accompanying information A first selector for selecting from the storage device, a first multiplexing circuit for multiplexing the selected coded signal and accompanying information and the optimal block length, and outputs of the plurality of encoders as inputs , Block A second selector controlled by a designation signal designating a length, a second multiplexing circuit for multiplexing the output of the second selector and the designation signal, and an output of the first and second multiplexing circuits , And at least a third selector for transmitting / accumulating the data by switching with the designation signal.

The present invention also provides a buffer for storing input samples,
A clock generator for generating a plurality of clocks for controlling the read timing of the buffer; and a plurality of clocks supplied from the clock generator are selected and supplied to the buffer according to a designation signal designating a block length. A fourth selector to perform encoding, and an encoder that performs encoding using a minimum number of a set of predetermined numbers as a block length;
A decoder that decodes an encoded output, an error calculation circuit that obtains an error by using an output of the decoder and the input signal sample, a storage device that stores the error, and a storage device that stores the error. An error comparison circuit that compares the calculated values and outputs a number that gives the smallest error among the set of predetermined numbers as an optimum block length, and corresponds to all of the set of predetermined numbers. A selection and multiplexing circuit for receiving and storing the coded signal and the accompanying information in order, selecting and multiplexing according to the optimal block length, and transmitting / accumulating the signal is provided.

The present invention also provides a buffer for storing input samples,
A clock generator for generating a plurality of clocks for controlling the read timing of the buffer; and a plurality of clocks supplied from the clock generator are selected and supplied to the buffer according to a designation signal designating a block length. A fourth selector for performing encoding including at least linear transformation and quantization using a minimum number of a set of predetermined numbers as a block length, and performing a linear inverse transformation on the linear transformation output A linear inverse transform circuit, an error calculating circuit for obtaining an error using the output of the linear inverse transform circuit and the input signal sample, a storage device for storing the error, and comparing the values stored in the storage device. An error comparison circuit that outputs a number that gives the smallest error among the set of predetermined numbers as an optimal block length, and that corresponds to all of the set of predetermined numbers. Storing Goka signal and associated information received in order, characterized by comprising a selection and multiplexing circuit for transmitting / storing select and multiplexing according to the optimum block length.

(Operation) The method and apparatus for adaptive transform coding according to the present invention are provided with a changeover switch, and when the error due to coding and decoding is more important than the delay time, the block length N is made variable and the resolution and the characteristics of the input signal are changed When the conflicting requirement of following changes is satisfied and the encoding delay time is important, the switch is switched to perform encoding with a specified short block length to minimize the encoding delay.

Embodiment Next, the present invention will be described in detail with reference to the drawings.
FIG. 1 is a block diagram showing one embodiment of the present invention.
The input signal samples obtained at the input terminal 1 are simultaneously supplied to n encoders 100 ₁ , 100 ₂ ... 100 _n (n is an integer). Different encoders have different block lengths
Encoding is performed using N ₁ , N ₂ ,... N _n , and auxiliary information such as encoding output and bit allocation is supplied to the storage device 101 and stored independently. On the other hand, the encoded output is simultaneously supplied to _n decoders 102 ₁ , 102 ₂ ... 102 _n . Each decoder performs decoding using the block lengths N ₁ , N ₂ ,..., N _n used in the encoding, and the decoded output is transmitted to the error calculation circuit 103. Error calculation circuit 103
At the block length N _1, N ₂ using an input signal supplied from the n decoder 102 _1, 102 ₂ ...... decoded signal supplied from 102 _n and the input terminal 1, the ...... N _n The errors s _d (N ₁ ), s _d (N ₂ )... S _d (N _n ) due to the corresponding encoding / decoding are calculated. The calculation of the error s _d can be performed, for example, using the signal s _i before encoding and the signal s _q after decoding, according to the following equation.

s _d = s _q ² / (s _i ² −s _q ² ) (2) where N ₁ <N ₂ ... <N _n and usually 2N _i = N _{i + 1} (1 ≦ i <
n). When the calculation of the errors for the block lengths N ₁ , N ₂ ,..., N _n has all been completed, s _d (N ₁ ), s _d (N ₂ ) _,.
(N _n ) is supplied to the error comparison circuit 104 at the same time, the optimum block length N _m giving the minimum error s _d min is detected, and supplied to the selector 105 and the multiplexing circuit 106. N _m may be transmitted to the multiplexing circuit 106 after being quantized. The selector 105, using the optimal block length N _m transmitted from the error comparison circuit 104, which corresponds to the encoded output and the bit auxiliary information allocation related such as selected from the memory device 101, supplied to the multiplexing circuit 106 I do. The multiplexing circuit 106 multiplexes the optimum block length N _m , the coded output corresponding thereto and auxiliary information such as bit allocation related information, and supplies the multiplexed information to the selector 111.

On the other hand, the outputs of the _n encoders 100 ₁ , 100 ₂ ... 100 _n are also supplied to the selector 109 at the same time. Selector 109
Selects _{one of} the encoders 100 ₁ , 100 _2, ..., 100 _n in response to a designation signal for designating the block length supplied to the input terminal 108, and transmits it to the multiplexing circuit 110. The designation signal is also supplied to the multiplexing circuit 110, and the selector 109
Are multiplexed with the designation signal and supplied to the selector 111. The selector 111 controls the multiplexing circuit 1 according to the designated signal.
One of the output 10 and the multiplexing circuit 106 is selected and sent out via the output terminal 107 for transmission / storage. Input terminal 108
When the designated signal is supplied to the selector 11
1 selects the output of the multiplexing circuit 110 and the output of the multiplexing circuit 106 when the designation signal is not supplied to the input terminal 108. That is, when the designated signal is supplied to the input terminal 108, a signal encoded with the designated block length is transmitted / received instead of the signal encoded with the optimal block length.
Will be accumulated.

The n encoders 100 ₁ , 100 ₂ ... 100 _n shown in FIG.
There is no limitation on the configuration of the _n decoders 102 ₁ , 102 ₂ ... 102 _n , and any configuration of encoder / decoder can be used. For example, the conventional encoder / decoder shown in FIGS. 6 and 8 can be used.

Next, another embodiment of the present invention will be described in detail. FIG. 2 is a block diagram showing one embodiment of the present invention. In FIG. 2, in FIG. 2, encoding is performed for a plurality of block lengths using the encoder 201 by time division multiplexing, and the encoding / decoding error for each encoded signal is calculated. The point is that an encoded signal giving the minimum error is selected and transmitted to the transmission path. Along with this, the decoder 203, the error calculation circuit 205, the storage device 206 for storing errors for a plurality of block lengths in the encoder, and the error comparison for determining the optimal block length that gives the minimum error circuit
207 is added, a coded signal corresponding to each block length and associated information on bit allocation are stored, and a value corresponding to the optimum block length is selected therefrom and multiplexed with the optimum block length. At 202, the multiplexing circuit 5 has been replaced.

Next, the operation of the embodiment shown in FIG. 2 will be described. In the encoder, the signal supplied to the input terminal 1 is stored in a buffer 200.
, And is encoded by the encoder 201.
The output of the encoder 201 is supplied to a decoder 203 for decoding. The output of the decoder 203 is
Supplied to That is, the encoder 201 and the decoder 203 decode the encoded signal, and reproduce the signal obtained by the decoder on the receiving / reproducing side by the encoder. On the other hand, the output of the buffer 200, that is, the signal before encoding is also supplied to the error calculation circuit 203. Error calculation circuit
In 203, an error is calculated using the signal before encoding and the signal after decoding. The calculation of the error s _d can be performed, for example, using the signal s _i before encoding and the signal s _q after decoding, according to the following equation.

s _d = s _q ² / (s _i ² −s _q ² ) (2) With the above processing, the calculation of the error s _d (N ₁ ) for the block length N ₁ is completed, and s _d (N ₁ ) Are stored in the storage device 206. Next, the second block length N ₂ stored in the buffer 200
Samples equal to (N ₁ <N ₂ ) are encoded by encoder 201. Thereafter, s _d (N ₂ ) is calculated in the same manner as in the case of N ₁ . s _d (N ₂ ) is stored in the storage device 206. In the same manner as in the case of N ₁ and N ₂ described above,
N _3, N _4, for the case of ...... N _n of error s _d (N _3),
d (N ₄ )... s _d (N _n ) is calculated and stored in the storage device 206. However, N ₁ <N ₂ <N ₃ <N ₄ ... <N _n , usually 2N _i = N _{i + 1}
And

When the calculation of the errors for the block lengths N ₁ , N ₂ , N ₃ , N ₄ ,..., N _n has all been completed, s _d (N ₁ ), s _d (N ₂ ), s
_d (N ₃ ), s _d (N ₄ ) ... s _d (N _n ) are the error comparison circuit 2
Is supplied to the 07, the optimum block length N _m giving the minimum error s _d min is detected, is supplied to the selected and multiplexing circuit 202. N
_m may be transmitted to the selection / multiplexing circuit 202 after being quantized. On the other hand, the output of the encoder 201 and the output of bit allocation information corresponding to each block length are accumulated in the selection / multiplexing circuit 202, and a value corresponding to the optimum block length supplied later is selected. Are multiplexed with the optimum block length and transmitted to the transmission path 12.

The input terminal 210 and the clock generation circuit 20 are used to perform encoding with one designated block length instead of the optimum block length.
8. A selector 209 is provided. Clock generation circuit 20
8 generates a clock for controlling the buffer 200 corresponding to a plurality of block lengths. The selector 209 selects a clock corresponding to the block length specified at the input terminal 210 from these clocks, and supplies it to the buffer 200 and the selection / multiplexing circuit 202. When performing encoding on a plurality of block lengths by time division multiplexing and determining the optimal block length, the selector 209 sequentially switches clocks corresponding to the block lengths and supplies the clocks to the buffer 200.

FIGS. 3A and 3B show examples of the configuration of the selection / multiplexing circuit 202. FIG. In the example of FIG. 3A, the input terminal 21 has an optimum block length, and the input terminal 22 has an eighth block length corresponding to each block length.
The output of the quantizer 4 is supplied to the input terminal 23, the output of the bit distribution circuit 6 corresponding to each block length is supplied to the input terminal 23, and the variance value of the input sample corresponding to each block length is supplied to the input terminal 24. The multiplexing circuit 25 multiplexes the three types of input signals corresponding to each block length, that is, the output of the quantizer 4, the output of the bit allocation circuit 6, and the variance of the input samples, and then switches the switch 37 and the storage device 26 Is stored. The output of the quantizer 4 corresponding to the optimum block length supplied to the input terminal 21, the output of the bit allocation circuit 6, and the variance value of the input sample are selected by the selector 27, and are passed through the selector 38 to the multiplexing circuit 28.
Is transmitted to In the multiplexing circuit 28, the multiplexed signal supplied from the selector 27 is further multiplexed with the optimum block length, and the multiplexed signal is transmitted to the transmission line 12 in FIG.

On the other hand, in an application in which encoding delay is emphasized, a designation signal is supplied to the input terminal 39. By this designation signal,
The switch 37 and the selector 38 are controlled, and the output of the multiplexing circuit 25 is directly supplied to the multiplexing circuit 28 without passing through the storage device 26 and the selector 27. Therefore, when the designation signal is supplied to the input terminal 39, the signals supplied to the input terminals 22, 23 and 24 are multiplexed and supplied directly to the selector 38. As the designation signal of the input terminal 39, a clock from the selector 209 in FIG. 2, that is, a clock corresponding to the block length designated by the input terminal 210 is supplied. Since this clock is the same as the control clock of the buffer 200, the buffer 200
The switch 37 and the selector 38 are controlled in accordance with the block length used in.

In the example of FIG. 3B, three types of input signals corresponding to each block length, that is, the output of the quantizer 4, the output of the bit allocation circuit 6, and the variance of the input samples are independent without being multiplexed. The storage devices 30, 31, and 32 and the switches 50, 51, and 52 are supplied. These three types of input signals are supplied to selectors 33 and 3
In steps 4 and 35, a value corresponding to the optimum block length supplied to the input terminal 21 is selected, and selectors 53, 54 and 55 are selected.
After that, the data is multiplexed by the multiplexing circuit 36 together with the optimum block length. The multiplexed signal is transmitted through an output terminal 29 to the transmission line shown in FIG.
Sent to 12. In the case of an application in which encoding delay is emphasized, a designation signal is supplied to the input terminal 39. The following operation is as described with reference to FIG. Switch 37
Are switches 50, 51, 52, and selector 38 is selectors 53, 5
4 and 55 respectively. Next, the operation of the buffer 200 in FIG. 2 will be described with reference to FIG. 4 by taking as an example a case where the optimum block length is determined from a plurality of block lengths.

It is assumed that time t = 0 when the encoder starts operating.
At time N ₁ T (T is a sampling period), N ₁ input signal samples are accumulated in the buffer 200. This situation is shown in FIG. Performs calculation of coding and error s _d (N ₁₎ for the block length _{N 1, s d (N 1} ) is stored in the storage device. At time N ₂ T, samples equal to the second block length N ₂ (N ₁ <N ₂ ) are accumulated in the buffer 200.
This is shown in FIG. 4 (b). Thereafter, encoding is performed, and s _d (N ₂ ) is calculated in the same manner as in the case of N ₁ and stored in the storage device. The buffer 200 becomes as shown in FIG. 4C at the time N ₃ T, and the error s _d (N ₃ ) is calculated in the same manner as in the case of N ₁ and N ₂ . Now, assuming that n = 3 (the optimal block length is selected from three types of block lengths) as shown in FIG. 4, when the calculation of the error s _d (N ₃ ) is completed, The block length is determined. Ideal if the block length was N ₁ is, N ₁ samples from old among the stored sample values in the buffer 200 are discarded, as shown in FIG. 4 (d) (N ₃ -N ₁ ) Samples remain in the buffer. Subsequently using the first N ₁ samples in the buffer 200 (the portion indicated by FIG. 4 (d) Medium I), the error calculation to select the next best block length is initiated. At the time the error calculation has been completed for N _1, assuming that required ΔNT seconds error calculation, the buffer 20
The sample stored in 0 is as shown in FIG. 4 (e). Then using the first N ₂ samples in the buffer 200 (FIG. 4 (e) moieties represented by the medium I and II), error calculation corresponding to N ₂ takes place. Hereinafter similarly calculates the error corresponding to N _3, 2-th optimum block length is determined. On the other hand, if the first optimal block length is N ₂ , the oldest one of the sample values stored in the buffer 200 becomes N ₂
Samples are discarded, as shown in FIG. 4 _{(f) (N 3 -N 2} ) samples remain in the buffer. Subsequently using the first N ₁ samples in the buffer 200 (the portion indicated by FIG. 4 (f) Medium I), the error calculation to select the next best block length is initiated. At the time the error calculation has been completed for N _1, assuming that required ΔNT seconds error calculation, samples stored in the buffer 200 is as shown in FIG. 4 (g). Then the first N in buffer 200
An error calculation corresponding to N ₂ is performed using _two samples (portions indicated by I and II in FIG. 4 (g)). Hereinafter similarly calculates the error corresponding to N _3, 2-th optimum block length is determined. By the above processing, different block lengths are applied to the input signal samples for each block. FIG. 4H shows an example of the selected optimum block length.

FIG. 5 shows another embodiment of the present invention. The difference between FIG. 5 and FIG. 2 is that an encoder and a linear inverse transform circuit 204 are used instead of the encoder and decoder of FIG. As a result, instead of decoding the encoded signal and comparing it with the input signal to obtain an error, instead of taking out the signal immediately after the linear conversion by the encoder and performing linear inverse conversion, the error with respect to the input signal is obtained. . The purpose of the error calculation is to investigate the effect of the block length, and the effect of the error due to the block length is dominant on the linear transformation in the encoder. Therefore, in the embodiment shown in FIG. 5, the same effect as that of FIG. 2 is obtained, and the circuit is simpler than that of FIG.

The configurations of the encoder and the decoder in the embodiment of FIGS. 2 and 5 are not limited, and any configuration of the encoder / decoder can be used. For example, as in the case of FIG. 1, the conventional encoder / decoder shown in FIGS. 6 and 8 can be used.

(Effects of the Invention) As described in detail above, according to the present invention, when an error due to encoding / decoding is more important than a delay time, encoding / decoding for different block lengths is performed to compare the errors. In order to transmit the information by selecting the optimal block length to obtain the minimum error when decoding on the receiving side, and performing encoding using the optimal block length, changes in the resolution and properties of the input signal In the case where the conflicting requirement of following is satisfied and the encoding delay time is important, encoding can be performed with a specified short block length to minimize the encoding delay.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, FIG. 2 is a block diagram showing another embodiment of the present invention, and FIG. 3 is a block diagram showing details of a selecting / multiplexing circuit in FIG. FIG. 4, FIG. 4 is a diagram showing an example of the state of a buffer for storing input samples, FIG. 5 is a block diagram showing another embodiment of the present invention, FIG. 6 is a block diagram showing a conventional example, FIG. Is a diagram showing details of the bit distribution circuit I and the bit distribution circuit II in FIG. 6, FIG. 8 is a diagram showing another conventional example, and FIG. 9 is a detail of the normalization circuit and the denormalization circuit in FIG. FIG. In the figure, 1, 108 and 210 are input terminals, 100 ₁ , 100 ₂ ...
100 _n is an encoder, 101 and 205 are storage devices, 102 ₁ , 102 ₂ ......
102 _n is a decoder, 103 and 205 are error calculation circuits, 104 and 207 are error comparison circuits, 105, 109, 111 and 209 are selectors, 106 and 1
10 is a multiplexing circuit, 107 is an output terminal, 200 is a buffer, 201
Is an encoder, 202 is a selection / multiplexing circuit, 203 is a decoder,
204 denotes a linear inverse conversion circuit, 208 denotes a clock generation circuit, and 12 denotes a transmission path.

──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-55-57900 (JP, A) JP-A-59-94797 (JP, A) JP-A-61-112433 (JP, A) JP-A-62 224122 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G10L 19/00-19/14 H03M 3/00-11/00 H04B 14/00-14/08 JICST file (JOIS )

Claims (28)

(57) [Claims] When an input signal is adaptively transformed and encoded in order to compress and transmit / store the information amount of the input signal, if the block length is designated, the code is encoded by the designated block length. Is performed, otherwise, independently coded with a plurality of block lengths, the coded signal and the accompanying information are stored independently, and the coded signal is simultaneously stored in the block corresponding to the coding. Independently decoding with a length, a plurality of errors corresponding to each block length are obtained using the decoded signal and the input signal, and the plurality of errors are compared to determine an optimal block length that gives a minimum error. Deciding, selecting the stored coded signal and associated information corresponding to the optimal block length, and transmitting / accumulating the signal together with the optimal block length. 2. An adaptive transform coding of an input signal for compressing and transmitting / accumulating an information amount of the input signal, and when a block length is designated, the code is encoded by the designated block length. Otherwise, the input signal samples are stored in a buffer, the minimum number of a set of predetermined numbers is encoded as a block length, and the encoded output is further encoded. Decoding is performed, an error is obtained by using the obtained decoded output and the input signal sample, and an error is obtained and stored in a storage device. The above operation is performed by time-division using an encoder and a decoder. Performing in order from the smallest number to all of the predetermined number of sets, comparing the values stored in the storage device, and selecting the optimal block length that gives the minimum error among the predetermined number of sets. Is determined, and the code corresponding to the optimum block length is determined. A method of adaptive transform coding, characterized in that a coded signal and associated information are selected and transmitted / stored together with the optimal block length. 3. An adaptive transform coding of an input signal for compressing and transmitting / accumulating an information amount of the input signal, if a block length is designated, the code is encoded by the designated block length. Otherwise, store the input signal samples in a buffer and perform encoding including at least linear transformation and quantization with the minimum number of the set of predetermined numbers as the block length. Further, a linear inverse transform is performed on the linear transform output, an error is obtained using the output obtained by the linear inverse transform and the input signal sample, and the obtained error is stored in a storage device. And a decoder are used in a time-division manner in order from the smallest number to all of the set of predetermined numbers, comparing the values stored in the storage device, and comparing the set of predetermined numbers. The optimal block that gives the least error among the numbers A method for adaptive transform coding, comprising determining a lock length, selecting the coded signal corresponding to the optimum block length and accompanying information, and transmitting / storing the coded signal and the optimum information together with the optimum block length. 4. When encoding, an input signal is subjected to a linear transformation to obtain a transform coefficient, a bit allocation is determined using the transform coefficient, and the transform coefficient is quantized according to the bit allocation. 4. The adaptive transform coding method according to claim 1, wherein the quantized transform coefficient and the transform coefficient used for the bit allocation are multiplexed and transmitted / stored. 5. The method according to claim 4, wherein the input signal is temporarily stored in a buffer and then subjected to linear conversion. 6. A method for calculating the variance of a sample in a buffer during encoding, normalizing the sample for which the variance has been calculated with the variance value, and selecting and multiplexing the variance value corresponding to the optimal block length. 5. The method of adaptive transform coding according to claim 4, wherein the method comprises transmitting / accumulating. 7. At the time of encoding, a square value of a transform coefficient is divided into a plurality of groups, thinning is performed by setting an average value of the square values of each group as a representative value, and interpolation is performed to perform interpolation. The method according to claim 1, wherein the same number of sample values are approximately reproduced, bit allocation is determined using the interpolated values, and the thinned values corresponding to an optimum block length are selected / multiplexed and transmitted / stored. 7. The method for adaptive transform coding according to 4, 5, or 6. 8. A bit allocation is determined so as to minimize a square error when a transform coefficient is quantized during encoding.
A method for adaptive transform coding according to claim 4, 5, 6, or 7. 9. The adaptive transform encoding method according to claim 4, wherein, at the time of encoding, the associated information is quantized, multiplexed, and transmitted / stored. 10. At the time of decoding, an encoded signal is separated into quantized transform coefficients and transform coefficients used for bit allocation, and bit allocation is determined using the transform coefficients used for the bit allocation. 10. The adaptive transform coding method according to claim 8, wherein the quantized transform coefficient is inversely quantized according to the bit allocation, and the inversely quantized result is subjected to a linear inverse transform. . 11. The adaptive transform coding method according to claim 10, wherein upon decoding, the data is subjected to a linear inverse transform, stored in a buffer, and output one sample at a time. 12. The adaptive transform coding according to claim 11, wherein at the time of decoding, a variance value of a transform coefficient is separated from the coded signal, and an output sample is denormalized with the variance value. Method. 13. A decoding method, wherein bit allocation is determined using a square value of a thinned-out transform coefficient, and inverse quantization of the quantized transform coefficient is performed according to the bit allocation. 13. The method of adaptive transform coding according to claim 10, 11 or 12, which performs the adaptive transform coding. 14. The decoding method according to claim 10, wherein, at the time of decoding, inverse quantization of the quantized transform coefficient is performed by using a bit allocation that minimizes a quantization square error of the transform coefficient.
14. The method for adaptive transform coding according to 11, 12, or 13. 15. The adaptive transform according to claim 10, wherein, at the time of decoding, the accompanying information is separated from the coded signal and dequantized before use. The encoding method. 16. An adaptive transform encoding method for an input signal, wherein a plurality of encoders for independently encoding with a plurality of block lengths, and an encoded signal and associated information are stored independently. A storage device, and a plurality of decoders for simultaneously decoding the signals coded by the coder independently with a corresponding block length, respectively using the signal decoded by the decoder and the input signal An error calculation circuit for obtaining a plurality of errors corresponding to the block lengths of the above, an error comparison circuit for comparing the plurality of errors to determine an optimum block length that gives a minimum error, and the encoding corresponding to the optimum block length A first selector for selecting a signal and accompanying information from the storage means, a first multiplexing circuit for multiplexing the selected coded signal and accompanying information and the optimum block length, and the plurality of codes; Chemist A second selector that receives an output as an input and is controlled by a designation signal that designates a block length, a second multiplexing circuit that multiplexes the output of the second selector and the designation signal, An adaptive transform coding apparatus comprising at least a third selector for transmitting / accumulating the output of the multiplexing circuit by switching the output of the multiplexing circuit with the designated signal. 17. A buffer for accumulating input samples when adaptively transforming and encoding an input signal, a clock generator for generating a plurality of clocks for controlling read timing of the buffer, and A fourth selector for selecting a plurality of clocks to be supplied according to a designation signal designating a block length and supplying the selected clock to the buffer;
An encoder for encoding an input signal given as a block length in order from the smallest number of a set of predetermined numbers, a decoder for decoding an encoded output, An error calculation circuit for obtaining an error by using an output and the input signal sample; a storage device for storing the error; and comparing the values stored in the storage device with the given number of the set to obtain an optimal block. An error comparison circuit for outputting as a length;
A selection / multiplexing circuit for sequentially receiving and storing the coded signals corresponding to all the given numbers of the set and the associated information, and selecting / multiplexing and transmitting / accumulating them according to the optimum block length. Adaptive transform coding device. 18. A buffer for accumulating input samples when adaptively transforming and encoding an input signal, a clock generator for generating a plurality of clocks for controlling read timing of the buffer, and A fourth selector for selecting a plurality of clocks to be supplied according to a designation signal designating a block length and supplying the selected clock to the buffer;
An encoder that performs encoding including at least linear transformation and quantization on an input signal given as a block length in order from the smallest number of a set of predetermined numbers, and performs linear inverse transformation on the linear transformation output A linear inverse transform circuit, an error calculating circuit for obtaining an error using the output of the linear inverse transform circuit and the input signal sample, a storage device for storing the error, and comparing the values stored in the storage device. An error comparison circuit that outputs the set of given numbers as an optimal block length, and sequentially receives and stores encoded signals and associated information corresponding to all the set of given numbers, and stores the optimal block length. And a selecting / multiplexing circuit for selecting / multiplexing and transmitting / accumulating according to the following. 19. An encoder includes: a linear conversion circuit that performs a linear conversion on an input signal to obtain a conversion coefficient; a bit allocation circuit that determines a bit allocation using the conversion coefficient; And a multiplexing circuit for multiplexing and transmitting / accumulating an optimum block length giving a minimum error, a quantized transform coefficient, and a transform coefficient used for bit allocation. 16. The adaptive conversion encoding device according to 16, 17, or 18. 20. The adaptive transform coding apparatus according to claim 19, wherein the encoder has a buffer for temporarily storing the input signal in the buffer and then performing a linear conversion. 21. An encoder has a normalization circuit for calculating a variance of a sample in a buffer, and normalizing the sample with the variance value, and also stores a signal from the normalization circuit.
21. The adaptive transform coding apparatus according to claim 20, wherein the adaptive transform coding apparatus selects / multiplexes and transmits / stores. 22. An encoder for decimating a transform coefficient, dividing the group into a plurality of groups after squaring the transform coefficients, and decimating the average of the square values of each group as a representative value, and an output of the decimator. And a bit allocation circuit including a bit number optimization circuit that determines the bit allocation by using the interpolated value, and an interpolation circuit that approximately reproduces the same number of sample values as before the thinning by interpolating. 22. The adaptive transform coding apparatus according to claim 19, wherein the output of the thinning circuit is stored / selected / multiplexed and transmitted / stored. 23. An encoder includes a second quantizer for quantizing an optimum block length, a third quantizer for quantizing information used for bit allocation, and a quantizer for quantizing an output of a normalizing circuit. And a fourth quantizer for transforming.
5. The adaptive transform coding apparatus according to claim 1. 24. A decoder which receives a coded signal, separates a quantized transform coefficient, an optimum block length and a transform coefficient used for bit allocation, and a transform coefficient used for the bit allocation. A second bit allocation circuit that determines a bit allocation by using the first and second bit allocation circuits, and a first inverse quantizer that inversely quantizes the quantized transform coefficient output from the separation circuit according to the output of the second bit allocation circuit. 24. An adaptive transform according to claim 22, further comprising at least a second linear inverse transform circuit for performing a linear inverse transform on the output of the first inverse quantizer using the optimal block length. Encoding device. 25. The adaptive transform coding apparatus according to claim 24, wherein the decoder has a buffer for storing the output signal, and outputs the value stored in the buffer one sample at a time. 26. The decoder according to claim 17, further comprising a denormalization circuit for separating a variance value of a transform coefficient from the coded signal and denormalizing the output signal with the separated variance value.
26. The adaptive conversion encoding device according to 24 or 25. 27. A decoder, comprising: a second interpolator for interpolating a thinned signal; and a bit number optimizer for optimizing the number of bits using a value interpolated in the second interpolator. 27. The adaptive transform coding apparatus according to claim 24, further comprising a second bit allocation circuit comprising a circuit, and performing inverse quantization of the quantized transform coefficient according to the bit allocation. . 28. A decoder, comprising: a second inverse quantizer for inversely quantizing an optimal block length; a third inverse quantizer for inversely quantizing transform coefficients used for bit allocation; 28. The adaptive transform coding apparatus according to claim 24, further comprising: a fourth inverse quantizer for inversely quantizing a variance value used for quantization.