JP2780355B2 - Semiconductor integrated circuit device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and in particular, a large-scale circuit is divided into two blocks, integrated in two pellets, and conventionally used. The present invention relates to a semiconductor integrated circuit device configured to be housed in an assembly case.

[Prior art] Conventionally, a semiconductor integrated circuit device realizes a device in which all necessary functional elements are arranged on one main surface on the same pellet and these elements are connected by internal wiring to perform a desired operation. I let you. Hereinafter, taking a semiconductor memory device as an example,
As shown in FIG. 3, a cell array circuit 33 including a memory cell, a row decoder, a column decoder and a sense amplifier, an input / output signal processing circuit 37, control circuits 32 and 36, and a bonding pad 31 are arranged on a semiconductor pellet 30. Thus, the intended semiconductor memory device is configured.

[Problem to be Solved by the Invention] In the above-described conventional semiconductor device, as shown in FIG. 3, the cell array circuit 33 occupies most of the area in the center of the pellet, and the control circuits 32, 36 In addition, the input / output signal processing circuit 37 is often arranged separately on the short side of the rectangular pellet. Such an arrangement is due to restrictions for being able to be enclosed in a standardized assembly case. A signal line for interconnecting the control circuits 32 and 36 and the input / output signal processing circuit 37 and a power supply line for supplying power to the entire pellet are mainly bus lines 34 provided on the long side of the pellet.
And pass inside 35. Therefore, these wirings must be thin and long and have a narrow interval, and these wirings have large parasitic capacitance and resistance. Therefore, in the conventional semiconductor integrated circuit device, noise levels increase due to interference between signal lines or between signal lines and power supply lines, and signal delays increase.

Further, in the conventional device, since the memory cell array and the peripheral circuit are formed on the same substrate, the substrate current generated by the operation of the peripheral control circuit may reach the memory cell. Sometimes destroyed.

[Means for Solving the Problems] In a semiconductor integrated circuit device according to the present invention, a circuit that performs a certain function is divided into two blocks, and each circuit is integrated into a separate semiconductor pellet, and the two semiconductor pellets are integrated into the same semiconductor pellet. Are bonded so that the surfaces on which the circuits are formed face each other. The pads on each pellet include those connected to external leads and those connected only to pads of other opposing pellets.

Example Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 (a) is a plan view of two semiconductor pellets in which a circuit is formed so that one function can be integrally performed.

In the first semiconductor pellet 10, a cell array circuit 12 including a row decoder, a column decoder, and a sense amplifier is formed. In the second semiconductor pellet 11, a control circuit 13 and an input / output signal processing circuit 14 are formed. I have. Around each semiconductor pellet, there are formed an internal connection pad 15 connected only to a pad of the other semiconductor pellet and an external input / output pad 16 connected to an external input / output pin of a lead frame. These pads 15 and 16 are arranged so as to be line-symmetric when the first and second pellets are arranged side by side as shown in FIG. Also, the first pellet
Of the 10 external input / output pads 16, data input / output pins,
The pad 16 to which the control signal input pin and the like are connected is
It is not connected to the internal circuit (cell array circuit 12),
This pad only serves to fix the pellet.

FIG. 1 (b) is a cross-sectional view showing one embodiment of the present invention, and FIG. 1 (c) is a plan view in which the sealing resin is not shown.

The first semiconductor pellet 10 is bonded to the lead frame 18 with its main surface 10a facing down by bumps 17 formed on the pads 15 and 16, and the second semiconductor pellet 11 has its main surface 11a facing up. Then, it is bonded to the same lead frame 18 by the same means as the first semiconductor pellet 10. After the bonding is completed, it is sealed with the sealing resin 19, and the leads are cut and molded to complete the integrated circuit device.

External input / output pins 18a and internal connection stitches 18b are formed on the lead frame 18, and are connected to the external input / output pads 16 and the internal connection pads 15, respectively. By this bonding, an electrical connection between the pellets 10 and 11 is achieved. That is, the second signal of the data signal from the first semiconductor pellet 10 is transmitted through the internal connection stitch 18b.
Of the second pellet 11
Can be transmitted to the first pellet. After the resin is sealed, the internal connection stitch 18b is cut at the sealing resin outline shown by the broken line in FIG. 1 (c). To facilitate this cutting, the lead frame is thinned at this portion. ing.

By arranging the two pellets in this manner, it is not necessary to provide a long bus line along the long side of the pellet as in the conventional example, and the power supply line and the GND line can be arranged at optimal positions. In addition, since the signal line can be shortened, noise is hardly picked up, and signal transmission delay is reduced. Further, by arranging a circuit in which a substrate current easily occurs on the second pellet side, adverse effects on the memory cell can be prevented.

In the above embodiment, the semiconductor pellets 10 and 11 are bonded to the lead frame 18 using bumps. However, the present invention is not limited to this, and other suitable semiconductors used for normal face-down bonding may be used. It can be changed to a simple bonding method. Although the bonding of the two pellets may be performed separately, it is preferable to perform the bonding simultaneously in order to equalize the manner of applying a force to the lead frame and from the viewpoint of work efficiency.

FIG. 2A is a cross-sectional view showing another embodiment of the present invention, FIG. 2B is a plan view in which the sealing resin is not shown, and FIG. It is the XY sectional view taken on the line.
In this embodiment, an insulating plate 21 is sandwiched between a first semiconductor pellet 10 and a second semiconductor pellet 11, and both pellets are bonded and fixed with an adhesive 22. The thickness of the insulating plate 21 is approximately the sum of the thickness of the lead frame 18 and the height of two bumps. In the insulating plate 21, a relief for connecting an external input / output pin or an internal connection stitch to each pellet is formed. Further, a lug 21a is formed outside the insulating plate 21 in accordance with the outer shape of the pellet, and the pellet can be positioned in accordance with the lug 21a. Insulating plate 21 and each pellet
It is desirable that the bonding with the 10 and 11 and the bonding of each pellet to the lead frame be performed simultaneously.

According to this embodiment, positioning between the pellet and the lead frame and bonding of the pellet are facilitated.

[Effects of the Invention] As described above, the present invention divides functions to be integrated into one integrated circuit device into two, and builds each function into separate pellets, and connects both pellets to the same lead frame. According to the present invention, the signal lines and the power supply lines can be shortly separated from each other and arranged at the optimum positions without changing the conventional package structure, since they are bonded with the circuit surfaces facing each other. it can. Therefore, according to the present invention, it is possible to reduce the parasitic capacitance and resistance of the wiring, and it is possible to prevent operation delay, malfunction due to internal fluctuation of the power supply voltage, and deterioration of the operation margin. Further, according to the present invention, the influence of the substrate current generated by the operation of the circuit on other circuits can be reduced, and the operation can be stabilized. Further, there is also a side effect that an optimum process can be selected for manufacturing the first pellet and the second pellet.

[Brief description of the drawings]

FIG. 1A is a plan view of a semiconductor pellet used in an embodiment of the present invention, FIG. 1B is a cross-sectional view showing an embodiment of the present invention, and FIG. FIG. 2 (a) is a cross-sectional view showing another embodiment of the present invention, in which the sealing resin is omitted, FIG. 2 (b) is a plan view in which the sealing resin is not shown, and FIG. 2 (c) is a sectional view taken along the line XY of FIG. 2 (b), and FIG. 3 is a plan view of a semiconductor pellet used in a conventional example. 10: First semiconductor pellet, 10a: Main surface of first semiconductor pellet, 11: Second semiconductor pellet, 11a ...
... Main surface of the second semiconductor pellet, 12 ... Cell array circuit, 13 ... Control circuit, 14 ... I / O signal processing circuit, 15 ... Pad for internal connection, 16 ... Pad for external I / O, 17 ... ... Bump, 18 ... Lead frame, 18a ... Pin for external I / O, 18b ... Stitch for internal connection, 19 ...
Sealing resin, 19a …… Seal resin outline, 21 …… Insulating plate, 21a
... ears, 22 ... adhesive, 30 ... semiconductor chip, 31 ...
Bonding pad, 32, 36 ... Control circuit, 33
... cell array circuits, 34, 35 ... bus lines, 37 ... input / output circuits.

Claims (2)

(57) [Claims] A first semiconductor pellet on which a first portion of a circuit to perform a predetermined function is formed, and a pad for external lead connection and a pad for internal connection are formed on a main surface thereof; The remaining second portion of the circuit to perform a certain function is formed, and on its main surface, an external lead connection pad and an internal connection pad connected to the internal connection pad of the first semiconductor pellet are formed. The formed second semiconductor pellet and the external lead connection pad of the first semiconductor pellet are connected on the first main surface thereof, and the second semiconductor pellet is formed on the second main surface thereof. An external lead to which the external lead connection pad is connected; and an internal connection pad of the first semiconductor pellet connected to a first main surface thereof; Semiconductor pen Comprising Tsu said internal connection pads connected to internal connection stitch bets, a semiconductor integrated circuit device, wherein the certain function should play a circuit is characterized in that it is configured. 2. The circuit formation surface of the first semiconductor pellet and the circuit formation surface of the second semiconductor pellet are thicker than the external lead and the internal connection stitch in a region where the pad is not formed. 2. The semiconductor integrated circuit device according to claim 1, wherein said semiconductor integrated circuit device is bonded through a thick insulating plate.