JPH053138B2 - - Google Patents
Info
- Publication number
- JPH053138B2 JPH053138B2 JP59233206A JP23320684A JPH053138B2 JP H053138 B2 JPH053138 B2 JP H053138B2 JP 59233206 A JP59233206 A JP 59233206A JP 23320684 A JP23320684 A JP 23320684A JP H053138 B2 JPH053138 B2 JP H053138B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- circuit
- semiconductor chip
- mounting
- circuits
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/072—Connecting or disconnecting of bump connectors
- H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W72/251—Materials
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/541—Dispositions of bond wires
- H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/931—Shapes of bond pads
- H10W72/932—Plan-view shape, i.e. in top view
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
- H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
Landscapes
- Wire Bonding (AREA)
Description
【発明の詳細な説明】
[技術分野]
本発明は、半導体装置に係り、特に、種類の異
なる複数の半導体チツプを塔載した塔載用半導体
基板を有する半導体装置に適用して有効な技術に
関するものである。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a semiconductor device, and particularly relates to a technique that is effective when applied to a semiconductor device having a mounting semiconductor substrate on which a plurality of semiconductor chips of different types are mounted. It is something.
[背景技術]
高速度で外部素子又は外部装置の駆動能力が大
きく、かつ低消費電力の半導体装置を得るため
に、一つの半導体チツプにバイポーラ型半導体素
子又は回路と相補型半導体素子又は回路のような
異なる種類の半導体素子又は回路を複数個設けた
ものがある。(例えば、特願昭58−143859号を参
照)
前記バイポーラ型半導体素子又は回路は、例え
ば、高速度で外部素子又は外部装置への駆動能力
の大きいものが必要なレベル変換回路、入出力回
路、論理回路等に適用され、相補型半導体素子又
は回路は、多くの電力を消費する記憶回路等に適
用される。[Background Art] In order to obtain a semiconductor device with high speed, high driving capacity for external elements or external devices, and low power consumption, a bipolar semiconductor element or circuit and a complementary semiconductor element or circuit are integrated into one semiconductor chip. There are devices that have a plurality of different types of semiconductor elements or circuits. (See, for example, Japanese Patent Application No. 58-143859.) The bipolar semiconductor element or circuit is used, for example, in a level conversion circuit, an input/output circuit, which requires a high speed and large driving capacity for an external element or device, Complementary semiconductor devices or circuits are applied to logic circuits and the like, and complementary semiconductor elements or circuits are applied to memory circuits and the like that consume a lot of power.
しかしながら、本発明者は、かかる技術を検討
した結果、下記の問題点を見い出した。 However, as a result of studying this technology, the inventor found the following problems.
(1) 一つの半導体チツプ上の集積度が高くなると
歩留が低下する。(1) Yield decreases as the degree of integration on a single semiconductor chip increases.
(2) 一つの半導体チツプ上に高集積度でバイポー
ラ型半導体素子又は回路と相補型半導体素子又
は回路等の異なる種類の半導体素子又は回路を
作成するには、それぞれの異なる製造法で作成
しなければならないために、製造工程が複雑と
なる。(2) In order to create different types of semiconductor devices or circuits, such as bipolar semiconductor devices or circuits and complementary semiconductor devices or circuits, with a high degree of integration on one semiconductor chip, they must be created using different manufacturing methods. This complicates the manufacturing process.
(3) 高速・高駆動動作のバイポーラ型の入出力回
路およびレベル変換回路を用いてもその配置位
置によつて、外部装置に対する駆動力の向上が
図れず、半導体装置を有する回路系の動作速度
の向上を図ることができない。(3) Even if bipolar type input/output circuits and level conversion circuits with high-speed, high-drive operation are used, the driving force for external devices cannot be improved due to their placement positions, and the operating speed of circuit systems that include semiconductor devices is reduced. It is not possible to improve the situation.
[発明の目的]
本発明の目的は、多種の半導体素子又は回路を
含んだシステムの半導体装置が容易にできる技術
を提供することにある。[Object of the Invention] An object of the present invention is to provide a technology that allows easy fabrication of a semiconductor device for a system including various types of semiconductor elements or circuits.
本発明の他の目的は、種類の異なる複数の半導
体素子又は回路からなる高集積度の半導体装置に
おいて、その歩留を向上することが可能な技術を
提供することにある。 Another object of the present invention is to provide a technique that can improve the yield of a highly integrated semiconductor device comprising a plurality of semiconductor elements or circuits of different types.
本発明の他の目的は、半導体装置を有する回路
系の動作速度を向上させることのできる技術を提
供することにある。 Another object of the present invention is to provide a technique that can improve the operating speed of a circuit system including a semiconductor device.
本発明の前記ならびにその他の目的と新規な特
徴は、本明細書の記述及び添付図面によつて明ら
かになるであろう。 The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.
[発明の概要]
本願において開示される発明のうち、代表的な
ものの概要を簡単に説明すれば、下記のとおりで
ある。[Summary of the Invention] A brief overview of typical inventions disclosed in this application is as follows.
すなわち、種類の異なる複数の半導体素子又は
回路からなる高集積度の半導体装置において、配
線及び第1種類の半導体素子又は回路を半導体チ
ツプ塔載用半導体基板に形成し、前記配線と第2
種類の半導体素子又は回路を有する半導体チツプ
とを突起電極で接続し、前記配線と封止用基板に
設けられた外部装置接続用リードとボンデイング
ワイヤ又は突起電極で電気的に接続した構造にす
ることにより、多品種のシステムが容易にでき、
かつ該システムの歩留を向上したものである。 That is, in a highly integrated semiconductor device consisting of a plurality of semiconductor elements or circuits of different types, wiring and a first type of semiconductor element or circuit are formed on a semiconductor substrate for mounting a semiconductor chip, and the wiring and a second type of semiconductor element or circuit are formed on a semiconductor substrate for mounting a semiconductor chip.
A semiconductor chip having various types of semiconductor elements or circuits is connected by a protruding electrode, and the wiring is electrically connected to an external device connection lead provided on a sealing substrate by a bonding wire or a protruding electrode. This makes it easy to create a multi-product system.
Moreover, the yield of the system is improved.
以下、本発明の構成について、本発明を、マイ
クロコンピユータに適用した実施例の半導体装置
とともに説明する。 Hereinafter, the structure of the present invention will be explained together with a semiconductor device according to an embodiment of the present invention applied to a microcomputer.
[実施例 ]
第1図は、本発明の実施例の半導体装置の封
止用キヤツプを取り外し、配線を省略した平面
図、第2図は、第1図の−切断線における断
面図である。[Embodiment] FIG. 1 is a plan view of a semiconductor device according to an embodiment of the present invention with a sealing cap removed and wiring omitted, and FIG. 2 is a sectional view taken along the - cutting line in FIG. 1.
なお、実施例の全図において、同一機能を有す
るものは同一符号を付け、そのくり返しの説明は
省略する。 In addition, in all the figures of the embodiment, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted.
第1図及び第2図において、1は封止用(パツ
ケージ)基板であり、アルミナで形成されてい
る。この封止用基板1には、配線(図示していな
い)、ボンデイングパツド2及び外部装置と電気
的に接続するためのリードピン3が設けられてい
る。4は半導体チツプ5を塔載するための塔載用
半導体基板(マザーチツプ)であり、半導体チツ
プ5と熱膨張率を等しくするために、単結晶シリ
コンで形成されている。この塔載用半導体基板4
には、例えば高速度で外部素子又は外部装置への
駆動能力の大きいバイポーラ型の入出力回路(又
はレベル変換回路、インタフエース回路等)6、
論理回路7等が形成されている。これらのバイポ
ーラ型半導体素子又は回路として、例えば非飽和
形のECL(emiter coupled logic)等の回路構成
が適用できる。また、その配線領域8には配線
(図示していない)が形成され、その周辺部には
ボンデイングパツド9が形成されている。そし
て、塔載用半導体基板4は、封止用基板1の中央
部に接着剤で接着され、前記ポンデイングパツド
2と9をボンデイングワイヤ10で電気的に接続
してある。 1 and 2, reference numeral 1 denotes a sealing (package) substrate, which is made of alumina. This sealing substrate 1 is provided with wiring (not shown), bonding pads 2, and lead pins 3 for electrical connection to external devices. Reference numeral 4 denotes a mounting semiconductor substrate (mother chip) on which the semiconductor chip 5 is mounted, and is made of single crystal silicon in order to have the same coefficient of thermal expansion as the semiconductor chip 5. This tower-mounted semiconductor substrate 4
For example, a bipolar type input/output circuit (or level conversion circuit, interface circuit, etc.) 6, which has high speed and large driving capacity to external elements or devices,
A logic circuit 7 and the like are formed. As these bipolar semiconductor elements or circuits, for example, a circuit configuration such as a non-saturated ECL (emiter coupled logic) can be applied. Further, a wiring (not shown) is formed in the wiring region 8, and a bonding pad 9 is formed around the wiring. The mounting semiconductor substrate 4 is bonded to the center of the sealing substrate 1 with an adhesive, and the bonding pads 2 and 9 are electrically connected with a bonding wire 10.
前記半導体チツプ5は、例えば、ROM(read
only memory),RAM(random access
memory)等の低消費電力の相補型記憶回路11
及び12が形成されている。この半導体チツプ4
は、塔載用半導体基板4に半田等のぬれ性の良好
な突起電極13で電気的に接続されている。 The semiconductor chip 5 is, for example, a ROM (read
RAM (random access)
Low power consumption complementary memory circuit 11 such as
and 12 are formed. This semiconductor chip 4
is electrically connected to the mounting semiconductor substrate 4 by a protruding electrode 13 having good wettability such as solder.
このように塔載用半導体基板4に予め高速度で
外部素子又は外部装置への駆動能力の大きいバイ
ポーラ型の入出力回路6、論理回路7を形成して
おき、低消費電力の記憶回路11又は12が設け
られている半導体チツプ5を突起電極13を介し
て塔載用半導体基板4に電気的に接続することに
より、多種の半導体素子又は回路のシステムが容
易に形成することができる。すなわち、システム
の機能を分割して、その分割された各機能の所定
種類の半導体素子又は回路をそれぞれ塔載用半導
体基板4又は半導体チツプ5上に作成しておき、
それらを組み立てることにより、多種の半導体素
子又は回路からなる多品種の半導体装置が容易に
できる。 In this way, the bipolar input/output circuit 6 and the logic circuit 7, which have a large driving capacity to external elements or devices at high speed, are formed in advance on the semiconductor substrate 4 for mounting, and the memory circuit 11 or the logic circuit 7 with low power consumption is formed in advance. By electrically connecting the semiconductor chip 5 provided with the semiconductor chip 12 to the mounting semiconductor substrate 4 via the protruding electrodes 13, various types of semiconductor elements or circuit systems can be easily formed. That is, the functions of the system are divided, and predetermined types of semiconductor elements or circuits for each divided function are created on the mounting semiconductor substrate 4 or the semiconductor chip 5, respectively.
By assembling them, various types of semiconductor devices including various semiconductor elements or circuits can be easily manufactured.
また、一つの半導体チツプ4上に形成されてい
るシステムを機能別に分割して、各機能別の半導
体素子又は回路を有する半導体チツプを作成し、
これらを組合せるようにすることにより、ウエハ
を小さい半導体チツプに分割できるので、そのシ
ステムの歩留を向上することができる。 In addition, the system formed on one semiconductor chip 4 is divided by function to create a semiconductor chip having semiconductor elements or circuits for each function,
By combining these, the wafer can be divided into small semiconductor chips, thereby improving the yield of the system.
また、相補型半導体チツプ5はモジユール内部
のみ駆動できれば十分であり、外部素子又は外部
装置への駆動能力は塔載用半導体基板4上のバイ
ポーラ型半導体素子又は回路でかせげるため、標
準的な相補型半導体チツプ5を用いても、高速度
で外部素子又は外部装置への駆動能力の大きいも
のが実現できる。 In addition, it is sufficient that the complementary semiconductor chip 5 can drive only the inside of the module, and the driving ability for external elements or devices can be achieved by the bipolar semiconductor element or circuit on the mounting semiconductor substrate 4. Even if the semiconductor chip 5 is used, it is possible to realize a device with a high speed and a large driving capacity for external elements or devices.
また、例えば、消費電力の大きい記憶回路11
及び12に、低消費電力の相補型半導体素子又回
路が使用できるので、低消費電力の半導体装置が
得られる。 In addition, for example, the memory circuit 11 with large power consumption
And 12, since complementary semiconductor elements or circuits with low power consumption can be used, a semiconductor device with low power consumption can be obtained.
また、前記塔載用半導体基板4を規格化すれ
ば、コストパーフオマンスが向上できる。 Further, by standardizing the mounting semiconductor substrate 4, cost performance can be improved.
[実施例 ]
第3図は、本発明の実施例の半導体装置の塔
載用半導体基板と配線領域とのレイアウトを示す
平面図、第4図は、第3図の−切断線におけ
る断面図である。[Example] FIG. 3 is a plan view showing the layout of a mounting semiconductor substrate and wiring area of a semiconductor device according to an example of the present invention, and FIG. 4 is a sectional view taken along the - cutting line in FIG. 3. be.
本実施例は、第3図及び第4図に示すよう
に、前記実施例1の変形であり、塔載用半導体基
板4の配線領域8を多層配線技術の利用により、
入出力回路7、レベル変換回路14等のバイポー
ラ型半導体回路上にまで拡大したものである。 As shown in FIGS. 3 and 4, this embodiment is a modification of the first embodiment, and the wiring area 8 of the mounting semiconductor substrate 4 is formed by using multilayer wiring technology.
This is expanded to include bipolar semiconductor circuits such as the input/output circuit 7 and the level conversion circuit 14.
このように配線領域8を拡大することにより、
相補型半導体チツプ5を配置できる面積が広がる
ので、相補型半導体チツプ5対塔載用半導体基板
4の比率を向上することができる。すなわち、有
効半導体素子の相補型半導体チツプ5を多く設け
ることができるので、外部素子又は外部装置への
駆動能力の大きい比較的低消費電力の大規模集積
回路の半導体装置が実現できる。 By enlarging the wiring area 8 in this way,
Since the area in which the complementary semiconductor chips 5 can be arranged is expanded, the ratio of the complementary semiconductor chips 5 to the mounting semiconductor substrate 4 can be improved. That is, since a large number of complementary semiconductor chips 5 of effective semiconductor elements can be provided, it is possible to realize a large-scale integrated circuit semiconductor device with relatively low power consumption and a large drive capability for external elements or devices.
また、本実施例2においては、図3に示すよう
に高速・高駆動動作のバイポーラ型入出力回路
7,7が、塔載用半導体基板4の主面において、
互いに対向する2辺の近傍に配置され、かつ、高
速・高駆動動作のバイポーラ型レベル変換回路1
4,14が他の2辺の近傍に配置されている。こ
れにより、外部装置と、バイポーラ型入出力回路
7およびバイポーラ型レベル変換回路14との距
離を短くすることができるので、外部装置に対す
る駆動力を向上させることができ、本実施例の半
導体装置を有する回路系の動作速度を向上させる
ことが可能となつている。 In addition, in the second embodiment, as shown in FIG.
A bipolar level conversion circuit 1 arranged near two opposing sides and capable of high-speed, high-drive operation.
4 and 14 are arranged near the other two sides. This makes it possible to shorten the distance between the external device and the bipolar input/output circuit 7 and the bipolar level conversion circuit 14, thereby improving the driving force for the external device. It has become possible to improve the operating speed of the circuit system that has.
[効果]
以上説明したように、本願において開示された
新規な技術によれば、以下に述べるような効果を
得ることができる。[Effects] As explained above, according to the novel technology disclosed in this application, the following effects can be obtained.
(1) 塔載用半導体基板に予め高速度で外部素子又
は外部装置への駆動能力大きいバイポーラ型の
レベル変換回路、入出力回路、論理回路を形成
しておき、低消費電力の記憶回路が設けられて
いる半導体チツプをフリツプ・チツプ方式の突
起電極を介して塔載用半導体基板に電気的に接
続する構造にすることにより、多種の半導体素
子又は回路を用いた多品種のシステムが容易に
形成することができる。すなわち、システムの
機能を分割して各々の機能を備えた塔載用半導
体基板及び半導体チツプを作成しておき、それ
らをフリツプ・チツプ方式で組み立てることに
より、多品種のシステムの半導体装置を容易に
得ることができる。(1) Bipolar level conversion circuits, input/output circuits, and logic circuits with high driving capacity for high-speed external elements or external devices are formed in advance on the semiconductor substrate for mounting, and a memory circuit with low power consumption is provided. By creating a structure in which a semiconductor chip is electrically connected to a mounting semiconductor substrate via a flip-chip protruding electrode, a wide variety of systems using a variety of semiconductor elements or circuits can be easily formed. can do. In other words, by dividing the functions of a system, creating mounting semiconductor substrates and semiconductor chips with each function, and assembling them using the flip-chip method, semiconductor devices for a wide variety of systems can be easily fabricated. Obtainable.
(2) 前記(1)により、システム設計が簡単になる。(2) The above (1) simplifies system design.
(3) システムの機能を分割して、それぞれの機能
の半導体チツプを作成し、それらを組合せるこ
とにより、ウエハを小さく分割することができ
るので、そのシステムの歩留を向上することが
できる。(3) By dividing the functions of the system, creating semiconductor chips for each function, and combining them, it is possible to divide the wafer into smaller pieces, thereby improving the yield of the system.
(4) 前記(1)により、半導体チツプはモジユール内
部のみ駆動できれば十分であり、外部素子又は
外部装置への駆動能力は塔載用半導体基板上の
バイポーラ型半導体素子又は回路でかせげるの
で、標準的な相補型半導体チツプを用いても、
外部素子又は外部装置への駆動能力の大きいも
のが実現できる。(4) According to (1) above, it is sufficient that the semiconductor chip can drive only the inside of the module, and the driving ability for external elements or devices can be achieved by bipolar semiconductor elements or circuits on the semiconductor substrate for mounting, so standard Even if complementary semiconductor chips are used,
A large driving capacity for external elements or devices can be realized.
(5) 前記(1)により、相補型半導体素子又は回路が
使用できるので、低消費電力の半導体装置が得
られる。(5) According to (1) above, complementary semiconductor elements or circuits can be used, so a semiconductor device with low power consumption can be obtained.
(6) 前記(1)において、塔載用半導体基板を規格化
すれば、コストパーフイマンスが向上できる。(6) In (1) above, if the semiconductor substrate for mounting is standardized, cost performance can be improved.
(7) 塔載用基板に設けられたバイポーラ型半導体
素子又ま回路の上にまで配線領域を拡大するこ
とにより、相補型半導体チツプを配置できる面
積が広がるので、相補型半導体チツプ対塔載用
半導体基板の比率を向上することができる。(8)
前記(7)により、有効半導体素子の相補型半導体
チツプを多く設けることができるので、外部素
子又は外部装置への駆動能力の大きい比較的低
消費電力の大規模集積回路の半導体装置が実現
できる。(7) By expanding the wiring area to the top of the bipolar semiconductor element or circuit provided on the substrate for mounting, the area in which complementary semiconductor chips can be placed is expanded, so it is possible to The ratio of semiconductor substrates can be improved. (8)
According to (7) above, it is possible to provide a large number of complementary semiconductor chips for effective semiconductor elements, so it is possible to realize a large-scale integrated circuit semiconductor device with relatively low power consumption and a large drive capability for external elements or devices.
(9) 高速・高駆動動作のバイポーラ型入出力回路
および高速・高駆動動作のバイポーラ型レベル
変換回路を、塔載用半導体基板の主面の周辺に
配置したことにより、外部装置と、バイポーラ
型入出力回路およびレベル変換回路との距離を
短くすることができるので、外部装置に対する
駆動力を向上させることができ、半導体装置を
有する回路系の動作速度を向上させることが可
能となる。(9) By arranging the high-speed, high-drive bipolar input/output circuit and the high-speed, high-drive bipolar level conversion circuit around the main surface of the tower-mounted semiconductor substrate, external devices and bipolar Since the distance between the input/output circuit and the level conversion circuit can be shortened, the driving force for external devices can be improved, and the operating speed of a circuit system including a semiconductor device can be improved.
以上、本発明を実施例にもとずき具体的に説明
したが、本発明は、前記実施例に限定されること
なく、その要旨を逸脱しない範囲において種々変
更可能であることは勿論である。 Although the present invention has been specifically explained above based on the examples, it goes without saying that the present invention is not limited to the above-mentioned examples and can be modified in various ways without departing from the gist thereof. .
例えば、前記実施例では、本発明をマイクロコ
ンピユータに適用したものについて説明したが、
他のシステムにも適用できることはいうまでもな
い。 For example, in the embodiment described above, the present invention was applied to a microcomputer.
Needless to say, it can be applied to other systems as well.
第1図は、本発明の実施例の半導体装置の封
止用キヤツプを取り外ずし、配線を省略した平面
図、第2図は、第1図の−切断線における断
面図、第3図は、本発明の実施例の半導体装置
の塔載用基板と配線領域とのレイアウトを示す平
面図、第4図は、第3図の−切断線における
断面図である。
図中、1……封止用基板、2……ボンデイング
パツド、3……リードピン、4……塔載用半導体
基板、5……半導体チツプ、6……バイポーラ型
論理回路、7……バイポーラ型入出力回路、8…
…配線領域、9……ボンデイングパツド、10…
…ボンデイングワイヤ、11,12……相補型記
憶回路、13……突起電極、14……バイポーラ
型レベル変換回路である。
1 is a plan view of a semiconductor device according to an embodiment of the present invention with the sealing cap removed and wiring omitted; FIG. 2 is a sectional view taken along the - cutting line in FIG. 1; and FIG. 4 is a plan view showing the layout of a mounting board and wiring area of a semiconductor device according to an embodiment of the present invention, and FIG. 4 is a sectional view taken along the - cutting line in FIG. 3. In the figure, 1...Sealing substrate, 2...Bonding pad, 3...Lead pin, 4...Semiconductor substrate for mounting, 5...Semiconductor chip, 6...Bipolar logic circuit, 7...Bipolar Type input/output circuit, 8...
...Wiring area, 9...Bonding pad, 10...
. . . bonding wire, 11, 12 . . . complementary storage circuit, 13 . . . projecting electrode, 14 .
Claims (1)
た半導体チツプ塔載用半導体基板と、前記半導体
チツプ塔載用半導体基板の中央に形成された多層
配線領域上に突起電極を介して塔載された半導体
チツプとを備え、前記半導体チツプに相補型記憶
回路を形成するとともに、前記半導体チツプ塔載
用半導体基板の主面の周辺に、外部素子または外
部装置に電気的に接続された高速・高駆動動作の
バイポーラ型の入出力回路と、レベル変換回路と
を配置したことを特徴とする半導体装置。1. A sealing substrate, a semiconductor chip mounting semiconductor substrate mounted on the sealing substrate, and a multilayer wiring region formed in the center of the semiconductor chip mounting semiconductor substrate via a protruding electrode. A complementary memory circuit is formed on the semiconductor chip, and a semiconductor chip is electrically connected to an external element or an external device around the main surface of the semiconductor substrate for mounting the semiconductor chip. A semiconductor device characterized by having a bipolar input/output circuit with high-speed, high-drive operation and a level conversion circuit arranged therein.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59233206A JPS61112338A (en) | 1984-11-07 | 1984-11-07 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59233206A JPS61112338A (en) | 1984-11-07 | 1984-11-07 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61112338A JPS61112338A (en) | 1986-05-30 |
| JPH053138B2 true JPH053138B2 (en) | 1993-01-14 |
Family
ID=16951413
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59233206A Granted JPS61112338A (en) | 1984-11-07 | 1984-11-07 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61112338A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3880676B2 (en) * | 1997-02-21 | 2007-02-14 | 株式会社ルネサステクノロジ | Integrated circuit device |
| TWI470762B (en) * | 2007-07-27 | 2015-01-21 | 尼康股份有限公司 | Laminated semiconductor device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0658922B2 (en) * | 1982-12-24 | 1994-08-03 | 株式会社日立製作所 | Semiconductor device |
-
1984
- 1984-11-07 JP JP59233206A patent/JPS61112338A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61112338A (en) | 1986-05-30 |
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