JP2785443B2 - Parallel circuit simulation device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention is applied to a parallel circuit simulation apparatus used for designing an electronic circuit of a large-scale LSI. In particular, the present invention relates to means for obtaining a circuit division that minimizes processing time in a parallel circuit simulation.

〔Overview〕

According to the present invention, in the circuit dividing means of the parallel circuit simulation device, by setting a break for comparing the parallel circuit simulation processing time in the division repetition process, the effect of shortening the parallel circuit simulation processing time can be reduced from the comparison result of the processing time. It is possible to determine that the saturation state has been reached.

[Conventional technology]

As a conventional technique of circuit division in a parallel circuit simulation apparatus, a process of dividing a circuit having a hierarchical structure into two from a partial circuit group referred to by a top-level parent circuit while maintaining this hierarchical structure is performed by a partial circuit group. Of the maximum simulation prediction time, and repeated until the number of generated partial circuits reaches the number of processors in the parallel simulation or until the reduction of the parallel simulation processing time is saturated (Reference: 1988) Patent application No. 239218
And JP-A-2-87279).

[Problems to be solved by the invention]

In such a conventional technique, the division of leaves into two with the maximum simulation prediction time is repeated until the generated partial circuit group, that is, the number of leaves reaches the number of processors in the parallel circuit simulation, or the parallel simulation processing time reduction is saturated. However, there is no description of a method of determining that the parallel simulation processing time reduction is saturated. The processing time of the parallel circuit simulation is determined by the maximum simulation processing time of the path from the parent circuit at the highest level to the leaf. By repeating the division of the leaf having the maximum simulation processing time, the simulation processing time of only the leaf decreases, but the simulation processing time represented by the number of external nodes of the parent circuit referring to the leaf increases. The overall parallel simulation processing time is not inversely proportional to the number of leaves. Also, due to the load balance of the leaves, the parallel simulation processing time may increase in the process of repeatedly dividing the leaves,
Thereafter, by repeating the division, the load balance of the leaves may be improved and the parallel simulation processing time may be reduced. Therefore, it is not possible to stop the division processing by capturing a temporary increase in the parallel simulation processing time.
As described above, the conventional technique has a drawback that it is difficult to determine that the parallel circuit simulation processing time is minimum in the repetition process of the division processing.

An object of the present invention is to provide a parallel circuit simulation apparatus capable of correctly determining that the parallel circuit simulation processing time has been minimized during the division process.

[Means for solving the problem]

The present invention includes a preprocessing means for configuring a whole circuit including a child circuit which is a partial circuit including a physical element including a transistor and a resistor and a parent circuit which is a partial circuit referring to the child circuit in a hierarchical structure. In a parallel circuit simulation apparatus, generation definition means for defining a section from a time point at which a simulation circuit has a long predicted time into two partial circuits to a predetermined time point as one generation, and a parallel operation of all child circuits for each generation. Circuit dividing means for calculating a circuit simulation prediction time, and stopping the division processing when the parallel circuit simulation prediction time is longer than the parallel circuit simulation prediction time obtained in the previous generation.

Here, the predetermined point in time is a point in time when the maximum parallel circuit simulation prediction time of the divided partial circuit becomes longer than the maximum parallel circuit simulation prediction time of the undivided child circuit or when all division of the child circuit ends. Preferably, there is.

[Action]

The operation time of the leaf corresponding to the sum of the processing times from the leaf and the top parent circuit to the parent circuit that directly refers to the leaf is used, and the processing time of the entire parallel circuit simulation is set as the maximum operation length of all the leaves. In the process of repeating the division, the section from the time when the maximum operation length of all leaves is compared with the previous maximum operation length to the time when the next operation is compared is defined as one generation, and there are multiple leaves at the beginning of one generation When the division operation is performed in order from the one with the largest operation length of the leaf, and the maximum operation length of the leaf generated by the division of the generation becomes larger than the maximum operation length of the leaf that has not been divided in the generation yet It is determined that the balance between the operation lengths of the leaves has improved, and the processing for that generation is terminated. Also, when all the leaves of the generation have been divided, the generation is terminated assuming that the operation lengths of the leaves are equalized. If the maximum operation length of the leaf that is generated when one generation is completed is smaller than the maximum operation length of the leaf that existed at the beginning of the generation, the next generation is split, and otherwise, Then, it is determined that the maximum operation length has been minimized, and the leaf division is terminated. in this way,
In contrast to the conventional circuit division method of parallel circuit simulation, the present invention sets a break, which is a generation to compare the parallel circuit simulation processing time in the partial circuit division repetition process, so that the simulation time can be reduced due to the increase in the parallel circuit simulation time. The circuit can be determined to be in a saturated state, and a circuit division having a minimum parallel circuit simulation processing time is performed.

〔Example〕

Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 and FIG. 2 are diagrams showing a flow of a circuit dividing process of a parallel circuit simulation as this embodiment and an example of a system configuration. In this embodiment, as shown in FIG. 1, in pre-processing S2, the power supply element of the data obtained at the circuit connection data input S1 is previously raised to the uppermost parent circuit, and the parent circuit of the circuit connection data other than the power supply is supplied to the parent circuit. If there is a physical element, a child circuit is generated under each parent circuit, the top-level parent circuit is set as a node, and the other circuits are set as one leaf.
In the update process S3, leaves of the generation, that is, leaves not directly divided among leaves directly referred to by one node and having the maximum operation length are selected and set to be division symmetric. In the division determination processing S4, when it is determined that the operation length of the leaf selected in the update processing S3 is larger than the maximum operation length of the leaf already divided in the generation, the selected leaf is divided into two in the division processing S5. The process proceeds to the generation repetition determination process S6; otherwise, the process proceeds to the end determination process S7. In the generation repetition determination processing S6, if all the leaves of the generation have completed the division processing S5, it is determined that the generation has been terminated, and the result is output to the termination determination processing S7.If the number of existing leaves is equal to the number of processors, the result is output. S8
Otherwise, the process returns to the update process S3. End determination processing S7
Then, when it is determined that the maximum operation length of the existing leaf, that is, the maximum operation length of the current generation, is greater than the maximum operation length of the first leaf of the current generation, that is, the maximum operation length of the previous generation, the result output S8 is performed and the processing is performed. The process ends, and otherwise returns to the update process S3. Here, the process of repeating the update process S3, the division determination process S4, the division process S5, and the generation repetition determination process S6 is referred to as a generation process S9, and the end determination process S7 compares the operation length of each generation to minimize the maximum operation length. Is a feature of the present invention.

That is, in this embodiment, as shown in FIG. 1, an entire circuit composed of a child circuit which is a partial circuit composed of physical elements including a transistor and a resistor and a parent circuit which is a partial circuit which refers to this child circuit is constructed. It has a means for executing pre-processing S2, which is a pre-processing means configured in a hierarchical structure, and is further characterized as a means characterized by the present invention. Generation definition means for defining a section up to the point in time when the maximum parallel circuit simulation prediction time of the divided partial circuit becomes longer than the maximum parallel circuit simulation prediction time of the undivided child circuit or the point in time when all division of the child circuit ends as one generation The execution means of the generation process S9, and the parallel circuit simulation prediction time of all the child circuits for each generation are obtained,
Execution means for executing a termination determination process S7, which is a division processing stopping means for stopping the division processing when the parallel circuit simulation prediction time is longer than the parallel circuit simulation prediction time obtained in the previous generation.

FIG. 2 is a configuration example of a parallel circuit simulation apparatus that performs the circuit division processing shown in FIG. First, a circuit diagram is input by the EWS1, and circuit connection data is created. Next, the controller 2 generates a circuit division file from circuit connection data using circuit division, that is, the circuit division procedure of the present invention. The parallel circuit simulator 3 performs parallel compilation to create object data, applies the data to a parallel circuit simulation, and outputs a result file to the controller 2. Finally, display the result file on EWS1.

FIG. 3 shows an example in which the circuit division processing of the present invention is applied to an SRAM memory circuit. (A), (b), (c), (d, 1),
The division proceeds in the order of (d, 2), (e, 1), (e, 2), (e, 3). Further, numbers in parentheses accompanying the partial circuit s _n in the drawing load of the partial circuit, the numbers in parentheses associated with the leaf l _n represents the operation length.

In (a), the uppermost parent circuit s1 is added to the node n1 and another partial circuit
s2~s7 is in leaf l _1. Operation length of leaf l ₁ , 3,
376 is the sum of the loads of the partial circuits s1 to s7, which is the maximum operation length of the generation (a). Leaf l ₁ is divided into leaves l ₂ and l ₃ as shown in (b). Operation length of the leaf l ₂ is the sum of the load subcircuit s1, s2, operation length of the leaf l ₃ 3 is the sum of the load of the load and the partial circuit s3~s7 subcircuit s1. Leaves referenced directly to the section n1 from (a) is only l _1, since the completed division, generation (b) is completed, the maximum operational length of the generation operation length 2,550 leaves l ₃ Becomes Since this is smaller than the maximum operation length of the generation (a), the process proceeds to the next generation.
(B) To have leaves l ₂ and l _3, since towards the operation length of the leaf l ₃ is greater than the operation length of the leaf l _2, leaves l ₃
Is divided manner, the leaf l ₄ and l ₅ in (c). Next, the leaf l ₂ remains without being divided, because towards Operations length leaf l ₅ is larger than the operation length of the leaf l _2, divided leaves l ₂ is without generation of (c) finish.
Since the maximum operation length 1,686 (leaf l ₅ ) of the generation (c) is smaller than the operation length 2,550 (leaf l ₃ ) of the generation (b), the process proceeds to the next generation. (C) has leaves l ₂ , l ₄ and
There is a l _5, since the operation length of the leaf l ₅ is the largest,
As the leaves l ₅ of (d, 1), divided into leaves l ₆ and l _7. Leaf l
₅ followed by those operations length is larger than a leaf l _4, so from the leaves l ₆ and l ₇ which is divided operation length is greater performs division, as (d, 2), leaves l ₈ and l ₉
Becomes Since the largest operation length of the split leaves l ₆ , l ₇ , l ₈ and l ₉ is the operation length 885 of the leaf l ₇ , which is larger than 849 of the unsplit leaf l ₂ ,
The (d, 1) and (d, 2) generations end and the maximum operation length for this generation is 885. Since (d, 1) and (d, 2) Operation length 885 (leaves l ₇₎ of generation is less than the operation length 1,686 (l ₅₎ of generation (c), the process proceeds to the next generation. (D, 2) has leaves l ₂ , l ₆ , l ₇ , l ₈ and l ₉ , and leaves l ₇ of maximum operation length are leaves l as in (e, 1)
It is divided into ₁₀ and l _11. Since the operation length of the leaf l ₆ having the next longer operation length is longer than that of the leaves l ₁₀ and l ₁₁ , the leaf l ₆ is divided into leaves l ₁₂ and l ₁₃ as shown in (e, 2). The largest operation length of the unsplit leaves l ₂ , l ₈ and l ₉ is the operation length 849 of the leaf l ₂ , and the largest operation of the split leaves l ₁₀ , l ₁₁ , l ₁₂ and l ₁₃ Since the length is larger than 615 (l ₁₀ ), the leaf l ₂ is divided into leaves l ₁₄ and l _{15 as} in (e, 3). The maximum operation length 615 (leaf l ₁₀ ) of the split leaves l ₁₀ , l ₁₁ , l ₁₂ , l ₁₃ , l ₁₄ and l ₁₅ is the maximum operation length 507 (l ₈₎ of the unsplit leaves l ₈ and l ₉ ), So (e,
The generations of 1), (e, 2) and (e, 3) are ended, and the maximum operation length of this generation is set to 615. (E, 1),
Since the operation length of the (e, 2) and (e, 3) generations is smaller than the maximum operation length of the previous (d, 1) and (d, 2) generations, it is possible to proceed to the next generation. Generation processing is repeated as described above, and when the operation length of one generation becomes larger than the operation length of the generation before this one generation, the processing is stopped and the result is output. Alternatively, when the number of leaves becomes equal to the specified number of processors, the processing is stopped and the result is output.

〔The invention's effect〕

As described above, the present invention divides the circuit so that the operation length of the generated partial circuit becomes uniform, and operates when the operation length of one generation becomes larger than the operation length of the previous generation. There is an effect that it can be determined that the length is minimized.

In addition, since the operation length is equivalent to the parallel circuit simulation processing time of the data, obtaining the circuit division that minimizes the operation length has the effect of creating circuit data that minimizes the parallel circuit simulation processing time. is there.

[Brief description of the drawings]

FIG. 1 is a flowchart showing a circuit dividing process according to an embodiment of the present invention. FIG. 2 is a configuration diagram showing a configuration of an embodiment of the present invention. FIG. 3 is a diagram showing a specific example of the processing of the embodiment of the present invention. 1 ... EWS, 2 ... Controller, 3 ... Parallel circuit simulator.

Claims (2)

(57) [Claims] 1. A pre-processing means for configuring a whole circuit including a child circuit which is a partial circuit including physical elements including a transistor and a resistor and a parent circuit which is a partial circuit referring to the child circuit in a hierarchical structure. A parallel circuit simulation apparatus, comprising: a generation defining means for defining a section from a time point at which a simulation prediction time is divided into two partial circuits in order to a predetermined time point to a predetermined time point to be one generation; Dividing processing stop means for obtaining a parallel circuit simulation prediction time, and stopping the division processing when the parallel circuit simulation prediction time becomes longer than the parallel circuit simulation prediction time obtained in the previous generation. Parallel circuit simulation device. 2. The predetermined time point is a time point when the maximum parallel circuit simulation predicted time of the divided partial circuit is longer than the maximum parallel circuit simulation predicted time of the undivided child circuit, or all division of the child circuit ends. The parallel circuit simulation device according to claim 1, which is a time point.