JP2748396B2 - Logic simulation method - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a logic simulation method for a logic circuit.

[Conventional technology]

Generally, once the logic design of a logic circuit is completed, a logic simulation is performed in accordance with verification input data to verify the normality of the logic circuit. After that, if any logic change is made to the above-described logic circuit, conventionally, a logic simulation using the same verification input data is performed again on the changed logic circuit including the changed circuit. The normality of the logic circuit after this change is verified.

[Problems to be solved by the invention]

In the above-described conventional logic simulation method, even if a part of the logic circuit is changed, the logic simulation of all the logic circuits of the changed logic circuit is re-executed without reusing the logic simulation result of the changed logic circuit. However, since the normality of the logical change is verified, a large amount of computer resources are required.

The present invention has been made in view of such circumstances, and an object of the present invention is to provide a logic simulation method capable of performing a logic simulation with a small amount of computer resources when a part of a logic circuit undergoes a logic change. is there.

[Means for solving the problem]

In order to achieve the above object, the present invention provides a logic simulation of a logic circuit after a change in which a logic change is made to a logic circuit before a change in logic design, wherein all paths from a changed portion in the logic circuit after the change are Fan-out tracing means for performing fan-out tracing to find an output terminal connected to the changed portion; and performing fan-in tracing of all paths from the output terminal to the input terminal which are fan-out traced by the fan-out tracing means. Fan-in tracing means; non-simulated output terminal group information storage means for storing output terminals not fan-out traced by the fan-out tracing means as non-simulated output terminal group information; Simulation target logic times based on Simulation target circuit creating means for creating path information, and a logic simulation result of the logic circuit before change,
The logic simulation result based on the simulation target logic circuit information using the same input pattern as that used for the logic simulation of the logic circuit before the change, and a logic simulation result, and the non-simulation target output terminal group information are edited. Simulation result editing means for generating a simulation result of the entire logic circuit after the change.

[Action]

When performing a logic simulation of the changed logic circuit,
The fan-out tracing means performs a fan-out tracing of all the paths from the changed portion in the logic circuit after the change to obtain an output terminal connected to the changed portion. Then, fan-in tracing is performed on all paths from all output terminals to input terminals, and all elements connected to the output terminals are obtained. The non-simulation target output terminal group information storage means stores the output terminals not fan-out traced by the fan-out trace means as non-simulation output terminal group information, and the simulation target circuit creation means includes a fan-in trace means. Based on the result of (1), only elements that need to be newly subjected to logic simulation by adding a changed part are extracted from the changed logic circuit to create simulation target logic circuit information. Next, a logic simulation is performed on the simulation target logic circuit information using the same input pattern used in the logic simulation of the logic circuit before the change. The simulation result editing means edits the logic simulation result of the logic circuit before change, the logic simulation result of the logic circuit information to be simulated, and the output terminal group information not to be simulated to obtain the simulation result of the entire logic circuit after change. Generate. Therefore, for elements that do not affect the logic simulation result by adding the changed part, the logic simulation result of the logic circuit before the change is effectively reused, and only the elements that affect the logic simulation result by the addition of the changed part are subjected to the logic simulation. Then, these results are edited and the result of the logic simulation of the changed logic circuit is obtained, so that the computer resources used for the logic simulation of the changed logic circuit can be significantly reduced.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, wherein a simulation target circuit creating means 1 receives a pre-change logic circuit information 10 and a post-change logic circuit information 11 as input information, The tracing means 3 is controlled to output the simulation target logic circuit information 4 and the non-simulation target output terminal group information 5, and the logic simulation means 6 outputs the pre-change logic circuit information 10 and the input pattern information 12 to the input information. The logic circuit result information 13 before the change is output, or the target logic circuit result information 7 is output using the simulation target logic circuit information 4 output from the simulation target circuit creation means 1 and the input pattern information 12 as input information. The simulation result editing means 8 outputs the simulation result which is the output result of the simulation target circuit creation means 1. ® emissions target go out force terminal group information 5
And the logic circuit result information 13 before change and the target logic circuit result information 7 which are the output results of the logic simulation means 6, and the logic circuit result information 9 after change is output.

The pre-change logic circuit information 10 includes elements constituting the logic circuit when the design of the logic circuit has been completed, connection information between the elements, and the like.

The post-change logic circuit information 11 includes elements constituting the logic circuit after a part of the logic circuit corresponding to the pre-change logic circuit information 10 has been changed, connection information between the elements, and the like.

The fan-out tracing means 2 performs a fan-out tracing of the entire path from the changed portion where the change of the logic circuit is made by a known means, and obtains all output terminals connected to the changed portion.

The fan-in tracing means 3 performs a fan-in tracing on the entire path from the output terminal to the input terminal obtained by the fan-out tracing means 2 by a known means, and obtains all elements connected to the output terminal.

The simulation target circuit creation means 1 outputs the simulation target logic circuit information 4 and the non-simulation target output terminal group information 5 based on the pre-change logic circuit information 10 and the post-change logic circuit information 11. That is, the pre-change logic circuit information 10 and the post-change logic circuit information 11 are input information,
First, the pre-change logic circuit information 10 and the post-change logic circuit information 11 are compared, and the post-change logic circuit information 11 is
With respect to 10, a changed part in which elements, connection information between elements, and the like are different is extracted from the changed logic circuit information 11. Then, the fan-out tracing means 2 is controlled to obtain all the output terminals connected to the changed portion, and the output terminals which have not been subjected to the fan-out tracing according to the result of the fan-out tracing means 2 are excluded from the simulation target output terminal group information 5.
Output as Next, the fan-in tracing means 3 is controlled to obtain all the elements connected to the output terminal which has been fan-out traced by the fan-out tracing means 2. Then, the fan-out element of the input terminal in the changed logic circuit information 11 is
It is determined whether or not the fan-in trace has been performed. If the fan-in trace has not been performed, the connection between the input terminal and the fan-out element is cut off because the fan-out element is not related to the changed portion. On the other hand, when the fan-in trace is performed, the connection relationship is kept as it is related to the changed portion. Then, the result of these processes is output to the simulation target logic circuit information 4 as a simulation target logic circuit. FIG. 2 shows a processing example of the simulation target circuit creating means 1 for performing such processing.

The input pattern information 12 is stored in the logic simulation unit 6.
And information such as verification input data to be added.

The logic simulation means 6 outputs the logic circuit information before change.
A logic simulation is performed on 10 and the changed logic circuit information 11. This is performed, for example, as follows.

When the logic circuit is created, the logic simulation means 6 uses the pre-change logic circuit information 10 and the input pattern information 12 as input information and performs a logic simulation of the pre-change logic circuit information 10 according to the input pattern information 12 by a known means. Then, the logic circuit result information 13 before the change, which is the result of the logic simulation of the logic circuit information 10 before the change, is output. Then, the normality of the logic circuit is verified by the pre-change logic circuit result information 13.

Thereafter, when any logical change occurs, a logical simulation is performed on the information of the changed logical circuit (the changed logical circuit information 11). At this time, the logical simulation means 6 creates the simulation target circuit. Using the simulation target logic circuit information 4 and the input pattern information 12 which are the output results of the means 1 as input information, a logic simulation of the simulation target logic circuit information 4 is performed by a known means in accordance with the input pattern information 12, and the simulation target logic circuit information The target logic circuit result information 7 which is the result of the logic simulation of No. 4 is output.

The simulation result editing means 8 edits the input information by using the non-simulation target output terminal group information 5, the target logic circuit result information 7, and the pre-change logic circuit result information 13 as input information, and edits the input information. 9 is output. That is, the simulation result editing means 8 performs the logic simulation means before the logic circuit change, the logic circuit result information 13 before the change already output by the logic simulation means 6 and the logic simulation means after the logic change occurs in the logic circuit. First, the non-simulation target output terminal group information 5 registered in the non-simulation target output terminal group information 5 is input with the target logic circuit result information 7 output by 6 and the non-simulation output terminal group information 5 output by the simulation target circuit creation means 1. As for the output terminals, the simulation results corresponding to these output terminals registered in the pre-change logic circuit result information 13 are output to the post-change logic circuit result information 9. Next, for output terminals not registered in the non-simulation target output terminal group information 5, the simulation results corresponding to these output terminals registered in the target logic circuit result information 7 are added to the post-change logic circuit result information 9. Output. As a result, the entire logic simulation result of the changed logic circuit information 11 is output to the changed logic circuit result information 9.

Next, the operation of the present embodiment will be described based on the logic circuit of FIG. 3 which is assumed for convenience. Note that this drawing shows input terminal 100,
100-1 to 101-n, 102-1 to 102-n and elements 200, 201-
1-201-n, 202-1 to 202-n and output terminals 500-1 to 50
0-n, 501-1 to 501-n, 600-1 to 600-n, and a changed portion X, and the fan-out trace range 20 is defined by the fan-out tracing means 2 for the changed portion X. The fan-in trace target range obtained as a result of the fan-in trace performed by the fan-in trace means 3 for the output terminals within the fan-out trace target range, the fan-in trace range 21, and the fan-out trace range 20 obtained as a result. is there.

When the start of the logic simulation is instructed from the outside, first, the simulation target circuit creating means 1 operates. In step S1 of the simulation target circuit creating means 1 in FIG. 2, the before-change logic circuit information 10 and the after-change logic circuit information 11 are collated, and a changed portion X shown in FIG. 3 is extracted as a changed portion. Then, the fan-out tracing means 2 is activated in step S2.

In response, the fan-out tracing means 2 obtains the entire path from the changed portion X to the output terminal by fan-out tracing. As a result, for example, a fan-out trace range 20 shown in FIG. 3 is obtained.

Next, in step S3, one output terminal, for example, the output terminal 600-1, within the fan-out trace range 20 obtained by the fan-out trace means 2 is extracted, and the fan-in trace means 3 is activated in step S4. .

The activated fan-in tracing means 3 performs fan-in tracing from the output terminal 600-1 to the input terminal, and obtains all elements connected to the output terminal 600-1.

Then, in step S5, it is determined whether there is an output terminal that has not been fan-in traced yet, and the processing of steps S3 to S5 is performed on all the remaining output terminals. A range 21 is required.

Next, it is determined in step S6 whether or not there is a changed portion that has not been processed yet. At this time, since it is assumed that the changed portion is only X, the process proceeds to step S7, and the output terminals 500-1 to 500-n and 501-1 to 501-n, which have not been fan-out traced by the fan-out trace means 2, are set. It is output to the non-simulation target output terminal group information 5 as a logic simulation non-target output terminal.

Next, in step S8, for example, the input terminal 101-1 of FIG.
Is taken out, and in step S9, the fan-out element of the input terminal 101-1 such as the element 201-1 is taken out.
Thus, it is determined whether or not the element 201-1 has been fan-in traced by the fan-in trace means 3. Since the element 201-1 is out of the fan-in tracing range 21 and has not been fan-in traced by the fan-in tracing means 3, the input terminals 101-1 and 101-1,
The connection between the elements 201-1 is cut off. Then, in step S12, it is determined whether or not the input terminal 101-1 still has a fan-out element. Since the input terminal 101-1 still has the fan-out element 201-2, the element 2 is again determined in step S9.
01-2 is extracted, and it is determined in step S10 whether the fan-in tracing means 3 has performed fan-in tracing. At this time, the input terminal 101-1 and the element 201- are within the fan-in trace range 21 and are fan-in traced by the fan-in trace means 3.
The connection between the two is left as it is, and it is determined in step S12 whether or not a fan-out element is still connected to the input terminal 101-1. At this time, since there is no fan-out element, it is determined in step S13 whether there is any input terminal that has not been processed yet, and the processing in steps S8 to S13 is performed on all remaining input terminals, and the third processing is performed. Connection between input terminal 100 and element 200, input terminal as shown
.., The connection between the input terminal 102-1 and the element 202-1,..., The input terminal 102-n and the element 202-
The connection between n is disconnected. As a result, the input terminals 100, 101-1 to 101-n, 102-1 to 102-n and the fan-in trace area 21 fan-in traced by the fan-in trace means 3 are used as the logic circuit to be subjected to logic simulation. 4 is output.

Next, the logic simulation means 6 is started. The logic simulation means 6 uses the input pattern information 12 and the simulation target logic circuit information 4 output from the simulation target circuit creation means 1 as input information, and performs a logic simulation of the simulation target logic circuit information 4 by a known means according to the input pattern information 12. Execute The logic simulation means 6 first executes the operation of the input terminal. However, since the input terminals 100 and 102-1 to 102-n have no fan-out element, the logic simulation of that part is ended here by the simulation target circuit creation means 1, and the input terminals 101-1 to 101-n have fan-out elements. Because they are connected, they are subject to logic simulation. Therefore, the logic circuit to be subjected to the logic simulation has all the input terminals and the fan-in trace area 21 in which the fan-in trace is performed by the fan-in trace means 3, and only the elements related to the changed portion are subjected to the logic simulation. After the completion of the logic simulation, the target logic circuit result information 7 is output as a logic simulation result of the changed logic circuit information 11.

Then, the simulation result editing unit 8 outputs the pre-change logic circuit result information 13 and the target logic circuit result information 7 output by the logic simulation unit 6 and the non-simulation target output terminal group information 5 output by the simulation target circuit creation unit 1. As input information, first, for the output terminals 500-1 to 500-n and 501-1 to 501-n registered in the non-simulated output terminal group information 5,
The simulation results corresponding to these output terminals registered in the pre-change logic circuit result information 13 are output to the post-change logic circuit result information 9. Next, the output terminals 600-not registered in the non-simulation target output terminal group information 5 are output.
For 1 to 600-n, the simulation results corresponding to these output terminals registered in the target logic circuit result information 7 are output to the changed logic circuit result information 9. As a result, the logic simulation result of the entire changed logic circuit information 11 is output to the changed logic circuit result information 9.

[Effects of the Invention] As described above, according to the present invention, when there is a logic change in a part of a logic circuit, it is possible to efficiently perform a logic simulation of the changed logic circuit, thereby greatly reducing computer resources. There is an effect that it can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an example of an embodiment of the present invention, FIG. 2 is a flowchart showing an example of processing of a simulation target circuit creating means 1, and FIG. 3 is an operation explanatory diagram of the embodiment. In the figure, 1 ... simulation target circuit creation means 2 ... fan out trace means 3 ... fan in trace means 4 ... simulation target logic circuit information 5 ... simulation target output terminal group information 6 ... logic simulation means 7 ... target logic circuit result information 8 ... simulation result editing means 9 ... changed logic circuit result information 10 ... changed logic circuit information 11 ... changed logic circuit information 12 ... input pattern information 13 ... before changed Logic circuit result information 20: Fan-out trace range 21: Fan-in trace range X: Changes

Claims (1)

(57) [Claims] In a logic simulation of a post-change logic circuit in which a logic change is applied to a pre-change logic circuit that has been logically designed, a fan-out trace of all paths is performed from a changed portion in the post-change logic circuit to perform the change. Fan-out tracing means for determining an output terminal connected to a point; fan-in tracing means for performing fan-in tracing of all paths from all output terminals to input terminals fan-out traced by the fan-out tracing means; A non-simulated output terminal group information storage unit that stores output terminals that have not been fan-out traced by the fan-out trace unit as non-simulated output terminal group information, and a logical circuit information to be simulated based on the result of the fan-in trace unit. Sim to create A logic object circuit creation means, a logic simulation result based on the simulation object logic circuit information using the logic simulation result of the logic circuit before change and the same input pattern used for the logic simulation of the logic circuit before change. A logic simulation method, comprising: simulation result editing means for editing a simulation result and the non-simulated output terminal group information to generate a simulation result of the entire changed logic circuit.