JP2797337B2 - Device separation method for integrated semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of separating integrated semiconductor devices.

[Related Art] In recent years, research and development of ultra-high-speed semiconductor integrated circuits using compound semiconductors such as GaAs have been actively conducted. Since the establishment of highly controlled growth methods such as molecular beam epitaxy (MBE), research and development of ultrahigh-speed semiconductor devices and integrated circuits using high impurity density and ultrathin epitaxial semiconductor layers have progressed rapidly. ing.

Generally, in a semiconductor integrated circuit, electrical isolation between semiconductor elements is required. FIG. 3 schematically shows a typical conventional element isolation method using a GaAs MESFET as an example. FIG. 3A shows a method of forming a device isolation region by removing a conductive layer 33 between devices by etching, and FIG. 3B shows a method of forming inert ions in the conductive layer 33 between devices. The method of implanting and forming the element isolation region is shown.

In FIG. 3, 31 indicates a semi-insulating GaAs substrate, 32 indicates an undoped GaAs layer, 33 indicates an n-type GaAs layer, 34 indicates an ohmic electrode, and 35 indicates a gate electrode. ) Of 36
Denotes an element isolation region by mesa etching, and 37 in FIG. 3B denotes an element isolation region by ion implantation. The semiconductor layer on the GaAs substrate 31 is formed by using, for example, the MBE method.

[Problems to be solved by the invention]

However, such isolation between elements according to the prior art has not been fully satisfactory. This is mainly because the interface state existing at the interface between the semiconductor substrate and the epitaxial growth layer or the carbon attached when the substrate is put into the growth apparatus forms another conductive layer at the interface. Have been. Therefore, various methods have been attempted so far to remove the conductive layer existing at these interfaces. However, none of these methods has been satisfactory.

SUMMARY OF THE INVENTION An object of the present invention is to solve such a problem and to provide a method for separating elements of an integrated semiconductor device which can realize a sufficiently large separation resistance between elements.

[Means for solving the problem]

According to the method for separating elements of an integrated semiconductor device of the present invention, at least two times of ion implantation are performed between integrated semiconductor devices formed on a semiconductor layer epitaxially grown on a substrate. Layers, and a conductive layer at the interface between the substrate and the semiconductor layer, the method including the steps of performing under different conditions so that an element isolation region is formed. And at least 10 ¹² cm ⁻² or more at the interface between the semiconductor layer and the semiconductor layer to increase the resistance.

In the present invention, it is preferable that the implanted ions are composed of any one or a combination of an inert element, oxygen, nitrogen, boron, hydrogen, and an element constituting a semiconductor element.

[Action]

In the method for separating elements of an integrated semiconductor device of the present invention, at least two times of ion implantation are performed between integrated semiconductor devices formed on a semiconductor layer epitaxially grown on a substrate. At this time, at least one implantation ion is applied at an interface between the substrate and the semiconductor layer.
If the implantation conditions are set so as to increase the resistance to ¹² cm ^-2 or more, the conductive layer existing at this interface can be made electrically inactive. Further, by selecting the implantation conditions so that at least one other implantation ion renders another conductive layer existing between the elements electrically inactive, sufficient isolation between the elements can be achieved.

In this case, the implanted ions are inert elements, oxygen, nitrogen,
It has been found that it is preferable to use boron or any of the elements constituting the semiconductor element, or a combination thereof.

Embodiment Next, an embodiment of the present invention will be described with reference to the drawings.

1 (a) to 1 (c) show a main part manufacturing process of a method for separating elements of an integrated semiconductor device according to one embodiment of the present invention.

FIG. 1A is a cross-sectional view of a semiconductor crystal grown using a metal organic chemical vapor deposition method (MOCVD method). In FIG. 1 (a), 1 is a high-resistance GaAs substrate, 2 is an undoped GaAs layer, 3 is an impurity density of 2 × 10 ¹⁸ cm ⁻³ and a film thickness of 200Å.
4 is an undoped AlGaAs.
Layer.

After the epitaxial growth, as shown in FIG.
The element formation region is covered with a photoresist 5 and oxygen ions 6 are applied at 100 keV, 2 using the photoresist 5 as a mask.
The implantation is performed under the condition of × 10 ¹⁴ cm ⁻² to form the first element isolation region 7.

Subsequently, as shown in FIG. 1C, boron ions 8 are implanted under the conditions of 300 keV and 2 × 10 ¹⁴ cm ⁻² using the photoresist 5 as a mask to form a second element isolation region 9.

Subsequently, the photoresist 5 is removed to form an element.

Here, the first element isolation region 7 is a conductive layer 3 on the front side.
The second element isolation region 9 is formed of the conductive layer 3 on the front surface side;
The conductive layer at the interface 10 between the substrate 1 and the semiconductor layer 2 is electrically inactive.

FIG. 2 shows a schematic distribution of implanted ions in the depth direction of the second element isolation region 9 in this embodiment. In FIG. 2, 21 indicates the distribution of implanted oxygen ions, and 22 indicates the distribution of implanted boron ions. The maximum value of each ion density under the ion implantation conditions in this embodiment is about 10 ¹⁹
cm ^-3 . At this time, the surface density of ions near the interface is about 10 ¹³ cm ⁻² .

The resistance between the elements in this embodiment is about one order of magnitude higher than in the case of the conventional mesa etching, and it has been found that sufficient isolation between the elements is performed. Further, in the present embodiment, a phenomenon called a side gate effect, which has generally been an obstacle to high integration, has been greatly reduced. Furthermore,
Since the method according to the present invention is basically a planar technology that does not cause a level difference, it is also effective for wiring formation in a later step, and problems such as disconnection and short circuit can be avoided.

In this embodiment, the element isolation is performed by performing the ion implantation twice, but it is also possible to increase the resistance by performing the implantation more times.

The ions to be implanted are not only oxygen and boron,
Elements constituting a semiconductor element, such as hydrogen, nitrogen, an inert element, and Ga, and combinations thereof can also be used.

Further, the present invention relates to other semiconductor materials such as InP and Si, and MES.
It is equally effective for other devices such as FETs and high electron mobility transistors (HEMTs).

[Effects of the Invention] As described above, according to the present invention, very large effects can be obtained, such as a planarization of a semiconductor device, a large improvement in isolation resistance between elements, and a large reduction in a side gate effect.

[Brief description of the drawings]

1 (a) to 1 (c) are main part manufacturing process diagrams showing a method of separating elements of an integrated semiconductor device according to an embodiment of the present invention, and FIG. 2 is a depth direction of implanted ions. FIG. 3 (a) and FIG. 3 (b) are schematic structural cross-sectional views of an integrated semiconductor device using a conventional typical device isolation method. 1,31 GaAs substrate 2,32 undoped GaAs layer 3,33 n-type GaAs layer 4 undoped AlGaAs layer 5 photoresist 6,8 implanted ions 7 first element isolation Region 9: Second element isolation region 10: Substrate interface 21, 22: Distribution of implanted ions 34: Ohmic electrode 35: Gate electrode 36, 37: Element isolation region

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H01L 21/337-21/338 H01L 27/095 H01L 27/098 H01L 29/775-29/778 H01L 29 / 80-29/812 H01L 21/33-21/331 H01L 29/68-29/737

Claims (1)

(57) [Claims] At least two times of ion implantation are performed between an integrated semiconductor element formed on a semiconductor layer epitaxially grown on a substrate and a conductive layer on the surface side and an interface between the substrate and the semiconductor layer. And conducting the steps under different conditions so that an element isolation region is formed in each of the conductive layers, and the area density of the implanted ions is at least 10 ¹² at the interface between the substrate and the semiconductor layer. A method for separating elements of a semiconductor element, wherein the resistance is increased to cm ^-2 or more.