JP2841632B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a semiconductor device provided with a plurality of semiconductor elements such as a heterojunction type field effect transistor (hereinafter referred to as FET) which operates at different threshold voltages. It relates to a manufacturing method.

[Problems to be solved by conventional technology and invention]

FIG. 3 is a view for explaining a conventional manufacturing method of this kind, and shows a cross-sectional view of an inverter constituted by a heterojunction FET. Non-doped GaAs on semi-insulating GaAs substrate 1
A layer 2, an n-type AlGaAs layer 3 having a smaller electron affinity and containing a donor impurity, and an n-type GaAs layer 4 are provided. Next, a part of the n-type GaAs layer 4 and a part of the n-type AlGaAs layer 3 are selectively removed to provide a gate electrode 5. Thereafter, the source electrode and the drain electrode 6 are formed on the n-type GaAs layer 4.
Is formed, and the wiring 8 is further formed via the insulating film 7.

Incidentally, the gate threshold voltage of a heterojunction FET is generally determined by the impurity concentration in the n-type AlGaAs layer immediately below the gate electrode and the thickness of this layer. Therefore, in the illustrated inverter, in order to form an enhancement mode (hereinafter referred to as E mode) FET element and a depletion mode (referred to as D mode) FET element constituting the same on the same substrate, Depending on whether the E-mode or D-mode FET element is to be formed, the AlGaAs
The thickness of the layer 3 was changed. In other words, by changing the thickness of the active layer made of AlGaAs, FET elements having different threshold voltages can be formed on the same substrate. However, recess (groove) etching must be repeated twice independently in the gate electrode forming step. And the process was complicated. Further, there are wet etching and dry etching as etching methods, and it is difficult to accurately control the recess etching as described above having different etching depths with good reproducibility by using either method.

In addition, JP-A-60-116178 discloses a technique for forming E-mode and D-mode FET elements having different threshold voltages on the same substrate. Briefly, E mode and D mode
An E-mode FET is provided before the recess etching by providing an AlGaAs layer in advance by the thickness difference of the n-type AlGaAs layer in the mode.
The gate electrode formation region of the device is selectively removed, and the gate electrode formation process is performed simultaneously for the E mode and D mode FET devices. However, according to this technique, the number of steps for selectively removing a region where a gate electrode is to be formed of an E-mode FET element is increased, so that the steps are complicated.

Furthermore, by providing an etch stop layer, a manufacturing technology that realizes an E-mode high electron mobility transistor (hereinafter referred to as HEMT) and a D-mode HEMT on the same substrate (Solid State Device Conference (1984)) Proceedings, p359-p3
62) is also known. Briefly referring to FIG. 4, a non-doped GaAs layer 12 and a Si
The doped AlGaAs layer 13 and the upper layers 14, 15, 16 are grown by molecular beam epitaxy (hereinafter referred to as MBE).
This upper layer is composed of the GaAs layers 14, 16 and the above-described etch stop layer, ie, the AlGaAs layer 15, embedded between them. Next, part of the upper layers 14, 15, 16 and the AlGaAs layer 13 are selectively removed to provide the gate electrode 20. After this, the GaAs layer
A source electrode and a drain electrode 21 are formed on 16,
Wiring 19 is formed via insulating films 17 and 18 of SiO ₂ .

However, this technique also has a problem that the time required for crystal growth becomes longer or a step of exposing one of the regions in a step prior to the step of forming a gate electrode is required, which complicates the process.

In view of the above circumstances, the present invention provides a simple and easy-to-use semiconductor device including a plurality of semiconductor elements having a plurality of threshold voltages.
It is another object of the present invention to provide a manufacturing method capable of obtaining a high yield.

[Means for solving the problem]

In order to achieve the above object, in a method for manufacturing a semiconductor device having a plurality of semiconductor elements operating at different threshold voltages according to the present invention, a semiconductor device having an exposed surface with a plane orientation slightly inclined from a predetermined crystal plane is provided. Forming, by anisotropic etching, an exposed surface having a plane orientation coincident with the predetermined crystal plane in a predetermined region on the substrate; and implanting impurities into a predetermined portion on the exposed surface of the semiconductor substrate including inside and outside the predetermined region. Supplying a raw material containing the material, and crystal-growing semiconductor layers having different carrier densities in accordance with the plane orientation of the exposed surface in the predetermined portion; and operating the plurality of semiconductor layers operating at different threshold voltages from the semiconductor layers having different carrier densities. Forming the semiconductor element on the semiconductor substrate.

[Action]

In the crystal growth step of the semiconductor layer, the semiconductor layer formed on the exposed surface of the semiconductor substrate having a different plane orientation,
The carrier density differs depending on the plane orientation. By forming predetermined electrodes and the like on the plurality of semiconductor layers having different carrier densities, a plurality of semiconductor elements having different threshold voltages can be formed on the same substrate. That is, according to the manufacturing method of the present application, only a single crystal growth step is required to provide a difference in the threshold voltage for operating each semiconductor element.

〔Example〕

First, the principle of the present invention will be briefly described. In the present invention, in order to manufacture a plurality of semiconductor elements (for example, FETs) operating at two kinds of threshold voltages, not the thickness of a semiconductor layer to be an active layer but the impurity concentration thereof is controlled. Such impurity control utilizes characteristics of semiconductor crystal growth. That is, the fact that the carrier density (impurity concentration) of the semiconductor layer containing impurities differs depending on the plane orientation of the exposed surface of the semiconductor substrate is utilized.

FIG. 2 shows the effect of the presence or absence of the inclination angle from the crystal plane orientation on the exposed surface of the semiconductor substrate on the carrier density of the semiconductor layer on which the crystal is grown.
Here, as a semiconductor substrate, a normal vector of a (100) crystal plane is adjacent to a GaAs substrate (hereinafter, called just substrate) having an exposed surface (hereinafter, called just plane) coinciding with the (100) crystal plane. The angle between the normal vector of the exposed surface and the normal vector of the (100) crystal plane is 2 which is processed so as to be inclined by 2 ° toward the <100> direction.
A GaAs substrate (hereinafter referred to as a 2 ゜ off substrate) having an exposed surface (hereinafter referred to as a 2 ゜ off surface) indicated by ゜ was used. On this just substrate and 2 ゜ off substrate, GaAs (hereinafter, Si-GaAs) intentionally doped with Si is epitaxially grown under the same conditions by an organic metal growth method (hereinafter, referred to as OMPVE method). FIG. 2 shows the carrier density obtained by measuring the semiconductor layer. The vertical axis represents the logarithmic value of the carrier density (cm ⁻³ ) obtained by the capacitance-voltage measurement, and the horizontal axis represents the depth of the Si-GaAs layer on which the crystal is grown. The solid line is the carrier density of the Si-GaAs layer formed on the just substrate, and the dotted line is the S-GaAs layer formed on the 2 ゜ off substrate.
This is the carrier density of the i-GaAs layer. As is clear from the figure, the Si-GaAs layer formed on the 2 ゜ off
It has about 1.7 times higher carrier density than the Si-GaAs layer formed on the ust substrate. It is considered that such a difference in carrier density is caused by a difference in the amount of Si atoms taken in during GaAs epitaxial growth depending on the plane orientation of the exposed surface of the semiconductor substrate.

Therefore, if a plurality of exposed surfaces having different plane orientations are formed on a semiconductor substrate, and semiconductor layers containing impurities are simultaneously crystal-grown on these exposed surfaces, semiconductor layers having greatly different carrier densities can be formed in one step. Obtainable.
By utilizing this difference, semiconductor layers having different carrier densities, that is, active layers, can be formed in desired regions on the semiconductor substrate, so that a plurality of FETs having different gate threshold voltages can be easily manufactured on the same substrate.

FIG. 1 illustrates a method of manufacturing two semiconductor elements having two kinds of threshold voltages on the same substrate by using such characteristics of crystal growth.

The entire exposed surface of the 2 ゜ off substrate 31 is covered with an insulating film 32 (for example, S
iN _x or SiO ₂ ), a pattern having an opening in a desired region by a photoresist 33, and an insulating layer 3 by RIE.
2 is selectively etched. FIG. 1 (a) shows 2 ゜ off
FIG. 3 is a cross-sectional view of an insulating layer 32 and the like left without being etched on a substrate.

Next, using the insulating layer 32 as a mask, anisotropic etching of the GaAs substrate 31 is performed with an etching solution of sulfuric acid: hydrogen peroxide solution: water = 1: 5: 1. The exposed surface 31a at the bottom of the recess formed as a result is a just surface. When the mask of the insulating layer 32 is removed, a semiconductor substrate 31 having an exposed surface 31a of the just base surface and an exposed surface 31b of the 2 ゜ off surface is prepared (FIG. 1B).

Next, a non-doped GaAs layer 34 is formed on the semiconductor substrate 31.
5000Å (angstrom), 50 Si-doped AlGaAs layers 35
結晶, Crystal growth by OMVPE method. Subsequently,
A Si-doped AlGaAs layer 36 as a semiconductor layer to be an active layer is grown to a thickness of 300 °. The carrier density (electron density) of the Si-doped AlGaAs layer 36 is 2 × 10 4 on the just-exposed surface 31a.
¹⁸ cm ^-3 and 3.4 × 10 ¹⁸ c on the exposed surface 31b of the 2 ゜ off surface
It is controlled to be m- ³ . Therefore, the semiconductor layer formed on the exposed surface 31a of the just surface is a semiconductor device having an active layer with a lower carrier density (E in the present embodiment).
Mode FET). On the other hand, 2 ゜ o
The semiconductor layer formed on the exposed surface 31b of the ff plane is a region where a semiconductor element (D mode FET in this embodiment) including an active layer with a higher carrier density is to be formed. Thereafter, a Si-doped GaAs layer 37 is grown by 300 ° (FIG. 1 (c)).

Next, isolation between elements is performed by mesa etching or proton implantation (in the case of the embodiment of the drawing, both ends 39 of the semiconductor device).
Is mesa-etched, and protons are injected between the semiconductor elements. ), And an ohmic electrode 38 is formed (FIG. 1 (d)).

Subsequently, the Si-doped GaAs layer 37 and the Si-doped AlGaAs layer in the regions where the gate electrodes of both the E-mode and D-mode FETs are to be formed are formed.
After selectively removing a part of 36, a gate electrode 41 is formed. Then, an insulating film (for example, SiN _x or SiO ₂ ) 40 is formed on the entire surface.
To form a wiring pattern, and form a metal wiring 42 to complete the process (FIG. 1 (e)).

As described above, according to the manufacturing method of the present embodiment,
Semiconductor layers having different carrier densities can be formed by a single crystal growth. In addition, a pre-process before crystal growth is simple because a mask for performing anisotropic etching does not require high-precision fine processing. Further, formation of an electrode for operating the active layer made of the semiconductor layer is
Since the operations can be performed simultaneously on the semiconductor layers, FETs having different gate threshold voltages can be obtained simply and with good yield. Therefore, it is effective to apply the embodiment to a semiconductor device including an inverter circuit or the like.

In the above embodiment, the exposed surface 31a on which the E-mode FET is to be formed is the (100) plane, and the exposed surface 31b on which the D-mode FET is to be formed is slightly inclined from the (100) plane toward the (110) plane. Needless to say, these plane orientations can be arbitrarily set as long as a difference is given to the carrier density as described above.

Further, in the above description, a semiconductor device including a heterojunction FET has been described. However, the present invention is not limited to this, and can be applied to the manufacture of a semiconductor device including MESFET, DMT, and the like. . Further, the present invention is applicable to a method of manufacturing a semiconductor device such as an inverter composed of a plurality of devices, that is, an inverter formed of semiconductor elements, using an n-type semiconductor active layer crystal-grown on a semiconductor substrate. The present invention can also be applied to a semiconductor device including an integrated circuit. The n-type impurity is not limited to Si, but may be Se, Te, or S.

Note that the crystal growth method of the semiconductor layers having different carrier densities formed by different plane orientations is described in the OMVP of the above embodiment.
It is not limited to the E method. For example, the semiconductor layer may be formed using an MBE method, a CBE (chemical beam epitaxy) method, or the like.

〔The invention's effect〕

As described above, according to the manufacturing method of the present invention, semiconductor layers having different carrier densities can be easily formed by a single crystal growth. Therefore, active layers having different threshold voltages can be simultaneously formed on the same substrate surface. For this reason, a semiconductor device including semiconductor elements operating at different threshold voltages can be manufactured simply and with high yield.

[Brief description of the drawings]

FIG. 1 is a view showing an embodiment of a method for manufacturing a semiconductor device according to the present invention, FIG. 2 is a view showing that the carrier density of a semiconductor to be crystal-grown varies depending on the plane orientation of an exposed surface of a semiconductor substrate, FIG. 3 is a view showing a heterojunction FET manufactured by a conventional technique, and FIG.
FIG. 3 is a diagram showing an EMT. 31 ... semiconductor substrate, 31a ... just exposed surface, 31b ...
2 ゜ off exposed surface, 36 ... AlGaAs semiconductor layer, 38 ...
... ohmic electrode, 41 ... gate electrode.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H01L 21/337-21/338 H01L 27/095 H01L 27/098 H01L 29/775-29/778 H01L 29 / 80-29/812

Claims (1)

(57) [Claims] 1. A method of manufacturing a semiconductor device having a plurality of semiconductor elements operating at different threshold voltages, wherein a predetermined region on a semiconductor substrate having an exposed surface with a plane orientation slightly inclined from a predetermined crystal plane is provided. Forming an exposed surface having a plane orientation coincident with the predetermined crystal plane by anisotropic etching, and supplying a source material containing impurities to a predetermined portion on the exposed surface of the semiconductor substrate including inside and outside the predetermined region; Crystal-growing semiconductor layers having different carrier densities in accordance with the plane orientation of the exposed surface in a predetermined portion; and converting the plurality of semiconductor elements operating at different threshold voltages from the semiconductor layers having different carrier densities to the semiconductor substrate. A method of manufacturing a semiconductor device.