JP2801683B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Purpose of the Invention] (Industrial application field) The present invention relates to an improvement of a GTO thyristor device with a MOS gate including a drive circuit unit.

(Prior Art) FIG. 5 shows a configuration of a conventional GTO thyristor with a MOS gate and its drive circuit unit. The GTO thyristor, a high-resistance N ^- high density on one surface of the base layer 1 N buffer layer 2
, A P ⁺ emitter layer 3 is provided, and a P base layer 4 is selectively provided on the other surface.
Has a PNPN structure in which an N ⁺ emitter layer 5 is selectively disposed on the surface thereof. A gate electrode 7 is provided on the surface of P base layer 4 interposed between N ⁻ base layer 1 and N ⁺ emitter layer 5 via a gate insulating film 6, and a cathode electrode 8 is in contact with the surface of N emitter layer 5. A base electrode 9 is provided in contact with the surface of the P base layer 4. As a drive circuit for performing ON / OFF control of the GTO thyristor, a first drive circuit 11 is provided between the cathode electrode 8 and the base electrode 9, and a second drive circuit 12 is provided between the cathode electrode 8 and the gate electrode 7. Is provided.

The turn-on and turn-off operations of this GTO thyristor with MOS gate are as follows. First, when the element is turned on, the second driving circuit 12 causes the gate electrode 7 to be turned on.
, A positive voltage is applied to the cathode electrode 8. Then, an inversion layer is formed on the surface of the P base layer 4 immediately below the gate insulating film 6 to form an N channel, and electrons are injected into the N ⁻ base layer 1 from the N ⁺ emitter layer 5. Along with this, holes are injected into the N ⁻ base 1 from the P ⁺ emitter layer, and the holes are collected by the N ⁺ emitter layer 5 through the P base layer 4. At this time, electrons are directly injected from the N ⁺ emitter layer 5 into the P base layer 4, collected by the N ⁻ base layer 1 and turned on.
At this time, in order to perform a faster turn-on operation,
The first drive circuit 11 may apply a zero or positive voltage to the base electrode 9 and the cathode electrode 8. When a positive voltage is applied to the base electrode 9, a forward bias voltage is applied to the PN junction formed by the P base layer 4 and the N ⁺ emitter layer 5, thereby promoting electron injection from the N ⁺ emitter layer 5. Because.

Next, turn-off will be described. First, the first drive circuit 11 causes the base electrode 9 to
Apply a negative voltage. Then, since a reverse bias voltage is applied to the PN junction between the N ⁺ emitter layer 5 and the base layer 9, holes accumulated in the P base layer 4 and the N ⁻ base layer 1 are discharged to the base electrode 9. Then, the junction between the N ⁺ emitter layer 5 and the P base 4 is gradually recovered, and the injection of electrons from the N ⁺ emitter layer 5 into the P base layer 4 is stopped. Next is the second
When a zero or negative voltage is applied to the gate electrode 7 by the drive circuit 12, the inversion layer immediately below the gate insulating film 6 disappears, and the injection of electrons from the N ⁺ emitter layer 5 to the N ⁻ base layer 1 is completely stopped. In particular, in order to accelerate the turn-off operation, the gate electrode 7
, It is necessary to quickly discharge the charge of the gate capacitance by applying a negative bias voltage to the gate. After that, the base electrode 9
When holes accumulated in the device completely disappear due to the reverse bias voltage applied to the device, the device is turned off.

Here, one method of turning off such a GTO thyristor with a MOS gate at high speed is to increase the reverse bias voltage applied to the P base layer 4. When the reverse bias voltage is increased, holes are quickly discharged, and a high-speed turn-off becomes possible. As a result, the current concentration of the element is reduced, and the turn-off capability (maximum turn-off current) is increased. However, if the speed of the turn-off operation is increased by this method, the following problem occurs.

A high reverse bias voltage applied between the cathode electrode 8 and the base electrode 9 is applied to the gate electrode 7 and the cathode electrode 8.
When the voltage between them is zero, that is, when the second drive circuit 12 is short-circuited, it is also applied between the base electrode 9 and the gate electrode 7 as it is, and the gate insulating film 6 may be broken by a high electric field.

To quickly discharge the charge of the gate capacitance, it is necessary to apply a negative bias voltage between the gate electrode 7 and the cathode electrode 8.
A PN junction diode composed of the base layer 4 and the N ⁺ emitter layer 5 enters in series. This PN junction diode can be used without considering the reverse bias between the P base layer 4 and the N ⁺ emitter layer 5.
It functions to prevent a voltage from being effectively applied between the gate electrode 7 and the P base layer 4. Actually, the P base layer 4-
Since a reverse bias is applied between the N ⁺ emitter layers 5 and has a polarity that cancels the electric field between the gate electrode 7 and the base layer 4, the electric field between the gate electrode 7 and the base layer 4 is sufficiently large. To do so, the reverse bias voltage applied between the gate electrode 7 and the cathode electrode 8 needs to be sufficiently high.

As a result, when a very large electric field is applied to the gate insulating film 6 between the gate electrode 7-N ⁺ emitter layer 5, the gate insulating film 6 may be broken.

In order to apply a high reverse bias between the P base layer 4 and the N ⁺ emitter layer 5, the junction blocking voltage must be sufficiently high.

(Problems to be Solved by the Invention) As described above, the conventional method of driving a GTO thyristor with a MOS gate has a problem that the gate insulating film may be destroyed in order to realize high-speed turn-off.

The present invention solves such a problem by using a G-gate with a MOS gate.
The purpose is to provide a TO thyristor device.

[Structure of the Invention] (Means for Solving the Problems) A GTO thyristor device with a MOS gate according to the present invention comprises:
A second drive circuit for supplying a control signal to the gate electrode is connected to a first drive circuit for supplying the P base control signal with reference to the potential of the cathode electrode, with reference to the potential of the base electrode. And

(Operation) When the GTO thyristor with the MOS gate is operated by the connection of the driving circuit, the bias voltage applied between the base electrode and the cathode electrode and the bias voltage applied between the gate electrode and the base electrode are each a reference voltage. Therefore, no voltage is applied between the base electrode and the cathode electrode between the gate electrode and the base electrode. As a result, a high reverse bias voltage can be applied between the base electrode and the cathode electrode without destruction of the gate insulating film, and high-speed turn-off can be performed.

(Example) Hereinafter, an example of the present invention will be described.

FIG. 1 shows an embodiment of the present invention. The same reference numerals as in FIG. 5 denote the same parts as in FIG. 5, which is a conventional example, and a detailed description thereof will be omitted. The element structure of the present embodiment is the same as the conventional one. The difference is in the method of connecting the second drive circuit 12 for supplying a control signal to the gate electrode 7. The second drive circuit 12
It is provided between the gate electrode 7 and the base electrode 9, and is configured to supply a control signal to the gate electrode 7 using the base electrode 9 as a potential reference.

The turn-on and turn-off operations of the GTO thyristor in this embodiment are performed as follows. At turn-on,
A positive voltage is applied to the gate electrode 7 with respect to the base electrode 9. Then, as described in the conventional example, an inversion layer is generated on the surface of the P base 4 immediately below the gate electrode 7, electrons are injected from the N ⁺ emitter layer 5 into the layer N ^- base layer 1, and the element is turned on. At this time, a positive voltage may be applied to the base electrode 9 with respect to the cathode electrode 8 as in the conventional example.

Next, at the time of turn-off, the first drive circuit 11 applies a negative voltage to the base electrode 9 with respect to the cathode electrode 8. This is the same as the conventional one, and the behavior inside the element is the same as the conventional one. Next, the gate electrode 7 is driven by the second driving circuit 12.
, A negative voltage is applied to the base electrode 9. Here, the zero or negative voltage applied to the gate electrode 7 is
, The base electrode 9-the cathode electrode 8
The reverse bias voltage applied between them has no effect on the voltage between the gate electrode 7 and the base electrode 9. Therefore, the gate insulating film 6 is not destroyed by the voltage applied between the base electrode 9 and the cathode electrode 8, and the high-speed turn-off operation can be realized by increasing the negative bias voltage between the base electrode 9 and the cathode electrode 8. Becomes In addition, even if the reverse bias voltage applied between the gate electrode 7 and the base electrode 9 is low, the inversion layer of the P base layer 4 easily disappears, so that the gate insulating film 6 is not broken and a high-speed turn-off can be achieved. It becomes possible.

 As described above, the turn-off ability increases.

FIG. 2 shows a modification of the first embodiment in the second embodiment. In this embodiment, a lead wire 13 connecting between the first drive circuit 11 and the base electrode 9 and a second drive circuit 12
And a lead wire 14 for connecting between the base electrode 9 are provided separately and independently.

Usually, this type of element is housed in a hermetically sealed envelope, and the base electrode 9 and the gate electrode 7 are led to the envelope by lead wires such as aluminum wires. However, as shown in FIG. 1, the lead wire taken out from the base electrode 9 is connected to the base electrode 9 -the signal line applied to the gate electrode 7 and the base electrode 9-.
When the signal line provided between the cathode electrodes 8 is shared, the following problem occurs. When the element is turned off, a large current flows through the lead wire taken out from the base electrode 9, and the lead wire is lost depending on a defect of the lead wire. At this time, if the element was used in series, the element would not turn off and the entire voltage of the device would be destroyed if the element was applied to the element whose lead was extinguished. However, if the lead wire 13 for the first drive circuit 11 and the lead wire 14 for the second drive circuit 12 are provided independently as shown in FIG. In other words, a large current does not flow through the signal lead provided to the gate electrode, and there is no danger of loss. Even if the signal lead 13 provided between the base electrode 9 and the cathode electrode 8 is lost, turn-off does not occur. Although the device can be turned on, the device can be prevented from being destroyed.

FIG. 3 shows a third embodiment in which an auxiliary emitter layer 51 is provided between a main emitter layer 5 and a gate electrode 7 in a P base layer 4, and a base electrode 9 is formed between the auxiliary emitter layer 51 and the P base layer 4. I have contacted both. First and second drive circuits 1
The connection methods 1 and 12 are the same as in the previous embodiment. The control operation of this element is basically the same as in the previous embodiment. However, the turn-on mechanism is slightly different from the previous element. When a positive voltage is applied to the gate electrode 7, an inversion layer is generated on the surface of the P base layer 4 immediately below the gate electrode 7, and electrons are injected from the auxiliary emitter layer 51 into the N ⁻ base layer 1. Accordingly, holes are injected from the P emitter layer 4 into the N ⁻ base layer 1, and when the holes enter the main emitter layer 5, electrons are directly injected from the main emitter layer 5 into the P ⁻ base layer 1.
This element is injected into the N ⁻ base layer 1 through the base layer 4 to turn on the device. Here, electrons are injected from the auxiliary emitter 51 by the base electrode 9 and the auxiliary emitter layer 51
Since the base layer 4 is short-circuited, it is performed only through the inversion layer, so that the latch-up does not occur. The turn-off is the same as in the previous embodiment. Here, in the case of this embodiment, the gate electrode 7 is provided only on the surface of the P base layer 4 sandwiched between the auxiliary emitter layer 51 and the N ⁻ base layer 1 and on the exposed surface of the N ⁻ base layer 1. And the base electrode 9-
The voltage applied between the cathode electrodes 8 is never applied to the gate insulating film 6.

In the embodiment shown in FIGS. 1 and 2, the gate insulating film 6 overlying the N ⁺ emitter 5 is provided with the base electrode 9 and the gate electrode 7 from the voltage applied between the base electrode 9 and the cathode electrode 8.
A voltage obtained by subtracting the voltage applied therebetween is applied, and there is a possibility that the gate insulating film 6 in a portion in contact with the N ⁺ emitter layer 5 is broken. However, in this embodiment, such a problem does not occur because the auxiliary emitter layer 51 and the P base layer 4 are short-circuited.

FIG. 4 shows a further improvement of the embodiment of FIG.
The N ⁺ emitter layer 5 is surrounded by a P ⁻ or N ⁻ low concentration layer 40, and the low concentration layer 40 is further surrounded by P ⁺ layers 41 and 42. With this configuration, the blocking voltage between the base electrode 9 and the cathode electrode 8 is improved, and the voltage applied between the base electrode 9 and the cathode electrode 8 at the time of turn-off can be made higher, so that a faster turn-off can be performed. Become.

The present invention is not limited to the above embodiment. For example, in the embodiment shown in FIGS. 3 and 4, the lead wires from the base electrode 9 to the first and second drive circuits 11 and 22 may be separated as in the embodiment shown in FIG. Further, the present invention can be applied to an element in which the conductivity type of each part shown in the embodiment is reversed. Further, the present invention can be applied to a device in which a single crystal layer is formed on a substrate having a dielectric isolation structure surrounded by an oxide film, and a contact type device in which an anode region is formed on the same surface as a cathode region.

[Effects of the Invention] As described above, according to the present invention, a high reverse bias voltage can be applied between a base electrode and a cathode electrode without breaking a gate insulating film, and a high-speed turn-off can be achieved. GTO with MOS gate with high turn-off capability
An apparatus can be provided.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a first embodiment of the present invention, and FIG.
FIG. 3 is a diagram showing a configuration of a second embodiment of the present invention, FIG. 3 is a diagram showing a configuration of a third embodiment of the present invention, and FIG.
FIG. 5 is a diagram showing a configuration of a fourth embodiment of the present invention, and FIG. 5 is a diagram showing a configuration of a conventional example. 1 ... N ^- base layer, 2 ... N buffer layer, 3 ... P ⁺ emitter layer, 4 ... P base layer, 5 ... N ⁺ emitter layer, 6 ... Gate insulating film, 7 ... Gate electrode , 8 ... cathode electrode, 9 ... base electrode, 10 ... anode electrode, 11 ... first drive circuit, 12 ...
... second driving circuit, 13, 14 ...... lead, 40 ...... P ^- or N ^-
Low-concentration layer, 41, 42 ... P ⁺ layer, 51 ... auxiliary emitter layer.

──────────────────────────────────────────────────続 き Continuation of front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H01L 29/74-29/749

Claims (4)

(57) [Claims] A first conductive type emitter layer, a second conductive type base layer, a first conductive type base layer, and a second conductive type emitter layer, wherein the first conductive type emitter layer has a first conductive type emitter layer; A second main electrode is provided on the main electrode and the second conductive type emitter layer, and a base electrode is provided on the first conductive type base layer, respectively, and the second conductive type base layer and the second conductive type base layer on the surface of the first conductive type base layer are provided. A GTO thyristor with a MOS gate in which a gate electrode of a MOS structure is provided in a region sandwiched between two conductive type emitter layers; and a second main electrode connected between the second main electrode and the base electrode. A first drive circuit for supplying a control signal to the base electrode on the basis of a second drive circuit connected between the base electrode and the gate electrode and supplying a control signal to the gate electrode on the basis of the base electrode And a driving circuit of The semiconductor device according to claim. 2. A first conductive type emitter layer, a second conductive type base layer, a first conductive type base layer, and a second conductive type emitter layer having a four-layer structure. The main electrode and the second conductive type emitter layer are provided with a second main electrode, a first conductive type base layer, and a base electrode extending over the second conductive type auxiliary emitter layer formed on the surface thereof. In a region between the second conductive type base layer and the second conductive type auxiliary emitter layer on the surface of the one conductive type base layer
A GTO thyristor with a MOS gate provided with a gate electrode having a MOS structure, and a control signal connected between the second main electrode and the base electrode and supplying a control signal to the base electrode based on the second main electrode. A first drive circuit connected between the base electrode and the gate electrode, and a second drive circuit for supplying a control signal to the gate electrode with reference to the base electrode. Semiconductor device. 3. The semiconductor device according to claim 2, wherein a low impurity concentration layer of a first conductivity type or a second conductivity type is formed around said second conductivity type emitter layer. 4. A lead wire connecting the first drive circuit and the base electrode and a lead wire connecting the second drive circuit and the base electrode are provided independently of each other. 3. The semiconductor device according to any one of 3.