JP2807290B2 - Method for manufacturing semiconductor device - Google Patents

Description

The present invention relates to a semiconductor device, for example, a Schottky gate field effect transistor (GaAsFET) using GaAs as a constituent material.
In particular, the present invention relates to a method for forming a conductive semiconductor layer serving as a channel layer to a predetermined thickness with good controllability when performing recess etching or the like of a gate portion.

[Prior Art] A method of manufacturing a GaAs FET will be described as an example of a conventional semiconductor device.

The GaAsFET has a semiconductor channel layer, which is a conductive semiconductor layer, formed on a semi-insulating substrate by epitaxial growth, and has on its surface a source electrode, a drain electrode in ohmic contact, and a gate electrode in Schottky contact. The semiconductor device controls the drain current by changing the conductance of the channel layer between the source and drain electrodes by a voltage applied to the gate electrode.

In such a GaAsFET, there is an optimum current value for improving high-frequency characteristics such as a power gain and a noise figure, and it is extremely important to control a saturated drain current (IDSS) to a predetermined value. Therefore, in order to control the IDSS to a predetermined value, reduce the series resistance between the source and gate electrodes, and further improve the withstand voltage of the drain, the semiconductor channel layer near the gate electrode is thinned to a required thickness. ) Structure is adopted. In addition, along with this, the distance between the source and drain is reduced,
Short gate lengths are being implemented.

As a conventional method of manufacturing a GaAs FET having such a recess structure, for example, a method as shown in FIG. 4 has been employed.

That is, first, as shown in FIG.
The region of the channel layer 22 formed by epitaxial growth on the As substrate 21 is limited to a predetermined region by selective etching or the like. As shown in FIG. 3B, an opening 24 for recess etching is provided by patterning the coated photoresist 23. A recess 25 as shown in FIG. 3C is formed by electrolytic etching using an appropriate electrolytic solution, and a gate metal 26 is deposited. As shown in FIG. 2D, a gate electrode 27 is formed by lift-off, and then the coated photoresist 28 is patterned to provide openings for the source electrode and the drain electrode. An ohmic metal is deposited, and a source electrode 29 and a drain electrode 30 are formed by lift-off as shown in FIG.

In the above-described manufacturing method, the thickness of the channel layer 22 in the recess 25 is obtained from the difference between the initial thickness of the epitaxial layer and the amount of etching by electrolytic etching. However, it is difficult to accurately determine the thickness of the epitaxial layer, and there is also an error in the amount of etching. Therefore, it has been difficult to accurately control the thickness of the channel layer in the recessed portion to a predetermined thickness. .

In order to solve this problem, the fact that the depletion layer extending to the channel layer during electrolytic etching reaches the semi-insulating substrate is detected from the change in current (hereinafter referred to as ICELL) at the time of etching, and this is terminated. Attempts have been made as a measure of However, this method also has the following problems.

That is, as shown in FIG. 1A, which will be described later, when electrolytic etching is performed through the opening 7 of the recess mask, the recess forming region to be etched is a region 8 immediately below the opening 7 and a region between the opening 7 and the opening 7. It can be divided into a curved portion region 9 of an undercut portion which is a side surface region formed along the periphery. By detecting from the change in ICELL that the depletion layer in the region 8 directly below the opening 7 has reached the semi-insulating substrate 1, the thickness of the channel layer 2 in the recessed portion becomes equal to the width of the depletion layer. Should be able to determine. However, in practice, the area of the above-mentioned curved portion region 9 where the depletion layer does not reach the semi-insulating substrate 1 becomes larger as the recess depth becomes deeper.
It becomes difficult to detect changes in ICELL.

[Problems to be Solved by the Invention] In a conventional method of manufacturing a semiconductor device in which the thickness of a channel layer in a recess portion is determined from the difference between the initial thickness of an epitaxial layer and the etching amount by electrolytic etching, It is difficult to accurately determine the thickness, and there is also an error in the amount of etching. Therefore, it has been difficult to accurately control the thickness of the channel layer to a predetermined thickness.

Also, at the time of electrolytic etching, the fact that the depletion layer extending to the channel layer at the bottom of the recess has reached the semi-insulating substrate is detected from the change in the current ICELL during the etching, and this is used as a guide to the end of the etching. In other manufacturing methods,
The area of the curved region of the undercut portion, which is the side surface region formed at the periphery of the mask opening, increases as the recess depth increases, and the depletion layer in this curved region does not reach the semi-insulating substrate. Therefore, there is a problem that it is substantially difficult to detect a change in ICELL due to a current leak in this region, and it is difficult to control the thickness of the channel layer in the recess to a predetermined thickness.

Therefore, an object of the present invention is to provide a method for manufacturing a semiconductor device in which the thickness of a conductive semiconductor layer in a formation region of a concave portion can be formed to a predetermined thickness with good controllability.

Means for Solving the Problems In order to solve the above problems, the present invention provides (a) a step of forming a conductive semiconductor layer on a substantially insulating substrate, and (b) this conductive semiconductor layer. above, first had first opening having a first opening area S _a, and the second opening area S _b 2
Forming a thin film of photoresist or the like having an opening of (c) using the thin film of photoresist or the like as a mask to start etching of the conductive semiconductor layer using an electrochemical etching method; Detecting a change in the current or voltage level used in the electrochemical etching method caused by the depletion layer extending to the bottom of the concave portion formed by the etching reaching the substrate, and terminating the etching, and Sum of first and second opening areas S _a
+ S _b is the gist that the manufacturing method of the semiconductor device is 10 times or more the total area S _A + S _B side region consisting undercut by etching.

Here, S _A of the first opening, S _B is a side area of the second opening. Further, the "first opening" corresponds to affect the opening characteristics of the semiconductor device, therefore, the first opening area S _a is a predetermined area defined by the design. For example, the first opening corresponds to a recess for forming a gate electrode of a Schottky gate field effect transistor. On the other hand, the second opening is an opening serving as an etching monitor region, and has a second opening area _Sb that can be freely selected within a range of S _a + S _b > 10 (S _A + S _B ).

The “electrochemical etching method” includes an electrolytic etching method, an anodic oxidation method, and the like. For example, during the electrolytic etching, when a depletion layer extending to the bottom of the concave portion generated by the etching reaches the substrate, the current I
_{Since the CELL} changes, the change in the level of the current I _CELL can be used as a guide to the end of the etching.
Also, the current I _CELL at the time of etching can be configured to be constant, and even if a rise in voltage is detected, it can be used as a measure of the end of etching.

[Operation] As described above, in the present invention, the first region of the concave region is formed.
The sum of the second opening area S _b of the opening area S _a and monitor areas of
S _a + S _b is the sum of the areas S _A + S _{B of the} side areas formed by undercut along the periphery of the opening in both areas.
It is set to be more than 10 times larger. Therefore, the leakage current passing through the depletion layer extending to the conductive semiconductor portion in the side surface region is caused by the first opening area _Sa and the second opening area _Sb.
Is relatively small compared to the current flowing through. Therefore, even when the semiconductor device has the fine first opening that satisfies S _a <S _b , the depletion layer extending to the portion of the conductive semiconductor layer immediately below the first and second openings is not reduced. , When the substrate reaches a substantially insulating substrate, the etching current I _CELL
Alternatively, the etching can be accurately detected from a change in the voltage level or the like, and the etching can be accurately completed. Therefore, by previously determining the relationship between the electrochemical etching conditions such as electrolytic etching and the depletion layer width, the thickness of the conductive semiconductor in the recess formation region is formed to a predetermined thickness with good controllability.

Embodiment An embodiment of the present invention will be described below with reference to FIGS. 1 to 3.

This embodiment is directed to a GaAs FET having a recess structure.
Has been applied to the manufacturing method.

First, a high-resistance buffer layer having a thickness of about 2 μm and a conductive semiconductor layer having an n-type carrier concentration of about 3 × 10 ¹⁷ cm ⁻³ and a thickness of about 0.3 μm are formed on a semi-insulating GaAs substrate 1 by vapor phase epitaxial growth. A channel layer 2 is formed. By patterning a photoresist on the surface of the channel layer 2 into a required shape and performing selective etching or the like, a plurality of
The region is limited to a region 3 such as an FET and a power supply line 4 for electrically connecting the region 3 such as an FET when etching by electrolytic etching or the like.

Further, the photoresist 5 coated on the surface of the channel layer 2 is patterned to form a first opening 7 (first recess 7) having a first opening area Sa in a recess (recess) forming region 6 in a region 3 such as an FET. Mask), and I is added to the detection region (monitor region) 11 in the region 3 of another FET or the like.
_A second opening 12 (monitor mask) having a second opening area S _A for CELL change detection is formed. Note that the first opening 7 and the second opening 12 can be simultaneously formed on the photoresist 5 using the same mask.

Here, the second opening area S _A of the second opening 12 is set as follows.

That is, the first opening area Sa that defines the size of the recess portion
Affects FET characteristics, and its dimensions cannot be freely changed. Then, when etching is performed to a depth d from the first opening 7, a region 8 immediately below the first opening 7 shown in FIG. 1A, that is, a first opening area Sa
(Hereinafter, the symbol Sa is also used when referring to the area directly below the first opening.) And the area of the curved portion region 9 of the undercut portion, which is a side surface region formed along the peripheral edge of the first opening 7.
Sb is as follows, respectively.

Sa = 1ｌW ₁ Sb ≒ π (l + W ₁ ) ・ dl, W ₁ is the first opening 7 as shown in FIG.
Length and width, and the etching was assumed to proceed isotropically. In this embodiment, if l = 0.5 μm, W ₁ = 300 μm, and d = 0.2 μm, Sa = 1.5 × 10 ⁻⁸ (cm ² ) Sb ≒ 1.9 × 10 ⁻⁸ (cm ² ), which is just below the first opening. Area Sa and Area of Curved Area 9
The relationship of Sb is Sa <Sb (1). For this reason, when the electrolytic etching proceeds, as described above, even when the depletion layer in the region 8 directly below the first opening 7 reaches the semi-insulating GaAs substrate 1, the etching of the curved region 9 is dominant. Therefore, it is difficult to detect a change in ICELL.

Here, the area of the region 13 immediately below the second opening 12, that is, the area immediately below the second opening 12 is S _A, and an undercut which is a side surface region formed along the peripheral edge of the second opening 12. Assuming that the area of the curved portion region 14 of the portion is S _B , the opening area S _A of the second opening 12 is to make the area of the entire curved portion region substantially negligible with respect to the area immediately below the entire opening. In addition, the sum of the first opening area Sa and the second opening area S _A is larger than the sum of the areas Sb and S _B of the two curved sections 9 and 14 by a predetermined magnification, for example, about 10 times. It is set as follows.

That is, as shown in FIG. 2 (b), the length and width of the second opening 12, when the L and W _2, the area of the second opening immediately below the area S _A and the curved region 14 S _B is as follows.

S _A = L ・ W ₂ S _B ≒ π (L + W ₂ ) ・ d If L = 30 μm, W ₂ = 100 μm and d = 0.2 μm in this embodiment, S _A = 3.0 × 10 ⁻⁵ (cm ² ) S _B ≒ 8.2 × 10 ⁻⁷ (cm ² ), and the area S _A immediately below the second opening and the area of the curved region 14
The relationship of S _B is S _A > S _B (2), and the first opening area Sa and the second opening area S _A
The sum of the area Sb of both the curved region 9,14, the relationship between the sum of S _B is as follows.

ΣSa + ΣS _A > 10 (ΣSb + ΣS _B ) (3) In the manufacturing process, since a large number of recess formation regions 6 are formed simultaneously on one substrate (wafer), the detection region 11 is determined by the above equation (3). Appropriate pluralities are formed to satisfy.

As a result of setting the second opening area S _A as described above, the total area is at least 10 times larger than the area of the entire curved portion regions 9 and 14, so that a change in ICELL can be easily detected.

Then, the recess forming region 6 and the detection region 11 opened by the first opening 7 and the second opening 12 are etched using electrolytic etching as an electrochemical etching method, thereby forming the recess forming region. A recess is formed in 6.
In this electrolytic etching, a substrate is used as an anode and a platinum electrode is used as a cathode in a solution in which a 3% tartaric acid aqueous solution and propylene glycol are mixed at a ratio of 2: 5, and the substrate is irradiated with white light so that an anodic oxide film is not formed. Low voltage,
The electrolytic etching is terminated when ICELL drops sharply. As a result, the thickness of the channel layer 2 in the region 8 immediately below the recess is formed to a predetermined thickness.

After a recess having a desired depth is formed by the above method, a gate metal is deposited and a gate is formed by a lift-off method. Subsequent steps are the same as in the above-described conventional method.

As described above, according to the manufacturing method of this embodiment, the thickness of the channel layer 2 in the region 8 immediately below the recess can be accurately formed to a predetermined thickness, so that the IDSS of the GaAs FET is controlled to a predetermined value. It becomes easier to do.

In the above-described manufacturing method, it is not necessary to particularly limit the applied voltage and the electrolytic solution composition at the time of electrolytic etching.
It goes without saying that the amount of etching can be controlled by detecting that the depletion layer formed under the anodic oxide film has reached the semi-insulating substrate. That is, in this specification, the electrochemical etching method includes both etching methods of electrolytic etching and etching using an anodic oxidation method.

In this case, the side surface region of the recessed region by etching is
It is not always necessary to have an undercut curved shape, and the etching can be controlled similarly when forming a vertical side surface.

Further, in the above-described embodiment, the fact that the depletion layer has reached the semi-insulating substrate is detected by the change of ICELL.
Can be detected by other changes in electrical level, such as a rise in voltage, while keeping the constant.

Further, in the above-described embodiment, the channel layer is formed by the vapor phase epitaxial growth method. However, the channel layer may be formed by another method, for example, the liquid phase epitaxial growth method, the MBE method, the ion implantation method, or the like.

In the above-described embodiment, the present invention is applied to the formation of the recess in the gate portion of the GaAs FET. However, the present invention is applicable to any case where the conductive semiconductor layer on the substantially insulating substrate is formed to a desired thickness. Obviously, it can be used, for example, for adjusting the thickness of an InP conductive layer on a semi-insulating InP substrate or a Si layer epitaxially grown on an insulating film.

[Effects of the Invention] As described above, according to the present invention, an opening for a recess having a first opening area of a predetermined size in a formation region of a recess on a conductive semiconductor layer and a region other than the formation region of the recess are provided. Forming a thin film having a monitor opening having a second opening area in a monitor region on the conductive semiconductor layer;
Is such that the sum of the first opening area and the second opening area is larger by a predetermined magnification than the sum of the areas of the side surface regions formed in the recessed region and the monitor region by etching. A first step of setting the thickness and the thickness of the conductive semiconductor layer based on a change in the electrical level of the conductive semiconductor layer based on a change in the electrical level during the etching. And a second step of reducing the thickness to a predetermined thickness, the etching is performed in a region directly under the first and second openings, and the depletion spreading to a portion of the conductive semiconductor layer in the region immediately under the first and second openings. The point at which the layer reaches the substantially insulating substrate can be accurately detected from changes in current or the like during etching. Therefore, there is an advantage that the thickness of the conductive semiconductor layer in the formation region of the concave portion can be formed to a predetermined thickness with good controllability.

[Brief description of the drawings]

1 to 3 are views for explaining an embodiment of a method of manufacturing a semiconductor device according to the present invention. FIG. 1 shows a longitudinal section of a recess portion formed by etching using a recess mask. FIG. 2 is a view showing a vertical section of a detection area formed by etching using a monitoring mask, FIG. 3 is a plan view showing a pattern of a recess formation area and a detection area, and FIG. FIG. 2 is a process chart for explaining a conventional method for manufacturing a semiconductor device. 1: semi-insulating GaAs substrate, 2: channel layer (conductive semiconductor layer), 6: recess (recess) formation region, 7: first opening area in the recess mask
8: a region immediately below the first opening, 9, 14: a curved portion region (undercut portion), 11: a detection region (monitor region), 12: a second opening area in the monitoring mask. Second opening, 13: an area immediately below the second opening.

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Claims (1)

(57) [Claims] (A) forming a conductive semiconductor layer on a substantially insulating substrate; and (b) forming a first opening area having a first opening area on the conductive semiconductor layer. Forming a thin film having an opening and a second opening having a second opening area; (c) etching the conductive semiconductor layer by electrochemical etching using the thin film as a mask; (D) detecting a change in a current or voltage level used in the electrochemical etching method caused by the depletion layer extending to the bottom of the concave portion formed by the etching reaching the substrate, A step of ending the etching, wherein the total of the first and second opening areas is at least 10 times the total of the area of the side surface region formed by the undercut portion by the etching. The method of production.