JP2808901B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device , and more particularly to element isolation of a device using a plurality of power supplies.

Conventionally, since an element formed in a well of the same conductivity type as a substrate is separated by a buried layer of the same conductivity type as the substrate, this element is electrically connected to another element through the substrate. , Can only be used with a single power supply.

The present invention can be used for element isolation of a device using a plurality of power supplies.

[0004]

In a conventional semiconductor device, when using an epitaxial layer as the element formation layer, element formed on the substrate and the same conductivity type in the well as shown in Figure 4 is connected with the substrate electrically I have.

FIG. 4 shows a conventional field effect transistor.
FIG. 4 is a cross-sectional view of (FET). In the figure, 1 is p-type silicon
(Si) substrate, 2 is a p ⁺ -type buried layer, 3 is an n ⁺ -type buried layer, 4 is a p-type well, 5 is an n-type well, 7 is an n ⁺ -type source / drain region, and 8 is a p ⁺ -type source. The drain region 9 is a gate formed on the substrate via a gate insulating film.

As shown in the figure, the FET formed in the well 4 of the same conductivity type as the substrate 1 is spatially separated by the buried layer 2 of the same conductivity type as the substrate 1, but is electrically separated. Connected to the board.

[0007]

Therefore, when a plurality of power supplies are used in the prior art, the elements formed in the wells of the same conductivity type as the substrate are connected to the elements of different potentials through the substrate. could not.

SUMMARY OF THE INVENTION It is an object of the present invention to electrically separate an element formed in a well of the same conductivity type as a substrate from a substrate, thereby enabling use of a plurality of power supplies for the device.

[0009]

Means for Solving the Problems To solve the above-mentioned problems, a mask having an opening on one conductivity type semiconductor substrate (1) is formed, and impurity ions of the opposite conductivity type are introduced from the opening into the one conductivity type semiconductor substrate.
(1) Injecting into the well and forming a well of opposite conductivity type (10) from its surface, and then forming a well of one conductivity type (2) from its surface in the well of opposite conductivity type (10) And the following
The buried layer of the opposite conductivity type (3) is provided in the one conductivity type semiconductor substrate (1) including the periphery of the opposite conductivity type well (10) from the surface thereof.
And then covering the one conductivity type well (2) and the opposite conductivity type buried layer (3) so as to cover the one conductivity type semiconductor substrate (1).
A step of growing an opposite conductivity type epitaxial semiconductor layer (5) thereon, and then forming one conductivity type well (4) in the opposite conductivity type epitaxial semiconductor layer (5) in a region including the one conductivity type well (2) ) forming and then is achieved by a method of manufacturing a semiconductor device characterized by comprising a step of element formed on said first conductivity type well (4) inside.

[0010]

FIG. 1 is a diagram illustrating the principle of the present invention. In the figure, 1 is a p-type Si substrate, 2 is a p ⁺ -type buried layer, 3 is an n ⁺ -type buried layer, 4 is a p-type well, 5 is an n-type well, 6 is an isolation insulating film and a SiO ₂ film, 7 is an n ⁺ type source / drain region, 9 is a gate formed on the substrate via a gate insulating film, and 10 is an n-type well according to the present invention.

According to the present invention, before forming the buried layer 2 of the same conductivity type as the substrate, a well 10 of the opposite conductivity type to the substrate is formed on the substrate,
The substrate and the same conductivity type buried layer 2 are formed in the center of the opposite conductivity type well 10 and the substrate and the opposite conductivity type buried layer 3 are formed in the peripheral portion, and then epitaxially grown to form the substrate and the same conductivity type buried layer 2. If a well 4 of the same conductivity type as the substrate is formed in the epitaxial layer on the region including the element and an element is formed in this well, the fact that the element is electrically separated from the substrate is used.

[0012]

FIG. 2 is a sectional view for explaining an embodiment of the present invention. In this example, an n-channel FET and a bipolar transistor are formed in an n-type epitaxial layer.

In the figure, 1 is a p-type Si substrate, 2 is a p ⁺ -type buried layer, 3 is an n ⁺ -type buried layer, 4 is a p-type well, 5 is an n-type well (n-type epitaxial layer), 6 Is the isolation insulating film
O ₂ film, 7 is an n ⁺ type source / drain region, 9 is a gate formed on a substrate via a gate insulating film, 10 is an n-type well according to the present invention, 11 is a p-type base region of a bipolar transistor, and 12 is a p-type base region. An n ⁺ type emitter region 13 is an n ⁺ collector contact region.

Next, an embodiment of the manufacturing process will be described. FIG.
3A to 3D are cross-sectional views illustrating a manufacturing process according to one embodiment of the present invention. In FIG. 3A, for example, arsenic ions (As ⁺ ) are implanted from the surface of the p-type Si substrate 1 using the patterned resist film as an implantation mask to a thickness of 3 to 6 mm.
A μm n-type well 10 is formed.

As ⁺ implantation conditions are energy of 100 to 200 Ke
V, dose amount is 1 × 10 ¹³ cm ⁻² . In FIG. 3 (B), n
Boron ions (B ⁺ ) are implanted into the center of
A p ⁺ type buried layer 2 of 2 to 4 μm is formed.

As ⁺ is implanted into the substrate including the periphery of the n-type well 10 to form an n ⁺ -type buried layer 3 having a thickness of 2 to 4 μm.

The conditions for implanting B ⁺ are an energy of 100 KeV and a dose of 1 × 10 ¹³ cm ⁻² . In FIG. 3C, an n-type or undoped epitaxial layer 5 having a thickness of 2 to 3 .mu.m and a resistivity of 1 to .OMEGA..OMEGA.cm is grown on the substrate.

In FIG. 3D, B ⁺ is implanted into the n-type epitaxial layer 5 in a region corresponding to the inside of the p ⁺ -type buried layer 2 to form a p-type well 4. B ⁺ implantation conditions are energy of 100 KeV and dose of 1 × 10 ¹² to 1 × 10 ¹³ cm ⁻² .

Activation annealing is performed on the conductive-type impurities implanted in the above steps by heat treatment in a later step.
Thereafter, through a normal process, the inside of the p-type well 4 or n
An element is formed in the type epitaxial layer 5.

Although a p-type substrate is used in the embodiment, in the case of an n-type substrate, the conductivity of each region may be reversed.

[0021]

As described above, the device formed in the well of the same conductivity type as the substrate can be electrically separated from the substrate, and as a result, it is possible to use a plurality of power supplies for the device.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a cross-sectional view illustrating one embodiment of the present invention.

FIG. 3 is a sectional view illustrating a manufacturing process according to one embodiment of the present invention.

FIG. 4 is a cross-sectional view of a conventional FET.

[Explanation of symbols]

Reference Signs List 1 p-type Si substrate 2 p ⁺ -type buried layer 3 n ⁺ -type buried layer 4 p-type well 5 n-type well (n-type epitaxial layer) 6 SiO ₂ film as isolation insulating film 7 n ⁺ -type source / drain region 8 p ⁺ -Type source / drain region 9 gate 10 n-type well 11 p-type base region 12 n ⁺ -type emitter region 13 n ⁺ -type collector contact region according to the present invention

Continuation of front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H01L 27/06

Claims (1)

(57) [Claims] An opening mask is formed on a semiconductor substrate of one conductivity type, and impurity ions of an opposite conductivity type are implanted into the one conductivity type semiconductor substrate through the opening to form an opposite conductive impurity ion from the surface thereof. Forming a mold well (10), then forming one conductivity type well (2) in the opposite conductivity type well (10) from the surface thereof, and then forming the opposite conductivity type well (10). A buried layer of opposite conductivity type from the surface in the one conductivity type semiconductor substrate (1) including the periphery
A step of forming (3), and then the one conductivity type well (2) and the opposite conductivity type buried layer (3)
A step of growing the opposite conductivity type epitaxial semiconductor layer (5) on the one conductivity type semiconductor substrate (1) over the then the reflected Taishirube conductivity type epitaxial semiconductor region including the first conductivity type well (2) One-conductivity well in layer (5)
(4) forming a, then the method of manufacturing a semiconductor device which comprises a step of element formed on said first conductivity type well (4) inside.