JP2819355B2 - Printer head - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printer head, and more particularly, to a printer head having a built-in signal processing function to reduce the load on a central processing unit.

[Prior Art] In a conventional printer head, a central processing unit in a printer or an external personal computer processes all signals related to the printer head,
The burden on the central processing unit is large. Therefore, it is necessary to reduce the load on the central processing unit by incorporating a signal processing function in the printer head.

[Problems of the Invention] An object of the present invention is to reduce the load on a central processing unit by incorporating a signal processing function in a printer head. To mitigate. An object of claim 2 is to provide a configuration for easily performing block selection. A fourth object of the present invention is to provide a method for inverting the direction of print data for each block.

[Constitution of the Invention] The present invention is directed to a time-division printer head that divides a print of one line into a plurality of blocks and prints the blocks. Such printer heads include an optical printer head that emits a large number of light emitting diodes in block units and a thermal head that emits a large number of heating elements in block units.

According to the present invention, print data and a clock pulse are input from outside the printer head by serial transfer, and the print data is input to the storage unit and the clock pulse is input to the block detection unit. The block detection means detects the input of print data for one block based on the number of clock pulses, and changes the block to be printed (hereinafter, this signal is referred to as a block detection signal). Further, based on the block detection signal, the print data in the storage means is transferred in parallel to the latch circuit, and is sent from the latch circuit to a block such as a light emitting diode or a heating element. As the block detecting means, a shift register or the like can be used in addition to the counter. If it is an n-ary counter, it is not different from an n-ary counter if it is changed to an n-stage shift register and a signal of the n-th stage of the shift register is taken out. After inputting the print data for the last block, a dummy clock pulse for one block is additionally input to the block detecting means. During this dummy clock, the latch circuit sends out the printing data of the last block, and the block selecting means selects the last block. Then, an internal reset signal is generated for each line and each block detection signal,
The block detecting means and the block selecting means are reset. This is because the printing of one line is not completed with the block detection signal for one line, but the printing is completed with one block detection signal of one line.

With this configuration, the block can be detected by the printer head, and the load on the central processing unit can be reduced.
Also, signal transmission between the central processing unit and the printer head may be serial transmission, and the bus line is simplified. On the other hand, signal transmission between the storage means and the latch circuit is parallel transmission at high speed, and the distance between the storage means and the latch circuit is short, so that the bus line is not complicated. Further, the print data can be input to the storage means even while the latch circuit is transmitting the print data to the light emitting diode or the like. Note that the printer head is not the central processing unit, but the output buffer and DMA of the central processing unit.
It may be connected to a controller or the like. The operation of the blocks such as the light emitting diode and the heating element is delayed by one block with respect to the print data from outside the printer head. This is because the data is transferred from the storage means to the latch circuit after the input of the print data for one block is completed. However, in the present invention, the last block can be printed during the dummy clock, and the reset signal can be generated in the print head.

According to the second aspect of the present invention, the block selecting means includes a block number counting means and a decoder for decoding an output of the block number counting means, and decodes a signal of the block number counting means to select a block. In this way, for example, the two counters and the decoder can know the block to be selected. For the block number counting means, a shift register or the like may be used in addition to the counter.

According to the third aspect of the present invention, the storage means is a shift register, and print data is input from the shift register to the latch circuit between the last clock pulse of the block and the first clock pulse of the next block. This input command signal is called a latch signal. With this configuration, the print data is transferred to the latch circuit immediately after the print data of the block is input to the shift register 1, and the print data of the next block can be input immediately.

The print data from the latch circuit to the blocks such as the light emitting diodes and the heating elements may need to be inverted for each block. This is due to, for example, the structure of a bus line between a block such as a light emitting diode and a latch circuit. Therefore, the invention of claim 4 makes it possible to reverse the input direction to the shift register for each block.

Embodiments of the present invention include a shift register, a latch circuit,
The block detecting means, the decoder, etc. may be designed by TTL or the like, or they may be integrated on one chip.

Embodiment An embodiment will be described using an optical printer head as an example. In the embodiment, each of the 64 light emitting diodes is integrated on one chip to form a light emitting diode block, and 40 blocks (2560 light emitting diodes) are driven. Each block has one cycle, for example.
It is driven in a time division of about 1.2 msec.

A special consideration in designing the embodiment is that the signal from the central processing unit of the printer is reduced to the minimum necessary, such as print data and clock pulses, to reduce the load on the central processing unit. In the embodiment, a shift register is used as a storage means as a buffer, data transfer from the shift register to a latch circuit (latch signal), change of a light emitting diode block (block detection signal and block selection signal), strobe signal, reset signal The signal (SWLR) for inverting the input direction to the shift register is generated inside the printer head. The light emitting diode block is controlled using a transistor array, which is controlled by a block selection signal. The light emitting diode is driven at a constant current and the light output is constant.

In the embodiment, in addition to the print data and the clock pulse, the request from the central processing unit was requested.
This is a control signal for system reset. Alternatively, the central processing unit may be partially used with the help of the central processing unit, for example, the strobe signal may be generated from the central processing unit.

For convenience of explanation, the embodiment shows more circuits than actually necessary. For example, a latch signal from a block detection signal or an input direction inversion signal (SW
LR) and the strobe signal are provided with separate generation circuits, but these generation circuits can be integrated into one. These signals may also be generated directly by the block detection means.

FIG. 1 is a detailed circuit diagram of the embodiment, and FIG. 2 is a block diagram. 1 and 2, reference numeral 02 denotes a central processing unit in the printer, 2 denotes input direction inverting means for a shift register, 4 denotes a shift register, 6 denotes a latch circuit, A0 to A63 denote AND gates, and B0 to B63 denote The constant current circuits, A65 to A67, are AND gates. C1 and C2 are, for example, hexadecimal counters. The initial value is 0 and the maximum value is 63. The counter C1 corresponds to block detection means, and the counter C2 corresponds to block number counting means. 8 is a DFF, 10 is an inverter, 12 is a strobe signal generation request circuit, and 14 is a strobe signal generation circuit.
The strobe signal generation request circuit 12 generates a signal (strobe request signal) synchronized with the last clock of one block, generates a strobe signal with the signal, and simultaneously ends input of one block of print data to the central processing unit 02. Report. The strobe signal generation circuit 14 is, for example, a one-shot multivibrator. But for example the counter C1
Can be decoded to extract the strobe signal. The central processing unit 02 can also generate a strobe signal based on the strobe request signal. D1, D2, and D3 are decoders, decoders D1 and D2 are hexadecimal decoders, and decoder D3 is decimal. Reference numerals 16 and 18 denote inverters, reference numeral 20 denotes a transistor array including 40 switching transistors, and reference numerals L1 to L40 denote light emitting diode blocks in which 64 light emitting diodes are integrated. In the description of the block diagram, the counter C1 and the AND gates A65 to A67 are collectively referred to as a counter 22, and the decoders D1 to D3 are collectively referred to as a decoder 24. The combination of the counter 22 and the decoder 24 is the block selection means. Reference numeral 26 in FIG. 1 denotes an OR circuit for resetting.

The main signals in FIGS. 1 and 2 will be described. The latch signal is active low and is generated from the rising edge of the last clock pulse of the block to the counter C1 until the rising edge of the next clock pulse, and the print data of the shift register 4 is transferred to the latch circuit 6 in parallel. SWLR specifies whether the input direction to the shift register 4 is from left or right. The strobe signal is a printing command, and opens the gates A0 to A63 connected to the latch circuit 6. Block detection signal is 64
This is caused by the input of a number of clock pulses. Here, it is divided into two parts due to timing problems. The output of the counter C1 is generated at 63 (initial value is 0) to the strobe signal generation request circuit 12 and the like, and the output of the counter C1 is generated at the counter C2.
Occurs when 63 changes to 0.
Add 1 to C2. The output of the counter C2 is a block selection signal, which is decoded by the decoders D1 to D3. Vk1 to VK40
Are the outputs of the decoders D1 to D3, VK1 operates the light emitting diode block L1, and VK40 is the light emitting diode block L40.
Means to operate. There are 64 data buses between the constant current circuits B0 to B63 and the light emitting diode blocks L1 to L40, and the order of print data is inverted for each block.
For example, assuming that the rightmost light emitting diode is connected to the first data path in block n, the rightmost light emitting diode is connected to the 64th data bus in block n + 1. This is because, as shown in FIG. 3, the wire bonding is facilitated through the data bus below the blocks L1 to L40, and the data bus is turned back every block.

When the output of the counter C2 is 0, it indicates that the print data of the first block of the line is being input to the shift register 4. When the output of the counter C2 is 1, the first block L1 is driven. Therefore, the transistor array 20 is not connected to the Y0 terminal of the decoder D1. The last block L40 prints one block of time after inputting print data of 40 blocks. Therefore, after inputting the print data for 40 blocks, a dummy clock pulse for one block is additionally input to the counter C1. That is, the clock pulse for one line is for 41 blocks. The internal reset signal is generated by decoding that the value of the counter C2 has reached 41 by the decoder D3. The system reset is a reset signal from the central processing unit 02, and has two modes, a line-by-line reset and a page-by-page reset. These signals are processed by the reset circuit 26 to reset the counters C1, C2, and DFF8. The system reset signal has a role of performing initialization before the operation of the printer head starts, and the driving of the printer head starts from the system reset signal.

4 to 8 show the operation of the embodiment. In FIG.
4 shows an operation algorithm of the embodiment. Each process shown in parallel in the figure indicates a parallel process.

The counters C1, C2 and DFF8 are reset by the system reset signal. Next, the print data and the clock pulse are input by serial transfer from the central processing unit 02, and the clock pulse for one block is counted by the counter C1 to generate a block detection signal. In accordance with the block detection signal, the print data of the shift register 4 is transferred in parallel to the latch circuit 6, and at the same time, the input direction to the shift register 4 is inverted for each block by DFF8. A strobe signal is generated after one clock pulse has elapsed from the block detection signal, and the print data is sent to the bus line via the gates A0 to A63 using this signal. The block detection signal is input to the counter C2, the number of blocks is counted, and a block is selected by the decoders D1 to D3 based on the block selection signal based on the signal, and the transistor array 20 is driven. As a result, the light emitting diode blocks L1 to L40 are time-divisionally driven by the printing signal from the data bus and the on / off of the transistor array 20. After inputting the print data for one line, a dummy clock pulse for one block is input for printing the last block. When the printing of the last block is completed, an internal reset signal is generated at the output of the Y9 terminal of the decoder D3 and reset, and the printing data and clock pulse of the next line (line reset mode) or the next page (page reset mode) are output. Wait for input.

FIG. 5 shows an operation waveform at a page reset, and FIG. 6 shows an operation waveform at a line reset. FIG. 7 shows a dummy clock pulse. During the dummy clock pulse, dummy print data may or may not be added. FIG. 8 shows a detailed waveform of the signal. For example, t1 for the latch signal is 50 nsec or less, and t2 is about 60 to 100 nsec. After the rise of the clock pulse of the 64th dot, the latch signal is generated during the rise of the first clock pulse of the next block. Also, an inverted signal of the input direction to the shift register 4
SWLR inputs the data to the shift register 4 before the rise of the first clock pulse of the next block.

[Effects of the Invention] In the present invention, processing such as block change and data transfer from the storage means to the latch circuit is performed inside the printer head, thereby reducing the load on the central processing unit. Since these processes are performed inside the printer head, there is no noise during data transfer from the central processing unit. Further, the input of print data and clock pulses from the outside of the printer head is a serial input, so that a bus line configuration is easy, and the data transfer from the storage means to the latch circuit is parallel transfer at a high speed, and the distance is short so that the transmission line is short. Is easy to configure. After inputting the printing data to the last block, a dummy clock pulse for one block is input so that the last block can be printed, and an internal reset signal is generated inside the printer head by the block number counting means, and the central processing is performed. Further reduce the load on the device.

According to the second aspect of the present invention, the block selecting means is composed of the block number counting means and the decoder so that the block can be easily selected.

According to the fourth aspect of the present invention, the order of the print data is inverted for each block, so that it is possible to easily cope with a zigzag type bus line.

[Brief description of the drawings]

FIG. 1 is a detailed circuit diagram of the embodiment, FIG. 2 is a block diagram thereof, FIG. 3 is a partial circuit diagram showing the structure of a data bus, FIG.
The figure is an operation flowchart of the embodiment, and FIGS.
0) and FIGS. 6 (1) to (10) are operation waveform diagrams of the embodiment,
7 (1) to 7 (7) are operation waveform diagrams of a main part of the embodiment, and FIG.
(1) to (6) are detailed operation waveform diagrams of the embodiment. In the figure, A0 to A67 AND gate, B0 to B63 constant current circuit, C1, C2 counter, D1 to D3 decoder, L1 to L40 light emitting diode block, 2 input direction inverting means , 20 ... Transistor array, 26 ... Reset circuit.

Claims (4)

(57) [Claims] 1. A printer head which divides a print of one line into a plurality of blocks and performs time-division printing in block units, and storage means for storing print data serially transferred from outside the printer head. A latch circuit for receiving print data for one block in parallel from the storage means and storing the data, and counting clock pulses sent in synchronization with the print data from outside the printer head, and inputting print data for one block. A block detecting means for detecting the number of blocks, a block number counting means for counting the number of blocks by counting the input signal from the block detecting means, and a block selecting means for changing a block by the count value. Each time the block detection means detects the input of one block of print data, The print data of the storage unit is transferred to the latch circuit in parallel, and the block is changed by the block selection unit. After the print data for the last block is input, a dummy clock pulse for one block is input to the block detection unit from outside the printer head. The printer head is characterized in that the block detecting means and the block selecting means are reset each time the block number counting means counts one line and one block. 2. The printer head according to claim 1, wherein said block selecting means comprises a block number counting means and a decoder for decoding a signal of said block number counting means. 3. A storage device comprising a shift register,
The print data of the shift register is transferred in parallel to the latch circuit between the last clock pulse of the clock pulse for one block to the block detection means and the first clock pulse to the next block. The printer head according to claim 1, wherein: 4. An input direction inverting means for inverting an input direction to a shift register every time one block of clock pulses is counted by the block detecting means. Printer head.