JPH0241059B2 - DMANYORUMEMORYOMIDASHIHOSHIKI - Google Patents

Description

[Detailed Description of the Invention] (1) Technical Field of the Invention The present invention relates to a DMA (direct memory access) method for exchanging data between memory and I/O without going through a CPU, and particularly relates to a DMA (direct memory access) method that exchanges data between memory and I/O without going through a CPU.
In addition, by manipulating transfer request signals, data stored at addresses with a certain arrangement can be transferred without software intervention.
Regarding the circuit system for reading with DMA.

(2) Background of the technology Thermal printers can print one line of data at the same time, but each bit has a narrow pitch of 0.1058 mm, so For example, if the number of pitches in one line is 1023, the register that stores the 1,0 information is 1023 flip-flops.
Since it would be impossible to provide a register consisting of FFs due to space considerations, we decided to use half of that number, 512. This dot information is continuously read out from the main memory using the DMA method.
It is sufficient if data can be read out to the register in the thermal printer, but it is difficult to physically set the correspondence between dots and registers so that data stored in consecutive addresses can be read out as is. Therefore, we made it possible to physically wire two registers consisting of 1023 dots and 512 flip-flops. That is, the 512 flip-flop information output from each register corresponds to 512 distributed dots over 1023 dots. For example, it is possible to make the odd-numbered dots correspond to the flip-flops of the first register and the even-numbered dots to the flip-flops of the second register, but even this would require physical wiring due to the narrow spacing between the dots. It becomes difficult. Therefore, every second dot, that is, dot data 1, 4, 5, 8, 9, 1
2, 13, ... correspond to the flip-flop FF of one register, and dot data 2, 3, 6,
By making registers 7, 10, 11, 14, 15, . . . correspond to the flip-flops of another register, two registers consisting of 1023 dots and 512 flip-flops can be physically wired. However, if such dots and registers are associated with each other, when reading data from the main memory to the register, it is not possible to change the address in a continuous address manner. It is necessary to rearrange the data corresponding to the register and the flip-flop of the second register, for example, the data of every second dot mentioned above.

(3) Prior Art and Problems Conventional DMA control methods can only read data stored in consecutive addresses. For this reason, when reading data stored at addresses that are not continuous and have a fixed arrangement, it is necessary to rearrange the data using software.

Therefore, it was necessary to create software to rearrange the data, which increased the burden on the CPU, and had the disadvantage that data transfer was slow because it was done through the CPU's software.

(4) Purpose of the invention The purpose of the present invention is to construct a circuit that matches a certain arrangement and manipulate transfer requests, thereby making it possible to read data using DMA without rearranging the data using software. This provides a DMA circuit system for processing non-continuous data.

(5) Structure of the Invention The present invention is characterized in that, in a computer system having at least a central processing unit and a random access memory connected to a data and address bus, the random Continuously changing the address from the initial value of consecutive addresses of the access memory to a specific final value and outputting it to the address bus.
A DMA controller and the slave contents of the RAM specified by the consecutive addresses latch specific data corresponding to addresses that are not consecutive addresses and have a fixed arrangement among the data output to the data bus. a latch circuit for latching the specific data in the latch circuit and at least two pulses for counting at least once within a specific cycle of a timing clock signal and generating a pulse corresponding to the counted value; a count circuit that is activated by the central processing unit and generates a pulse when setting the initial value of the address to the DMA controller.
a DMA startup circuit, the count circuit and the
The output signals of the DMA startup circuit are synthesized and the DMA
a transfer request signal generation circuit that sends a request signal for changing an address to the controller; and the DMA described above.
A switching circuit inputs specific bits of consecutive addresses output from the controller and selects which output of the counting circuit is to be sent to the transfer request signal generating circuit based on the bit information; To provide a memory read method using DMA, which is composed of a timing clock generation circuit that controls the timing of a counting circuit, and is characterized in that data stored in addresses that are not continuous addresses and have a fixed arrangement is transferred by DMA. It is.

(6) Example of the invention An example will be shown below to compare the conventional method and the present invention.

Figure 1 schematically shows a 1 x 16 dot printer head, which has print information registers for only 8 dots by switching between the first control line and the second control line. . 1 is the print head, 2 is the print information register, 3-A is the data required by the first transfer,
3-B is data required for the second transfer. In this way, in a circuit that has a fixed arrangement but requires non-continuous information, it is necessary to rearrange the data once as shown in FIG.
That is, in FIG. 2, the memory map 21 shows that 16 dots of data corresponding to the 16 dots of data in the register are stored consecutively at addresses, and then, as shown in the memory map 21, the diagonally shaded Dot data 1, 4, in address
Extract only 5, 8, 9, 12, 13, 16,
Dot data 2, 3, 6, 7, 10, 1 within the addresses in the white frame are placed in addresses 0 to 7 of the register 22.
The dot data 1, 14, and 15 are stored in addresses 8 to F of the register 22, and during the first DMA, the dot data 22-1 in the diagonal line is transferred to the print information register 2 22-11, and then the dot data 22-11 is transferred to the print information register 2. the second time
When using DMA, the white frame dot data 22-2 is transferred to the print information register 2 22-22. In FIG. 2, an arrow 22 of the print information register 2 indicates the direction of data transfer. As mentioned above, the rearrangement of dot data from the memory map 21 to the memory map 22 has conventionally been done by software, but the DMA system of the present invention is characterized in that it is done by hardware.

The circuit block diagram of the present invention is shown in Fig. 3a, the circuit diagram of the main part is shown in Fig. 4, and the time chart is shown in Fig. 5a,
Shown in b.

In FIG. 3a, the DMA controller 31 checks whether there is a transfer request signal TXREQ every falling edge of the CPU cycle clock CLK2 as shown in FIG. 3b, and if there is, it counts up (or counts down) the address. and send it. In other words, in Figure 3b, the addresses count up to N, N+1, N+2 or count down to M, M-1, M-2 at the falling edges of CLK2 1, 3, and 5 (a), but when CLK2 In numbers 2, 4, and 6, the addresses do not change (b). The RAM 32 is a RAM 32 in which print information is stored, and the stored contents are continuous data at consecutive addresses, similar to the memory map 21 in FIG. 2. Reference numeral 30 denotes a transfer request signal generation circuit which is the core of the present invention. The TXREQ creation unit 33 sends a transfer request TXREQ to the DMA controller 31, that is, a signal determining whether to raise or lower the address, to a circuit 34,
Created by combining from 35 and 36. The 3rd address count up TXREQ circuit 34 is a circuit that creates a TXREQ for advancing the 3rd address within the latch period in which the data latch circuit 39 latches data from the RAM 32 through the data bus.
This circuit is required when skipping 4 and 15 and continuing the 13 dot data, and the TXREQ circuit 35 for counting up address 1 is connected to the data latch circuit 39.
A circuit that creates a TXREQ to advance the 1st address within the latch period in which data is latched from the RAM 32 through the data bus, that is, a circuit that is required when 12 dot data is consecutively placed next to 13 dot data in the memory map 21. in,
The DMA startup circuit 36 is a circuit that starts DMA using software, the timing clock creation circuit 37 is a circuit that creates a timing clock used in this circuit, and the switching circuit 38 is a circuit that starts DMA from the address being transferred, that is, the LSB of the address. The data latch circuit ₃₉ , which is a circuit that switches between the TXREQ circuit 34 for counting up address 3 and the TXREQ circuit 35 for counting up address 1, latches the data to be transferred from the data bus, depending on the logic state of bit 1 (AD 1) of the next higher order. This is a circuit that does this.

Using FIG. 4 and FIG. 5a, the first transfer, that is, 16, 13, 12,
The general operation will be described for transferring the dot data of 9, 8, 5, 4, 1 in the direction of counting down from the dot data of 16, that is, from the data at address F (hexadecimal). To start a DMA transfer, the CPU sets the transfer start address (address F), number of transfer bytes (16), address count up/down (executed by countdown), etc. in the DMA controller 31 using software, and then After setting the flag _DT1 indicating the first transfer to ON logic 1 (that is, the output of the exclusive OR circuit 48 inverts _AD1 ), the software DMA activation request DTSET is set. As a result, the reset FF 46 is set by the rise detection circuit 460, the output of the OR circuit 43, that is, the TXREQ signal becomes logic 1, and the first TXREQ goes up to the DMA controller. The DMA controller uses this TXREQ to put the CPU in HALT state (bus available BA =
Step 1) enters the DMA control routine. Then, when this BA signal is returned, the next DSCLK
At the rising edge of , the reset FF 46 is reset and the output becomes logic 0.

The switching circuit 48 selects one of the addresses currently being transferred.
AD ₁ information and a flag indicating the first transfer,
DT ₁ sequentially switches the 3rd address count up TXREQ circuit 44 and the 1st address count up TXREQ circuit 45 including the latch FF. In other words, the output address of the DMA controller 31
When AD ₁ , which represents the logic of the bit higher than the LSB, is 1, if the output becomes 0 due to exclusive OR, BA = 1 (that is, the CPU
(Because it has been HALT and is in DMA mode)
TXREQ circuit 44 is set, but when AD ₁ is 0, it is used for counting up address 1 including latch FF.
TXREQ circuit 45 is set. In the TXREQ circuit 44 for address 3 count up, RQCLK (FF
TXREQ to advance the address by 3 is created by combining the synchronous clock) and DSCLK (FF reset signal). That is,
A waveform as shown in FIG. 5 a44 is formed. And the address counts down to three. The TXREQ circuit 45 for counting up address 1 uses a binary counter to set when AD ₁ =0,
By synchronizing with RQCLK and resetting with DSCLK, it is possible to advance the address by one address.
Create TXREQ with a delayed rise. That is, a waveform as shown in FIG. 5 a45 is formed and the address counts down by one.

As shown in the time chart in Figure 5a, by appropriately combining these 44, 45, and 46, that is, by using TXREQ43 as an OR of the three waveforms,
By latching the data as an output to the I/O at DSCLK, changing the way the address advances within the data sample cycle, i.e. changing the address at point 43 in Figure 5a. It becomes possible to read data stored at addresses that are not consecutive and have a fixed arrangement without software intervention.

FIG. 5b similarly shows the second transfer. At this time, the difference from the first transfer is that the flag _DT1 indicating the number of transfers is turned off, that is, set to logic 0. This changes the switching order of 44 and 45, and for the second transfer
TXREQ can be output. Figure 5b-4
The two points in 3 are the points where the address changes. In addition, 2
In the second transfer, if the transfer start address is the same as the first transfer, that is, the address indicated by the diagonal line of the F address in the memory map 21 with F as the start address becomes an invalid address.
Since one data worth of invalid addresses is generated, the first data is invalidated in the circuit.

In this way, in this circuit, for the logic 1 signal that requests a transfer and increments or decrements the address of the DMA controller, the length of the signal within one cycle of the clock entering the latch circuit is changed to increase the number of transfers to the logic 1 length. By simply changing the flag indicated by , it is possible to rearrange the data and read the data from the memory without any software intervention.

In the above embodiment of the present invention, the selection of dot data is 1, 4, 5, 8, 9, 12, 13,
Although the case where data 15 and 16 are set as one set and the other set is set as another set has been described, the present invention is applicable when data is not stored continuously at the address but is stored with a certain regularity. By providing the necessary hardware, you can do it without using software.
It is used to rearrange data while maintaining the DMA method.

(7) Effects of the invention As described above, according to the present invention, data stored at addresses having a certain arrangement is rearranged using hardware, so software processing is simplified and hardware processing is simplified. Since rearrangement is performed during DMA transfer, the transfer time is the same as when transferring data stored at consecutive addresses. Furthermore, the number of circuit components is reduced, and the transfer rate can be increased. For example, according to the present invention, the transfer speed is approximately doubled for a 6800 CPU. In other words, the conventional method takes about 160 μs/16 bytes, but with this method, it takes about 80 μs/16 bytes.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the relationship between the print information register and dot data, FIG. 2 is a diagram showing how dot data is rearranged during DMA transfer, and FIG. 3a is a block diagram of an embodiment of the present invention. FIG. 3b is a timing chart for the embodiment, FIG. 4 is a circuit diagram of the main part of the embodiment shown in FIG. 3a, and FIGS. 5a and b are for the first and second times, respectively. DMA
5 is a timing chart showing waveforms at various parts in FIG. 4 during transfer. FIG. 30... Transfer request signal generation circuit, 31... DMA controller, 32... RAM, 33... TXREQ generation unit, 34... TXREQ circuit for counting up address 3, 35... TXREQ circuit for counting up address 1, 36... DMA starting circuit, 37 ...Timing clock creation section, 38...Switching circuit, 39...Data latch section, 43...TXREQ creation section, 44...TXREQ circuit for counting up address 3, 45...TXREQ circuit for counting up address 1, 46...DMA starting circuit, 460 ...DTSET rising edge detection circuit, 47...Timing clock creation circuit, 48...Switching circuit, 4
9...Data latch section.

Claims (1)

[Claims] 1. In a computer system having at least a central processing unit and a random access memory connected to a data and address bus, after receiving a start signal from the central processing unit, a specific final value is determined from the initial values of consecutive addresses of the random access memory. a DMA controller that continuously changes addresses up to and outputs them to the address bus; and a DMA controller that continuously changes addresses up to and outputs them to the address bus; and a latch circuit that latches specific data corresponding to addresses having a certain arrangement and transfers it to an output device, and at least once within a specific cycle of a timing clock signal that causes the latch circuit to latch the specific data. at least two counting circuits that count and generate pulses having pulse widths corresponding to the counted values; and at least two counting circuits that are activated by the central processing unit and generate pulses when setting the initial value of the address in the DMA controller. a transfer request signal generation circuit that combines the output signals of the count circuit and the DMA activation circuit and sends a request signal for changing the address to the DMA controller; A switching circuit inputs a specific bit of an address and uses the bit information to select which output of the counting circuit is sent to the transfer request signal generating circuit, and controls the timing clock signal and the timing of each counting circuit. It consists of a timing clock generation circuit, and is characterized by DMA transfer of data stored at addresses that are not continuous and have a fixed arrangement.
Memory read method using DMA.