JP2824318B2 - Evaluation method of overlay accuracy and dimensional accuracy - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention is intended to reduce the overlay accuracy and dimensional accuracy when forming a fine pattern using photolithography and etching in the manufacturing process of a semiconductor integrated circuit device. The present invention relates to a method for evaluating overlay accuracy and dimensional accuracy for inspection and evaluation.

[Conventional technology]

Conventionally, as a method of evaluating the overlay accuracy of a conductive base pattern on a substrate and a desired mask pattern formed on a photosensitive resin film (hereinafter referred to as a resist) thereon, there is a method shown in FIG. A method called a vernier method was used, and an overlay pattern was read by visual inspection by transferring evaluation patterns having different pitches.

On the other hand, as a method of evaluating the dimensional accuracy of a desired mask pattern formed on the resist on the underlying pattern, the dimensional accuracy is evaluated by measuring the dimensions of a monitor pattern formed in the same process as the actual desired mask pattern. I was

By the way, the Vernier method as an evaluation method of the overlay accuracy will be described in detail. As shown in FIG. 7, separately from an actual device pattern, five pieces of a fixed width L are formed on a substrate 1 dedicated to error reading. The first patterns 2a, 2b, 2c, 2d, and 2e are formed, and the first patterns 2a to 2e are shifted by a predetermined amount p with respect to the first patterns 2a to 2e by a predetermined amount p.
The patterns 3a, 3b, 3c, 3d, 3e are formed.

At this time, each of the first patterns 2a to 2e of the second patterns 3a to 3e
The displacement amount p for 2e is (L-1) / 5, which is set to a value corresponding to the accuracy actually required.

Then, it is visually determined whether the positional relationship between the underlying pattern and the desired mask pattern in the actual device matches any of the patterns on the substrate 1 shown in FIG. On the basis of the positional relationship of the most left-right uniform patterns 2c and 3c at one location, for example, if the patterns 2b and 3b or the patterns 2d and 3d have a slightly shifted positional relationship from each other, the overlay error is p ( = L-1) / 5), and if they match the patterns 2a and 3a or the patterns 2e and 3e, the overlay error is 2
J is determined to be p and the actual device pattern is the seventh
The overlay error is determined depending on which of the positional relationships of the patterns in the drawing corresponds, and whether the actual overlay error between the base pattern and the mask pattern is within an allowable range is evaluated.

Next, the method of evaluating the dimensional accuracy will be described in detail. The mask pattern transferred to the resist on the underlying pattern of the actual device and the monitor pattern having the same dimensions as the mask pattern are simultaneously transferred to the resist, and the transferred monitor pattern is transferred. Is patterned on the monitor substrate 4 as shown in FIG. 8, and the dimensions of the monitor pattern itself transferred to the resist or the dimensions of the pattern 5 obtained by patterning on the substrate 4 are measured by an optical measurement method or the like. Measurement is performed by a known method such as a measurement method using an electron beam or the like, and an error from a design value is obtained to evaluate a dimensional error of the mask pattern.

[Problems to be solved by the invention]

In the conventional case, the evaluation of overlay accuracy and the evaluation of dimensional accuracy are performed in separate processes, and these accuracy evaluations may be dependent on each other in design, so both accuracy evaluations must be performed in one process. However, since the two evaluation steps are performed separately despite the fact that the evaluation is possible, there is a problem that it takes a long time for the comprehensive evaluation processing of these accuracy.

Here, the evaluation of overlay accuracy and dimensional accuracy depends on that overlay accuracy is determined by the relative positional relationship between the underlying pattern and the mask pattern, and is affected by the accuracy of the dimensions of the mask pattern and the underlying pattern. For example, if a mask pattern with a line width smaller than the standard size is formed for a base pattern with a line width larger than the standard size, the overlay error may eventually fall within an allowable range. Indicates that there is something.

The present invention has been made in order to solve the above-described problems, and has been made to evaluate overlay accuracy and dimensional accuracy.
It is an object of the present invention to enable the operation to be performed in a short time based on the results of conduction and resistance measurement of a conductive pattern.

[Means for solving the problem]

The method for evaluating overlay accuracy and dimensional accuracy according to the present invention includes the steps of: (a) using a photolithography technique to transfer a desired mask pattern onto a photosensitive resin film formed on a conductive underlying pattern on a substrate; In the overlay accuracy and dimensional accuracy evaluation method for evaluating the overlay accuracy with the pattern and the dimensional accuracy of the mask pattern, the first conductive pattern is formed in the verification pattern formation region on the substrate by the same process as the base pattern. And forming a second conductive pattern composed of two orthogonal sides on the verification pattern formation region on the substrate using a monitor mask pattern formed in the same process as the mask pattern. Forming the first verification pattern on both sides of both sides of the second verification pattern, Conduction and non conduction between turns, by measuring the resistance value of the second verification pattern,
The method is characterized in that overlay accuracy of the base pattern and the mask pattern and dimensional accuracy of the mask pattern are evaluated.

[Action]

In the present invention, the conduction / non-conduction between the first and second verification patterns and the resistance value of the second verification pattern are measured, and if both the verification patterns are conductive or non-conductive, the actual base pattern and the mask are measured. It is evaluated that the overlay error with the pattern is within the allowable range or out of the allowable range, and the second
The dimensional accuracy of the actual mask pattern is evaluated based on the difference between the measured resistance value of the verification pattern and the design value.

Thus, the conduction / non-conduction of both verification patterns and the second
Since the resistance value of the verification pattern can be measured in a series of steps, the evaluation of overlay accuracy and the evaluation of dimensional accuracy do not need to be performed in separate steps as in the related art, and the evaluation process can be performed in a shorter time than in the past.

〔Example〕

FIG. 1 is a plan view schematically showing an embodiment of a method for evaluating overlay accuracy and dimensional accuracy according to the present invention, and FIG. 2 is a sectional view taken along the line AA 'in FIG.

As shown in FIG. 1 and FIG. 2, a thin insulating film 7 is formed in a verification pattern formation region on the same substrate 6 by the same process as a conductive base pattern formed on the substrate in an actual device pattern. The first verification patterns 8a, 8b, 8c, 8d are formed by using the monitor mask pattern formed in the same process as the desired mask pattern transferred to the resist on the conductive base pattern. Two sides 9 orthogonal to the verification pattern formation region on the substrate 6
A cross-shaped conductive second verification pattern 9 composed of a and 9b is formed.

At this time, the first verification patterns 8a and 8b are located on both sides of one side 9a of the second verification pattern 9, and the first verification patterns 8c and 8c are located on both sides of the other side 9b of the second verification pattern 9. 8d
Are formed so as to be located.

After completion of a series of device forming processes, the verification pattern forming region is cut and separated, and is subjected to accuracy evaluation.

In FIG. 1, reference numeral 10 denotes each first verification pattern 8a.
8d is a measurement pad provided at one end of
Are measurement pads provided at both ends of both sides 9a and 9b of the verification pattern 9 of FIG.

By the way, the interval between the first verification patterns 8a and 8b is set, for example, to a value that allows for an overlay margin.
The same applies to the intervals between the other first verification patterns 8c and 8d. On the other hand, both sides 9a and 9b of the second verification pattern 9 are aligned, for example, in a series of steps for forming the first verification patterns 8a to 8d. Aligned with reference to the mark.

Next, a method of evaluating overlay accuracy and dimensional accuracy using the verification patterns 8a to 8d and 9 will be described with reference to various cases as shown in FIGS. 3 to 6. Here, FIGS. 3A to 6A are partially plan views, and FIGS. 3B to 6B are cross-sectional views taken along a chain line in FIG.

First, when the overlay error between the actual base pattern and the desired mask pattern is within the allowable range, as shown in FIG. 3, the second verification pattern 9 is placed between the first verification patterns 8a and 8b. Since one side 9a is located, there is no conduction between the side 9a and each of the first verification patterns 8a and 8b, and the side 9a
The resistance value between both ends of a becomes a predetermined value.

On the other hand, if the overlay error is within the allowable range, although not shown, the positional relationship between the first verification patterns 8c and 8d and the other side 9b of the second verification pattern 9 is the same as in FIG. , And there is no electrical connection between the side 9b and each of the first verification patterns 8c and 8d, and the resistance value between both ends of the side 9b becomes a predetermined value.

Next, when the overlay error between the actual base pattern and the desired mask pattern exceeds the allowable range, as shown in FIG. 4, for example, the side 9a of the second verification pattern 9
Side 9a overlaps the first verification pattern 8b, the side 9a and the first verification pattern 8b conduct, and the side 9a is shifted in the direction of the first verification pattern 8a. In this case, the side 9a and the first verification pattern 8a conduct,
When the other side 9b is displaced in the direction of the first verification pattern 8c or 8d, the side 9b and the first verification pattern 8c or 8d conduct.

Therefore, conduction / non-conduction between each of the first verification patterns 8a and 8b and the side 9a of the second verification pattern 9, and each of the first verification patterns 8c and 8d and the side 9 of the second verification pattern 9
Conduction and non-conduction with b are measured, and as a result of these measurements, if all are non-conduction, the overlay error between the actual base pattern and the desired mask pattern can be evaluated as being within the allowable range. If it is conductive, the overlay error between the actual base pattern and the desired mask pattern can be evaluated as exceeding the allowable range, and the overlay misalignment direction can be specified based on which verification pattern is conductive.

Further, the relationship between the resistance value of each side 9a and 9b of the second verification pattern 9 and the line width thereof is obtained in advance,
As shown in the figure, the line width of both sides 9a and 9b is derived from the resistance values of both sides 9a and 9b when the overlay error is within the allowable range, and the line width of the actual mask pattern is quantitatively evaluated. can do.

By the way, when the line width of the actual base pattern and the mask pattern is larger than the standard size, if the line width of the base pattern becomes large, the line width of each of the first verification patterns 8a to 8d becomes large and the interval between them becomes opposite. As shown in FIG. 5, for example, the side 9a of the second verification pattern 9
Overlaps with the first verification patterns 8a and 8b and conducts them, so that the side 9a (or 9b) and the first verification patterns 8a and 8b
(Or 8c, 8d), it is understood that the line width of either the actual base pattern or the mask pattern is larger than the standard size.

Furthermore, in order to check whether or not the line width of the actual mask pattern is smaller than the standard dimension, for example, assuming that the allowable range of the dimensional error of the actual mask pattern is ± 0.1 μm, the actual dimension is set to the lower limit of the allowable range. If the line width of both sides 9a and 9b of the second verification pattern 9 is formed to be 0.1 μm in order to check whether or not it is lower than the above, the conduction between both ends of each side 9a and 9b is checked. For example, as shown in FIG. 6, if the side 9a is disconnected halfway and the both ends of the side 9a are non-conductive, or if the both ends of the side 9b are non-conductive, the line width of the actual mask pattern is It can be evaluated that it is below the standard size.

As described above, the conduction / non-conduction of the two verification patterns 8a to 8d, 9 and the resistance value of both sides 9a, 9b of the second verification pattern 9 can be measured in a series of steps. And the evaluation of the dimensional accuracy need not be performed in separate steps, the evaluation process can be performed in a shorter time than in the past, and the efficiency of the evaluation process can be improved.

In the above embodiment, the second verification pattern 9 is formed in a cross shape. However, the second verification pattern 9 may be formed in an L shape having two orthogonal sides.

Further, in the above embodiment, the case of evaluating the overlay accuracy and dimensional accuracy of the two-layer pattern of the underlying pattern of the actual device and the mask pattern transferred to the resist thereon has been described. The present invention can be carried out in the same manner even when the above-mentioned pattern is evaluated. In this case, for example, a method of forming another verification pattern outside the patterns 8a and 8b in the cross section shown in FIG. Can be considered.

Further, several patterns in which the intervals between the first verification patterns 8a and 8b (or 8c and 8d) are changed at a predetermined pitch are prepared, and a second verification pattern 9 is formed on these patterns. By doing so, it is possible to evaluate how much the overlay accuracy can be guaranteed.

〔The invention's effect〕

As described above, according to the evaluation method of overlay accuracy and dimensional accuracy of the present invention, the conduction / non-conduction of both verification patterns and the resistance value of the second verification pattern can be measured in a series of steps. The time required for evaluating the overlay accuracy and the dimensional accuracy can be shortened as compared with the related art, which is extremely advantageous in manufacturing a semiconductor device.

[Brief description of the drawings]

FIG. 1 is a plan view of an embodiment of a method for evaluating overlay accuracy and dimensional accuracy according to the present invention, FIG. 2 is a sectional view taken along line AA 'of FIG. 1, and FIG. a) is a partial plan view for explaining the evaluation procedure of FIG. 1, (b) is a cross-sectional view of each figure, and (a) and (b) of FIG. 7 explain a conventional method for evaluating overlay accuracy. Plan view and cross-sectional view, FIG.
FIG. 2B is a plan view and a sectional view for explaining a conventional method for evaluating dimensional accuracy. In the figure, 8a to 8d are first verification patterns, 9 is a second verification pattern, and 9a and 9b are sides. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (1)

(57) [Claims] 1. A superposition accuracy between a desired mask pattern transferred to a photosensitive resin film formed on a conductive base pattern on a substrate by using a photoengraving technique and the base pattern, and the mask In the overlay accuracy and dimensional accuracy evaluation method for evaluating the dimensional accuracy of a pattern, a conductive first verification pattern is formed in a verification pattern formation region on the substrate by the same process as the base pattern, and the mask is formed. Forming a conductive second verification pattern consisting of two orthogonal sides in the verification pattern formation region on the substrate using a monitor mask pattern formed in the same process as the pattern; The first verification pattern is positioned on both sides of each of the two sides, conduction / non-conduction between the first and second verification patterns, the second verification By measuring the resistance value of the turn, the underlying pattern and the evaluation method of the overlay accuracy and dimensional accuracy and evaluating the overlay accuracy and dimensional accuracy of the mask pattern of the mask pattern.