JP2825584B2 - Method for manufacturing lead frame for semiconductor device - Google Patents

Description

The present invention relates to a method for manufacturing a lead frame, and more particularly to a method for manufacturing a lead frame for a semiconductor device.

(Prior Art) A conventional method for manufacturing a lead frame for a semiconductor device will be described with reference to the drawings. FIG. 4 shows an example of a lead frame for a semiconductor device. A diver 42 suspends the die pad 41. A plurality of internal leads 43 are arranged around the die pad 41. Outer leads 44 extend from the internal leads 43, and are supported by a connecting frame 46 via connecting members 45.

When manufacturing such a lead frame for a semiconductor device, the lead frame is manufactured by a blanking layout as shown in FIG.
The flow direction is to the right. 11 to m indicate punched shapes from the first step to the m step, respectively. In each of these steps, since the material and the material thickness are the same, the internal lead 43 of the lead frame for a semiconductor device is manufactured with the same value of punch and die clearance from the first step to the m-th step.

(Problems to be Solved by the Invention) However, in such a method for manufacturing a lead frame, the internal lead 43 punched from the first step to the last step is cut off after the tip is cut off and the internal stress is released. There was a drawback that displacement occurred in the direction punched in the process.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a method for manufacturing a lead frame in which even if the shapes of both sides of the internal lead are alternately punched, the internal lead does not shift in position and is held at a proper position. And

(Means for Solving the Problems) A method for manufacturing a lead frame for a semiconductor device according to the present invention for solving the above problems is formed by press working.
Forming one internal lead of a semiconductor device having a plurality of internal leads in two or more punching steps;
The clearance between the punch and the die in the side punching process that is punched in the previous process is larger than the clearance between the punch and the die in the side punching process that is punched in the subsequent process.

(Operation) The above-described method of manufacturing a lead frame for a semiconductor device uses the punch 61 punched out as shown by an arrow when punching one side of the internal lead 64 as shown in FIG. 6 (a). This is based on the fact that the force for moving the internal lead 64 from the normal position in the direction changes depending on the clearance C and the pressing force. That is, FIG.
As shown in (1), when punching one side of the internal lead 64 by the punch 61 and the die 63, the force for holding down the internal lead 64 is large because the stopper 65 and the die 63 press the material 65. However, as shown in FIG. 6B, in the subsequent step of punching with a punch 66 and a die 67,
The force for holding down the internal lead 64 is reduced to hold down the internal lead 64 only. Further, the force for causing the internal 64 to move from the normal position is large when the clearance C is large, and is small when the clearance C is small. The ability to hold down internal leads 64
The difference between the pre-process and post-process. To offset this difference, the internal lead 64 is kept in the proper position by making the clearance C of the side punched in the post-process smaller than the clearance C of the side punched in the pre-process. can do.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a diagram showing a layout for removing internal leads. An internal lead, a tie bar, and a die pad are punched outward from the center in order from a first step of punching out the central internal lead to an n-th step of cutting off the tip of the internal lead. Each internal lead, tie bar, and die pad are formed in two or three steps.

The clearance of the first step 1 of this blanking layout is C
1, the clearance of the second step 2 is C2, the clearance of the third step 3 is C3, the clearance of the fourth step 4 is C4, and the fifth step 5
Is C5, the clearance in the n-th step is C5, and the respective clearances have a relationship of C1>C2>C3>C4> C5.

FIG. 2 illustrates the effect of the order of the clearance and the punching configured as described above on the corresponding internal lead. FIG. 2 (a) is a cross-sectional view of a punch 21 for punching a side surface of an internal lead 24, a die 23 corresponding thereto, and a stopper 22 for guiding the punch 21 and pressing a material 25. FIG. 2B is a cross-sectional view of the punch 26, the die 27, and the stopper 22 for punching the opposite side of the internal lead 24 punched in FIG. 2A.

Internal lead 24 when punched in Fig. 2 (a)
Receives the force to bend the internal lead 24 in the direction of the arrow. Next, when the side surface of the opposite internal lead 24 already punched in FIG. 2B is punched, the internal lead 24 receives a force to bend the lead in the direction shown by the arrow.

The force generated in FIG. 2 (a) and the force generated in FIG. 2 (b) become equal by changing the clearance, and cancel each other out because they are acting in opposite directions.

FIG. 3 is a layout diagram showing another embodiment of the present invention.

The clearance of the first step 1 'and the second step 2' is C1, the third step 3 ', and the clearance of the n-th step is C5. Here also, the relationship of C1> C5 is satisfied.

With such a clearance, the force generated at the time of punching acts on the lead in the same manner as in the previous embodiment.
It is not necessary to have a regular punching layout in which punching is performed outward one after another, and the lead position can be maintained at the normal position even if a number of shapes are punched in one process.

(Effect of the Invention) As described above, in the present invention, in forming the internal lead by pressing, the clearance of the side surface punched in the subsequent process is smaller than the clearance of the side surface punched in the previous process. This has the effect of preventing misalignment of the internal leads, and is particularly effective when the internal leads are dense and the strength of the internal leads is low.

[Brief description of the drawings]

FIG. 1 is a blank layout diagram showing an embodiment of the present invention, FIG. 2 is a cross-sectional view at the time of punching showing an embodiment of the present invention, FIG. 3 is a blank layout diagram showing another embodiment of the present invention, FIG. 4 is a plan view of a lead frame, FIG. 5 is a cut-out layout diagram showing a conventional technique, and FIG. 6 is a cross-sectional view at the time of punching showing a conventional technique. 21,61… Punch 23,63… Die 24,64 …… Internal lead 26,66 …… Punch 27,67 …… Die 43 …… Internal lead

Claims (1)

(57) [Claims] In a method of manufacturing a lead frame for a semiconductor device having a plurality of internal leads formed by press working using a punch and a die, a step of punching one internal lead twice or more is provided. Wherein the clearance between the punch and the die in the side punching step punched in the preceding step is larger than the clearance between the punch and the die in the side punching step punched in the subsequent step. Lead frame manufacturing method.