JP2828007B2 - Printed circuit board wiring accommodation evaluation method and apparatus - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and an apparatus for evaluating the storability of a printed circuit board wiring, and more particularly, to a method of forming a wiring of a predetermined logic circuit on a printed circuit board having a predetermined number of wiring layers, a wiring grid interval and a substrate size. The present invention relates to a method and an apparatus for evaluating a printed circuit board wiring storability for evaluating whether or not it is storable.

[0002]

2. Description of the Related Art Conventionally, whether or not wiring of a predetermined logic circuit can be accommodated on a printed circuit board having a predetermined number of wiring layers, a wiring grid interval, and a board size is determined by the experience and intuition of a designer. Alternatively, it is general to make a determination based on temporary wiring.

[0003]

However, in the above-mentioned conventional example, there is a disadvantage that it takes a very long time and man-hour to evaluate the accommodating property. However, there were cases where the actual accommodation was not as expected, and the accuracy of the judgment was lacking.

[0004]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned disadvantages of the prior art. In particular, the present invention relates to a printed circuit board having a predetermined number of wiring layers, a wiring grid interval, and a board size. It is an object of the present invention to provide a method and an apparatus for evaluating a printed circuit board wiring accommodating property which can easily and surely evaluate the above in a short time.

[0005]

In order to achieve the above object, according to the first aspect of the present invention, the number of wiring pin pairs is calculated from a net list of a logic circuit created in advance, and the number of wiring pin pairs is calculated from predetermined board data input in advance. The total number of wiring channels of the printed circuit board is calculated, and the wiring accommodation accuracy data is extracted from the wiring accommodation accuracy data file registered in advance based on the number of wiring pin pairs and the total number of wiring channels. The method adopts a method in which the wiring accommodating property is specified based on the number and the wiring accommodating accuracy data.

According to the second aspect of the present invention, a method is employed in which the result of the determination of the wiring storability is output as a report in a predetermined format.

According to a third aspect of the present invention, a wiring pin pair number calculating means for calculating the number of wiring pin pairs from a net list of a logic circuit created in advance, and a total wiring channel of the printed circuit board from predetermined board data input in advance. Means for calculating the total number of wiring channels. Also,
Wiring accommodating accuracy data extracting means for extracting wiring accommodating accuracy data based on the number of wiring pin pairs and the total number of wiring channels from a pre-registered wiring accommodating accuracy data file; And a comparing means for determining the wiring accommodability based on the accuracy data.

According to a fourth aspect of the present invention, the comparing means has an output function of outputting a result of the determination of the wiring storability in a report in a predetermined format.

In the present invention, the number of wiring pin pairs is calculated from the netlist of the logic circuit by the wiring pin pair number calculating means. The total number of wiring channels of the printed circuit board is calculated from the board data by the total wiring channel number calculating means. Thereafter, the wiring accommodation accuracy data is extracted from the wiring accommodation accuracy data file by the wiring accommodation accuracy data extraction unit based on the number of wiring pin pairs and the total number of wiring channels already calculated. Then, the comparing means determines the wiring accommodability based on the already calculated number of wiring pin pairs, total number of wiring channels, and wiring accommodating accuracy data.

According to the second or fourth aspect of the present invention, the result of the determination of the wiring storability is displayed or printed.

[0011] Accordingly, the above-mentioned object is to be achieved.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIG.
This will be described with reference to FIGS.

The printed board wiring storability evaluation apparatus shown in FIG. 1 is a wiring pin pair number calculating means 4 for calculating the wiring pin pair number P from a logic circuit netlist 1 created in advance.
And a total wiring channel number calculation means 5 for calculating the total wiring channel number N of the printed circuit board from predetermined board data 2 input in advance. Further, the wiring accommodating accuracy data K (K _P , K _N , K _S ) is extracted from the wiring accommodating accuracy data file 3 registered in advance based on the number of wiring pin pairs P and the total number of wiring channels N. The accuracy data extraction means 6, the number of wiring pin pairs P, the total number of wiring channels N, and the wiring accommodation accuracy data K (K _P , K _N ,
And a comparing means 8 for judging the wiring accommodability based on K _S ).

In the present embodiment, the comparing means 8
Is provided with an output function of outputting the result of the determination of the wiring storability in a report 9 in a predetermined format.

More specifically, in this embodiment, the netlist 1 is stored in an external storage device such as a magnetic disk device in advance. Here, the contents of the netlist 1 will be described later. The board data 2 is composed of factors such as the number of wiring layers of the printed board to be subjected to the evaluation of accommodability, the wiring grid interval, and the board size. For example, a value input from a keyboard is used. The wiring accommodation accuracy data file 3 is also stored in an external storage device such as a magnetic disk device in advance. Here, the contents of the wiring accommodation accuracy data file 3 will be described later.

The wiring pin pair number calculating means 4, the total wiring channel number calculating means 5, the wiring accommodability accuracy data extracting means 6, and the comparing means 8 are constituted by microcomputers and sequentially execute processing programs prepared in advance. By doing so, various processes are executed. The main memory 7 is a random access memory (RAM). The report 9 may be displayed on a display or printed out.

Next, an example of a logic circuit to be evaluated is shown in FIG.
Shown in Reference numerals C1 to C12, A1, and A2 in FIG. 2 indicate component names assigned to each component. The numbers 01 to 08 assigned to the components A1 and A2 respectively indicate pin numbers. Here, the pin numbers of the components C1 to C12 are 0, respectively.
Only 1 is assumed. Also, net_na written on the wiring
me1 to net_name11 each represent the net name of the wiring.

Next, FIG. 3 shows a description example of the netlist 1 based on the above-described logic circuit. In the description example of the net list 1, the first column 33 indicates a net name, the second column 34 indicates a component name, and the third column 35 indicates a pin number. In the netlist 1, a set of a component name and a pin number in a row in which a net name is described indicates a connection source of a wiring having the net name, and a component name and a pin number described in a row below the wiring indicate the connection name of the wiring. Indicates the connection destination. For example, code 31
Indicates that the connection source is the 01 pin of the component C1, and the connection destination is the 04 pin of the component A1 and the 04 pin of the component A2.

Subsequently, the wiring accommodation accuracy data file 3
8 is shown in FIG. Wiring storability accuracy data file 3
Includes a plurality of sets of the number of wiring pin pairs K _P , the total number of wiring channels K _N , and the wiring accommodation accuracy K _S as data acquired empirically based on the results of past printed circuit board design. .

Next, the overall operation of the above embodiment will be described.

When the apparatus is set to the operating state, the wiring pin pair number calculating means 4 calculates the wiring pin pair number P from the netlist 1 and stores it in the main memory 7. Further, the total wiring channel number calculating means 5 calculates the total wiring channel number N from the board data 2 and stores it in the main memory 107. Subsequently, the wiring accommodating accuracy data extracting means 6 reads the number P of wiring pin pairs and the total number N of wiring channels from the main memory 7, and from the wiring accommodating accuracy data file 3, optimal wiring accommodating data K ( K _P , K _N , and K _S ) are extracted and stored in the main memory 7. Then, the data P, N, K (K _P , K _N , K _S ) stored in the main memory 7 are compared by the comparing means 8 and a report 9 is output. The details will be described below.

First, the processing operation of the wiring pin pair number calculation means 4 will be described with reference to FIG.

First, the wiring pin pair number calculating means 4 initializes a variable P for storing the total value of the number of wiring pin pairs with O (step S41), and moves the pointer position on the net list 1 to the head of the net list 1. (Step S
42). Here, the head of the netlist 1 shown in FIG.
The net name net_name1 indicated by the reference numeral 31. Next, it is determined whether or not the pointer is positioned at the end of the net list 1 (step S43). If not, the number m of wiring pin pairs of the net name currently pointed to by the pointer is determined.
Is calculated (step S44). The number m of wiring pin pairs per one net name is represented by m = n−1, where n is the number of pins connected to the net (that is, the number of rows included per net name in the net list). . The variable P is updated with a value obtained by adding the wiring pin pair number n-1 to the previous value of the variable P (step S45).

For example, when the pointer is located at the position indicated by the reference numeral 31 which is the head of the netlist 1, there are three rows related to the net_name1 in the netlist 1, so that the number m of wiring pin pairs is 3-1 = 2, and P 2 is added.
Since the initial value of P is 0, P = 2.

Thereafter, the pointer is advanced to the line of the next net name (step S46). That is, the pointer is advanced to the position indicated by reference numeral 32 in FIG. Then, step S43
It is determined whether the pointer is positioned at the end of the netlist 1 or not. As a result, when the pointer is not positioned at the end of the netlist 1, the number m of wiring pin pairs is calculated for the net name newly indexed by the pointer, and the net name net_name2
5-1 = 4 is calculated as the number of pin pairs for the net. Then, m = 4 obtained this time is added to 2 which is the previous value of P and updated to P = 6. Thereafter, until the pointer is positioned at the end of the netlist 1, the processing of steps S44 and S45 is repeatedly executed. FIG.
In the example of the above, steps S44 and S44 are performed until the pointer moves after the net having the last net name net_name11.
45 is repeated.

On the other hand, if the pointer is at the end, P is stored in the main memory (step S47). In the example of FIG. 3, the total value of the number of wiring pin pairs calculated for each net is P =
17 is stored in the main memory 7.

Next, the processing operation of the total wiring channel number calculation means 5 will be described with reference to FIG.

As the board data 2, the horizontal length A [mm] of the printed board, the vertical length B [mm] of the printed board,
When the number C [lines] between pins representing the number of wires that can pass between pins and the number D of wiring layers, which is the number of layers that can be wired, are input from the keyboard (step S5).
1) The total wiring channel number calculation means 5 calculates the total wiring channel number N by the following equation (1) and stores it in the main memory 7.
In this embodiment, the length between the pins of the target printed circuit board is 2.54 [mm]. When the number of wiring layers D is 2, as shown in FIG. 6, the first surface of the printed circuit board (FIG.
(A)) and the second surface (FIG. 6 (b)) have channels orthogonal to each other.

[0029]

(Equation 1)

Here, the remainders of A / 2.54 and B / 2.54 are discarded. Also, in equation (1),
The portion shown in the following equation (2) represents the number of channels obtained by adding the number of channels in the vertical direction and the number of channels in the horizontal direction.

[0031]

(Equation 2)

The reason why 1 is reduced in each of the number of channels in the vertical direction and the number of channels in the horizontal direction is that wiring cannot be performed at the edge of the substrate.

Where A = 7.62, B = 7.62, C
= 3, D = 2, the total number N of wiring channels is calculated as in the following equation (3).

[0034]

(Equation 3)

Next, the processing operation of the wiring storability accuracy data extracting means 6 will be described with reference to FIG. The number P of wiring pin pairs and the number N of total wiring channels used in the following description are different from the numerical examples used in the above description for convenience. Therefore, it is unrelated to the above-described logic circuit of FIG. 2 and the netlist of FIG.

First, the wiring accommodation accuracy data extraction means 6
Reads the number P of wiring pin pairs and the total number N of wiring channels stored in the main memory 7. Then, a plurality of wiring accommodating accuracy data K (K _P , K _N , K _S ) that approximates the wiring pin pair number P is selected from the wiring accommodating accuracy data file 3 (step S71). Subsequently, from among the plurality of selected wiring accommodating accuracy data, the wiring accommodating accuracy data having the closest total number N of wiring channels is selected and extracted (step S7).
2). Then, the extracted wiring storability accuracy data is stored in the main storage unit 107 (step S73).

For example, if the number of wiring pin pairs P calculated from a predetermined netlist and board data is 1481 and the total number of wiring channels N is 4010, steps S71 and S7
8, the wiring accommodation accuracy data K (the number of wiring pin pairs K _P = 1500, the total number of wiring channels K _N = 4000,
The wiring accommodation accuracy K _S = 100%) is selectively extracted and stored in the main memory 7.

Next, the processing operation of the comparing means 8 will be described with reference to FIG.

The number of wiring pin pairs P, the total number of wiring channels N, and the wiring accommodation accuracy data K (K _P , K _N , K _S ) described above.
Are stored in the main memory 7, the comparing means 8 determines (the total number of wiring channels K _N ) / (the number of wiring pin pairs K _P ) based on the wiring accommodation accuracy data K (K _P , K _N , K _S ). And the value of (total wiring channel number N) / (wiring pin pair number P) based on the netlist and the board data (step S91). Then, the values of these two types (total number of wiring channels N) / (number of wiring pin pairs P) are compared with each other. As a result, the value of (total number of wiring channels N) / (number of wiring pin pairs P) based on the netlist and the board data is the wiring accommodation accuracy data K (K _P , K _N ,
If the value is equal to or larger than the value of (total number of wiring channels K _N ) / (number of wiring pin pairs K _P ) based on K _S , the wiring accommodation indicated by the wiring accommodation accuracy data K (K _P , K _N , K _S ) Accuracy K _S
It is determined that the wiring can be accommodated.

For example, in the above example, (the total number of wiring channels N) / (the number of wiring pin pairs P) based on the netlist and the board data is 4010/1481 = 2.71, and based on the wiring accommodation accuracy data K (the total The number of wiring channels K _N ) / (the number of wiring pin pairs K _P ) is 4000/150
0 = 2.67. Comparing these two calculation results, the value of (total number of wiring channels N) / (number of wiring pin pairs P) based on the netlist and the board data is larger,
The wiring accommodation accuracy K _S of the wiring accommodation accuracy data 81 is 10
Since it is 0%, it is determined that 100% of the wiring can be accommodated.

Subsequently, the comparison means 8 creates a report in a predetermined format and outputs the report (step S93). FIG. 10 shows a report output example.

As described above, according to the present embodiment, by inputting the board data of the printed circuit board, which is the basis of the evaluation of the accommodation, and the netlist of the logic circuit whose accommodation is to be evaluated, Since the storability of the logic circuit is determined and the possibility is output as a report, it is determined whether or not the wiring of the predetermined logic circuit can be accommodated on a printed circuit board having a predetermined number of wiring layers, a wiring grid interval, and a board size. Evaluation can be performed easily and reliably in a short time.

[0043]

According to the present invention, the number of wiring pin pairs is calculated from the netlist of the logic circuit, the total number of wiring channels is calculated from the board data, and registered in advance. The optimal wiring accommodating accuracy data for the logic circuit is extracted from the existing wiring accommodating accuracy data file, and the wiring accommodating is determined by comparing these data. It is possible to easily and reliably evaluate in a short time whether or not wiring of a predetermined logic circuit can be accommodated in a printed circuit board having the same.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a configuration diagram of an example of a logic circuit to be evaluated in the embodiment of FIG.

FIG. 3 is a configuration diagram showing a configuration example of a net list in FIG. 1;

FIG. 4 is a flowchart showing a processing operation of a wiring pin pair number calculation means in FIG. 1;

FIG. 5 is a flowchart showing a processing operation of a total wiring channel number calculation means 5 in FIG. 1;

FIG. 6 is a configuration diagram illustrating a configuration example of a printed circuit board layer;
FIG. 6A shows the first layer, and FIG. 6B shows the second layer.

FIG. 7 is a wiring storability accuracy data extracting means 6 in FIG.
5 is a flowchart showing the processing operation of the first embodiment.

8 is a configuration diagram showing a configuration example of a wiring storability accuracy data file in FIG. 1;

FIG. 9 is a flowchart showing a processing operation of a comparing means 8 in FIG. 1;

FIG. 10 is a configuration diagram showing an output example of a wiring storability evaluation report by the comparing means of FIG. 1;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Netlist 2 Board data 3 Wiring accommodating accuracy data file 4 Wiring pin pair number calculating means 5 Total wiring channel number calculating means 6 Wiring accommodating accuracy data extracting means 7 Main memory 8 Comparison means 9 Report 31 Net name net_name1 32 Net name net_name2 81 Wiring accommodability K (K _P , K _N , K _S ) Wiring accommodating accuracy data N Total number of wiring channels P Number of wiring pin pairs

Continuation of the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H05K 3/00 G06F 17/50

Claims (4)

(57) [Claims] The present invention calculates the number of wiring pin pairs from a net list of a logic circuit created in advance and calculates the total number of wiring channels of the printed circuit board from predetermined board data input in advance. Wiring accommodating accuracy data is extracted from the accuracy data file based on the number of wiring pin pairs and the total number of wiring channels, and the wiring accommodating ability is specified based on the number of wiring pin pairs, the total number of wiring channels, and the wiring accommodating accuracy data. A method for evaluating printed circuit board wiring accommodability, characterized in that: 2. The method according to claim 1, wherein the determination result of the wiring storability is output as a report in a predetermined format. 3. A wiring pin pair number calculating means for calculating the number of wiring pin pairs from a net list of a logic circuit created in advance, and a total wiring for calculating the total number of wiring channels of the printed circuit board from predetermined board data input in advance. Channel number calculation means, wiring accommodation accuracy data extraction means for extracting wiring accommodation accuracy data based on the number of wiring pin pairs and the total number of wiring channels from a wiring accommodation accuracy data file registered in advance, and the number of wiring pin pairs And a comparing means for judging wiring accommodability based on the total number of wiring channels and the wiring accommodability accuracy data. 4. The printed circuit board wiring accommodating evaluation apparatus according to claim 3, wherein the comparing means has an output function of outputting the result of the determination of the wiring accommodating ability in a report of a predetermined format.