JP2907412B2 - Dynamic logic status display method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention makes it possible to more easily understand signal propagation in a logic circuit, and to more effectively deal with problems such as timing errors such as competition and hazards and skew. The present invention relates to a method for displaying a dynamic logical state.

[0002]

2. Description of the Related Art A logic circuit including a plurality of logic gates for performing a logic operation includes a so-called asynchronous sequential circuit,
There is a so-called synchronous sequential circuit.

[0003] In this asynchronous sequential circuit, the output is determined not only by the present input but by the input and the past history of the sequential circuit, and when the state of the input or the sequential circuit changes, The output changes sequentially. At the time of designing such an asynchronous sequential circuit, attention must be paid to timing errors such as race conditions and hazards. When skew between a plurality of signals becomes a problem, skew adjustment is performed by delaying propagation of a predetermined signal.

On the other hand, the above-mentioned synchronous sequential circuit detects a change in the state of its output and, in some cases, a change in its internal state.
Synchronization is performed using a predetermined clock. For this reason, the design of the logic circuit is generally easier with the synchronous sequential circuit than with the asynchronous sequential circuit described above. However, even in such a synchronous sequential circuit, there is a case where skew becomes a problem at the time of clock distribution. In such a case, skew adjustment is performed by delaying a part of the distributed clock.

Conventionally, such problems as timing errors such as competition and hazards and skew have been generally dealt with based on, for example, the results of logic simulation. As a result of the logic simulation, if a problem such as the timing error or skew described above is found, for example, the waveform data obtained as a result of the logic simulation is converted into each node in each path using a predetermined waveform editor. It was to confirm about. Alternatively, by analyzing various log files obtained as a result of the logic simulation, each node in the path where a problem has occurred is confirmed. The log file records, for example, the timing error occurrence time and the like for each node in each path in ASCII format.

On the other hand, Japanese Patent Application Laid-Open No. 1-267778 discloses a large scale integrated circuit (LSI) in which graphic elements on a critical path are clearly displayed so that layout compression processing can be performed accurately and interactive processing work is facilitated. A technique relating to a layout display device is disclosed. In Japanese Patent Application Laid-Open No. 1-267778, first, a layout information storage means for storing layout information obtained by designing an LSI mask pattern, and a layout limit of an LSI design area are determined from layout information stored in the layout information storage means. And a critical path detecting means for detecting a critical path composed of an array of graphic elements for determining the critical path. Further, extracting means for extracting only graphic elements on the critical path detected by the critical path detecting means, layout information stored in the layout information storing means, and a graphic on the critical path extracted by the extracting means. Display means for displaying the element.
According to Japanese Unexamined Patent Application Publication No. 1-267778, it is possible to reduce the burden on the designer regarding the critical path in the layout compression processing.

[0007]

However, in any of the above-mentioned conventional techniques, it is relatively difficult to extract a problem location such as a timing error or a skew in a logic circuit under design.

[0008] For example, in the case of using a waveform editor as described above, or in the case of analyzing various log files, if the logic circuit under design is not understood in detail, efficient work is required. Was difficult to do. In addition, despite the fact that the data to be analyzed is generally large, most of the work is performed manually by the designer himself, which makes it difficult to perform the work efficiently. For this reason, there is also a problem that it takes a lot of time to find a problem location such as a timing error and a skew of the logic circuit under design. Incidentally, the above-mentioned Japanese Patent Laid-Open No. 1-2
In 67778, "critical path detection means"
However, the configuration is not disclosed at all.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems. The present invention makes it possible to more easily grasp signal propagation in a logic circuit, and to prevent timing errors such as competition and hazard, skew and the like. It is an object of the present invention to provide a dynamic logic state display method that can more effectively deal with a problem.

[0010]

According to the present invention, each net on a logic circuit diagram is divided and recognized into small nets by each input / output terminal and each branch point on the logic circuit diagram. The signal propagation speed on the wiring is obtained, the display change propagation speed on the display of each small net is obtained based on the signal propagation speed, and the display change propagation speed is calculated using the display change propagation speed. The object has been achieved by dynamically displaying the state of signal propagation on each wiring together with the logic circuit diagram.

In the above-mentioned dynamic logic state display method,
When determining the signal propagation speed, this is determined as the signal propagation speed for the net that includes the relevant small net, and when determining the display change propagation speed, the signal propagation speed of the net that includes each small net, By calculating the display change propagation speed of each small net based on the wiring length from the most input end of the net to the small net, particularly, the relationship between the wiring lengths of the wirings differs from the actual layout. As in the first embodiment described later, the above-described object is achieved even for a general logic circuit while making the display more natural.

In the above-mentioned dynamic logic state display method,
In advance, the expected signal propagation time and the normal timing relationship between the plurality of signals are grasped, and the observed signal propagation time obtained using the signal propagation speed and the expected signal propagation time are compared, While detecting an expected value matching error, comparing the observation timing relationship between a plurality of signals obtained using the signal propagation speed and the normal timing relationship,
By detecting the timing error and displaying the detection result of the expected value matching error and the detection result of the timing error together with the dynamic display, the above-described problem is achieved, and the problems of the timing error, the skew, and the like are achieved. The location can be more easily extracted.

[0013]

[Function] In recent years, in the situation where logic circuits of various electronic devices are integrated into circuits and the degree of integration of integrated circuits is being improved more and more, the work of designing integrated circuits and verifying the designed ones is increasing. It has become more difficult. The present invention has been made by focusing on such points. That is, the analysis is performed by analyzing the contents of such design work and verification work. As a result, it was found that the work of extracting the problem parts such as the timing error and the skew from the logic circuit under design took a lot of time and was a complicated work. It is.

Further, in order to more easily extract such a problem location such as a timing error and a skew, the present invention dynamically displays the logic state of a target logic circuit to reduce its efficiency. It has been found that it can be further improved. Therefore, the present invention has various procedures for dynamically displaying the logical state of a target logic circuit.

First, in the present invention, each net on a target logic circuit diagram is divided into small nets by each input / output terminal and each branch point on the logic circuit diagram. . Each of the nets in the above-described logic circuit diagram is a wiring that connects between an input / output terminal to the outside of the circuit in the logic circuit diagram and an input / output terminal of each of various logic gates in the logic circuit diagram. is there. In the present invention, such a net is divided and recognized as a small net as described above,
The dynamic logic state of the target logic circuit can be displayed effectively.

For example, when displaying the dynamic logic state of a logic circuit, it is conceivable to divide and recognize each net more finely. However, if the net is finely divided in this way, the amount of various processes for displaying the dynamic logical state increases, and the processing time increases accordingly. If such an increase in the processing amount or the processing time occurs, the display of the dynamic logic state of the target logic circuit cannot be realized at a practical display speed, or the processing device to be used may not be able to display the dynamic logic state. CPU (central proces
For the sing unit, etc., a more expensive one having a higher processing capability must be used.

On the other hand, for example, the division of each net into small nets may be recognized more coarsely. However, as the division becomes coarser, it becomes more difficult to dynamically and precisely grasp the logic state of the target logic circuit.

In view of the above, in the present invention,
As described above, each net is divided and recognized into small nets at least by each input / output terminal and each branch point on the target logic circuit diagram. In addition, in such a small net unit, at least the display change propagation speed representing the signal propagation in actually displaying the display to the user is grasped. In order to determine the display change propagation speed for each of the small nets, first, the signal propagation speed on the wiring is determined. Further, in actual display, even within such a small net, a state in which a signal propagates on a wiring is dynamically displayed based on the display change propagation speed.

Therefore, as described above, although the signal propagation speed and the display change propagation speed are grasped for each small net, the display of the signal propagation in the small net is represented by:
It can be displayed more smoothly and dynamically, and the user can more easily grasp the dynamic logic state.

The aforementioned signal propagation speed for each small net is a change speed of a signal propagating in the corresponding small net. Strictly speaking, the distribution of electrical resistance, capacitance, and inductance is not uniform even within one small net. A small net in an integrated circuit has a different capacitance with respect to its substrate depending on, for example, in which wiring layer it is built. Therefore, when the small net passes through a plurality of wiring layers, the distribution of the capacitance is not uniform. However, in the present invention, even if the signal speed propagating in each small net is defined as the signal propagation speed according to the average speed in the small net, it is large in terms of the display of the dynamic logic state targeted by the present invention. Find out that there is no problem.

On the other hand, as in the present invention, the speed at which a signal in a small net propagates is defined as a single value called a signal propagation speed, which is a representative value of the average, for obtaining a signal propagation speed. Based on the signal propagation speed, it is possible to reduce the amount of processing when the display change propagation speed is obtained or when a dynamic logic state is displayed. The signal propagation speed of the present invention can be obtained, for example, from the total resistance value, the total capacitance, and the like of the corresponding small net as in an embodiment described later. For example, in an embodiment described later, the signal propagation speed is obtained by a relatively simple mathematical formula.

In comparison, when the speed of signal propagation is determined in consideration of the distribution of resistance, the distribution of capacitance, the distribution of inductance, and the like in a net, various differential equations must be determined each time. Instead, the amount of calculation increases.

The display change propagation speed of the present invention is used when dynamically displaying the logical state of a target logic circuit based on the above-described signal propagation speed of the present invention. This is because, for example, even when the same small net is displayed, the display magnification may change when it is displayed. Furthermore, the ratio of the actual wiring length or the temporary wiring length on the integrated circuit layout of each small net to the length of the corresponding small net on the actually displayed logic circuit diagram on the drawing is determined by the logic circuit diagram. Because they are different. Further, such a ratio is different for each small net even in the same logic circuit diagram.

Therefore, in the present invention, when displaying the dynamic logic state in accordance with the signal propagation speed obtained for each small net, first, based on the signal propagation speed, the display of each small net is displayed. Is calculated. As a result, the amount of processing performed during the display of the dynamic logical state performed in real time during the display to the user can be reduced.

As described above, according to the present invention, the logic state of a target logic circuit can be dynamically displayed. Therefore, by utilizing such a display, the designer can more effectively find a timing error such as a conflict or a hazard or a problem location such as a skew.

The logic circuit dynamically displayed in the present invention is not limited to a normal logic circuit as in the first embodiment described later. That is, the same effects can be obtained even with logic circuit diagrams using various drawing methods.
For example, as in a second embodiment described later, an integrated circuit layout diagram may be used.

As described above, the signal propagation speed of the present invention and the display change propagation speed of the present invention need not be numerical values of the actual speed dimension as long as they can be used similarly. For example, the display change propagation speed is used to more effectively use the value of the signal propagation speed during dynamic logic state display. The display change propagation speed may be any coefficient of the displayed signal propagation speed with respect to the signal propagation speed. It goes without saying that the present invention is not limited to the units of the signal propagation speed and the display change propagation speed.

The signal propagation speed may be any as long as the display change propagation speed for each small net can be obtained.
It does not necessarily have to be for each small net. For example,
As in a first embodiment to be described later, it may be obtained for each net composed of a plurality of small nets.

In displaying the dynamic logic state of the present invention described above, other information is also displayed.
The present invention is not limited. For example, when various errors related to the display of the dynamic logic state of the target logic circuit, for example, timing errors such as conflicts and hazards and errors related to skew and the like occur, these may be displayed together. Such an error display has an effective synergistic effect with respect to the dynamic logic state display of the present invention in terms of extraction of a problematic part of a target logic circuit and the like.

[0030]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below in detail with reference to the drawings.

FIGS. 1 to 3 are flowcharts showing the processing contents of the first embodiment and the second embodiment of the dynamic logical state display device to which the present invention is applied.

In the dynamic logical state display device of the first embodiment, the target logical circuit is displayed by the dynamic logical state display method to which the present invention is applied as shown in the flowcharts of FIGS. In particular, while displaying the logic circuit diagram, the dynamic logic state is displayed. On the other hand, the dynamic logic state display of the second embodiment is shown in FIG.
In the dynamic logic state display method to which the present invention is applied as shown in the flowcharts of FIG. 3 to FIG. Is to do.

In the first embodiment shown in the flowcharts of FIGS. 1 to 3, furthermore, in a second embodiment to be described later, an expected value such as an expected signal propagation time registered in advance or a normal time According to a timing rule such as a timing relationship between a plurality of signals, an expected value collation error and a timing error in displaying a dynamic logic state are displayed. In this display, the location where the error occurred is displayed on the displayed logic circuit diagram or the displayed integrated circuit layout diagram, for example, in a highlight display, a flicker display, or the like.
Alternatively, it is performed by display using various colors. Also, by the option setting, it is possible to suspend the display of the dynamic logic state being executed simultaneously with the occurrence of such an error.

Further, in the first embodiment and a second embodiment to be described later, it is possible to effectively use the result of a simulation performed in advance, for example, error detection information obtained by the simulation. I have. That is, based on the error detection information registered in advance, for example, near the time of occurrence of an expected value collation error or timing error, the dynamic logic state is displayed at a low speed to grasp the situation of the occurrence of the error. In other cases, the dynamic logic state display is performed at a relatively high speed, and the work efficiency can be improved.

In the first embodiment, and also in a second embodiment to be described later, the dynamic logic state display device is provided with various data as listed below in advance.

(1) Data relating to a logic circuit diagram (in the case of the first embodiment) or integrated circuit layout data (in the case of the second embodiment) (2) Delay time data of each logic gate (each cell) (3) Data for calculating the signal propagation speed of each net or each small net (constants Kt and the like described later in the case of the first embodiment; signal propagation speeds of each wiring layer and the like in the case of the second embodiment) (4) Test pattern data and related data such as expected values such as expected signal propagation time and timing rules such as normal timing relationship (when simulation result analysis is performed)

First, the method of displaying a dynamic logical state according to the first embodiment will be described with reference to FIGS.

As described above, in the first embodiment, a dynamic logic state is displayed while a general logic circuit diagram described later with reference to FIG. 5 is displayed.

At this time, the size relationship of the virtual wiring length LNm (or the actual wiring length LNn) between the nets or between the small nets and the wiring length Ln in the general logic circuit diagram of FIG. May be different from each other. For example, although the virtual wiring length LN2 of the net N2 is longer than the virtual wiring length LN3 of the net N3, the wiring length L2 of the net N2 is shorter than the wiring length L3 of the net N3 on the logic circuit diagram. In some cases, it will.

As described above, the wiring length Ln on the logic circuit diagram
Of the virtual wiring length LNm between the nets and the small nets on the actual layout because the mutual relation between the nets and the small nets is different from each other. When a dynamic logical state is displayed on the diagram, the dynamic logical state may be very unnatural. For example, for a certain net that branches into a plurality of small nets, the display change due to signal propagation may be discontinuous.

Therefore, in the first embodiment, the following considerations are made.

(A1) The dynamic display of signal propagation for a certain net that branches sequentially from the most input end to a plurality of small nets is displayed as a signal that propagates sequentially and continuously from the most input end. (A2) It is assumed that as the number of branches of the small net from the most input end to the corresponding small net increases, the display change propagation speed representing signal propagation to the small net increases . (A3) Further, in order to simplify the processing contents and improve the display speed, for each net composed of a plurality of small nets, each signal delay from one most input end to a plurality of most output ends. Times are assumed to be equal to each other. (A4) Further, for the path from the most input end to the most output end where the number of the small net branches is the smallest in terms of display quality, the speed at which the display change indicating the signal propagation is transmitted, that is, the display change propagation speed is constant. And (A5) Similarly, in terms of display quality, on the path from the branch of the first small net from the most input end of the net to the most output end with the least number of small net branches, the display change. Let the propagation speed be constant.

Under such a premise, in the first embodiment, step 11 in the flowchart shown in FIG.
At 0, the signal delay time T is determined for each net. The signal delay time T is for obtaining the display change propagation speed of a small net included in the net. In this embodiment, the signal delay time T for each net is determined according to the total provisional wiring length of all the small nets included in the net, as described later.

When the signal delay time T of each net is obtained in this way, at step 112, the display change propagation speed used for actually performing the dynamic logic state display is obtained for each small net. . The display change propagation speed for each small net includes the signal delay time T (corresponding to the signal propagation speed of the present invention) of the net including each small net, and the wiring from the most input end of the net to the small net. They seek based on their length .

When the display change propagation speed of each small net is obtained in this way, based on this, step 1 is performed.
At 14, an initial state display to be displayed is first determined as the dynamic logical state display. This is determined according to the initial logic state of the logic circuit to be displayed.

Further, in step 116, error detection information for extracting a timing error such as a conflict or a hazard or a problem location such as a skew is acquired. The acquisition of the error detection information is performed based on, for example, a simulation result of a target logic circuit performed before this. The acquisition of the error detection information in step 116 is obtained before the processing shown in step 120 described below. Therefore, for example, it may be performed before the step 110.

When the initial state display is determined and the error detection information is obtained in this manner, step 12 in FIG.
A series of processes indicated by 0, 122, 124, and 126 are repeatedly executed at predetermined unit time intervals to display a dynamic logical state. That is, the logic state of the target logic circuit at every predetermined unit time and the state of signal propagation on the wiring are obtained and displayed.

In the step 120, if the unit time, for example, the error detection information obtained in the step 116 cannot be sufficiently obtained, the unit time is set to 10 ns in the present embodiment. On the other hand, if sufficient error detection information is obtained in step 116, the unit time is set to 1 ns near the time when the error occurs, and otherwise, the unit time is set to 100 ns.

When such a unit time elapses, in a succeeding step 122, a logical state display update process which will be described in detail later with reference to FIG. 2 is performed. After this, step 124
A logic circuit error detection process described later in detail with reference to FIG.

After the processing in steps 122 and 124, in step 126, it is determined whether or not the end time of the display of the dynamic logical state has come. Until the end time is determined in step 126, the processing described in steps 120, 122, and 124 described above is repeatedly executed for each predetermined unit time.

FIG. 2 is a flowchart showing the logical state display update processing of the first embodiment.

FIG. 2 shows the process shown in step 122 of FIG. In step 140 of FIG. 2, first, the logical state of each unit is determined.
In particular, the head position of the display change at that time is obtained.
That is, based on the display change propagation speed for each small net obtained in the step 112, a signal propagation state on a displayed logic circuit diagram, that is, a logic state on each wiring is obtained. It is. When the logical state on the logical circuit diagram and the head position of the display change according to the change are obtained in this way, next, in step 142, the actual display is updated based on this.

FIG. 3 is a flowchart showing a logic circuit error detection process in the first embodiment.

The logic circuit error detection processing shown in FIG. 3 corresponds to step 124 described above.

In step 160 of FIG. 3, among the error detection information obtained in step 116, the expected signal propagation time is used. The expected signal propagation time is a signal propagation time during normal operation. Therefore, by comparing the observed signal propagation time detected while displaying the dynamic logic state with the expected propagation time, an expected value collation error can be detected. If such an expected value collation error is detected, in the first embodiment, this is displayed on the displayed logic circuit diagram.

Subsequently, at step 162, a timing error is detected. This is performed based on the information regarding the normal timing relationship among the error detection information obtained in step 116. The information on the normal timing relationship is information indicating a timing relationship between a plurality of signals during a normal operation. In step 124, a logic circuit error that causes a timing error such as a conflict or a hazard is detected by comparing the observation timing relationship between a plurality of signals obtained at the time of displaying the dynamic logic state and the normal timing relationship.

Subsequently, in step 164, the expected value collation error detected in step 160 and the timing error detected in step 162 are displayed together with the logic circuit diagram being displayed. By displaying the expected value comparison error and the timing error, the user can more effectively find a timing error such as a conflict or a hazard or a problem location such as a skew.

FIG. 4 is a block diagram showing a hardware configuration used in the first embodiment.

As shown in FIG. 4, a dynamic logical state display device to which the dynamic logical state display method of the present invention is applied mainly has a CPU (central processing unit) 5.
0, main storage device 52, hard disk device 54,
Floppy disk device 58, input / output device 60, keyboard 62, CRT (cathode ray tube) controller 6
4a, a CRT 64b, and a system bus 70.

The CPU 50 executes the program module and the like according to the present embodiment in the main storage device 52 read from the hard disk device 54. The hard disk device 54 stores program modules, data, and the like according to the present embodiment, and is read out to the main storage device 52 as needed.

The optical disk device 56 is used for backing up program modules and data stored in the hard disk device 54. The floppy disk device 58 is used for transferring various program modules and data to and from other computer systems.

The input / output device 60 is connected with a mouse used for input operation by the user together with the keyboard 62. The keyboard 62 is used when operating the dynamic logical state display device. The keyboard 62 is also used for setting various data.

The CRT control device 64a is a bitmap display device, and can display not only characters such as numbers, but also figures and images on the CRT 64b. The C
The RT control device 64a displays, on the CRT 64b, a logic circuit diagram described later with reference to FIG. 5 and an integrated layout diagram described later with reference to FIG. 12 while mixing necessary characters. Can be.

The system bus 70 is connected to the CP
U50, the main storage device 52, the hard disk device 54, the optical disk device 56, the floppy disk device 58, the input / output device 60, the keyboard 62 and the CRT control device 64a when transferring data and the like. It is used for

FIG. 5 is a logic circuit diagram of an example of a logic circuit targeted by the first embodiment.

The logic circuit diagram shown in FIG. 5 shows an example of a target logic circuit and is actually displayed when a dynamic logic state is displayed. The logic circuit shown in FIG. 5 has a total of five logic gate instances I1 to I1.
I5. Hereinafter, these are respectively referred to as instances I1 to I5. The logic circuit composed of these instances I1 to I5 has input terminals A to
C, and the output terminals are D to G. or,
The small nets N1 to N7 are interconnected. One net is formed by the small nets N1 to N6. The small net N7 is one net.

The instance I1 is a NOR gate. Each of the instances I2 to I4 is an inverter gate. The instance I5 is a D-type flip-flop. The D-type flip-flop holds the D input at the rising edge of the clock input, outputs the D input as an output Q, and outputs an inverted version thereof as a Q bar output.

The operation of the first embodiment in the logic circuit shown in FIG. 5 will be described with reference to the flowcharts of FIGS.

First, as shown in step 110 of FIG. 1, the signal propagation speed, that is, the signal propagation speed T of the net including each small net is obtained. Specifically, the signal delay time Ta of the net constituted by the small nets N1 to N6 and the signal delay time Tb of the net constituted by the small net N7 are obtained by the following equations.

Ta = kt × (LN1 + LN2 + LN3 + LN4 + LN5 + LN6) (1a) Tb = kt × LN7 (1b)

In the above equations (1a) and (1b),
LN1 to LN7 are the small nets N1 to N7, respectively.
Is the virtual wiring length. The constant Kt is used for obtaining the signal delay time of the relevant net from the total virtual wiring length. The constant Kt is in accordance with the total capacitance and the like related to the total virtual wiring length.

As described above, the signal delay times Ta and Tb
Is obtained, the display change propagation speed is obtained as shown in the step 112 of FIG. 1 in accordance with the preconditions (A1) to (A5) described above. Based on these preconditions ( A1 ) to ( A5 ), the following relationship can be obtained. That is, multiple output from one input end
Assuming that each signal delay time to the end is equal to each other
From the precondition (A3 ), the following equation is obtained.

Ta = L1 / V1 + L2 / V2 = L1 / V1 + L3 / V3 + L5 / V5 = L1 / V1 + L3 / V3 + L4 / V4 + L6 / V6 (2a) Tb = L7 / V7 (2b)

In the above equations (2a) and (2b), L1 to L7 are the wiring lengths of the small nets N1 to N7 on the displayed logic circuit diagram when displaying the dynamic logic state. is there. V1 to V7 are the nets N1 to N
7 is the display change propagation speed. These displays change propagation velocity V1-V6, on the basis of the above-mentioned preconditions (A 4) ~ (A5) , further, it is possible to obtain the conditions as follows. That is, at the display change propagation speed V2
The net N2 reaching the most output end has the display change propagation speed V1.
Net N1 connected, output end at display change propagation speed V5
N5 leading to the display change propagation speed V3
3 and reaches the output end at the display change propagation speed V6.
The net N6 is connected to the net V4 having the display change propagation speed V4.
It is long.

V1 = V2 (3a) V3 = V5 (3b) V4 = V6 (3c)

Therefore, (2a), (2b) and (3a)
) To (3c), the display change propagation speeds V1 to V
7 can be obtained as in the following equation.

V1 = V2 = (L1 + L2) / Ta (4a) V3 = V5 = {(L1 + L2) × (L3 + L5)} / (L2 × Ta) (4b) V4 = V6 = ｛(L1 + L2) × (L3 + L5) ) × (L4 + L6)｝ / (L5 × L2 × Ta) (4c) V7 = L7 / Tb (4d)

From the above equations (4a) to (4d),
When the display change propagation velocities V1 to V7 of the respective small nets N1 to N7 are obtained, step 12 in FIG.
0, 122, 124, 126, and FIG. 2 and FIG.
As shown in (1), a dynamic logic state can be displayed. That is, it is possible to display the propagation state of the signal on the displayed logic circuit diagram at each elapsed time by the display change propagation speeds V1 to V7.

FIGS. 6 to 11 show the respective elapsed times t.
FIG. ₆ shows a dynamic logic state display of the logic circuit diagram of FIG. 5 at ₁ to t6.

In these FIGS. 6 to 11, for each net or each small net, those indicated by solid lines are as follows:
No signal is being propagated. The dashed line
"1", that is, the "H state" is in a state of propagation. A broken line indicates a state where “0”, that is, the “L state” is propagating.

First, in FIG. 6, "1" is input to the input terminal A.
Is input, and “0” is input to the input terminal B. The signal states of the other input terminals, nets, and small nets are undefined.

[0082] After a lapse of a predetermined unit of time from the time t _1, time
In t _2, as shown in FIG. 7, in accordance with an input of the input and the input terminal B of the input terminal A as described above, the output of the instance I1 is "0",
This propagates to the small net N1.

[0083] The output "0" of the instance I1, as shown in FIG. 8 to FIG. 10, according to the time t ₃ ~ t ₅ of each of the predetermined unit time, and propagates to the instance I3~I5 To go. On the other hand, FIGS.
As shown in (1), "0" is also input to the input terminal C, and is sequentially propagated to the instance I2 and the small net N7 on the output side of the instance I2.

In FIG. 10, "0" is input to the input D of the instance I5, which is a D-type flip-flop, and then "1" is input to the clock input CK of the instance I5. This is determined to be a timing error based on the error detection information (normal timing relationship) obtained in step 116 of FIG. As a result, the display of the instance I5 in FIGS. 10 and 11 is a thick line. The display of such a thick line indicates the detection of the timing error.

On the other hand, in FIG. 11, the propagation of the output of “1” of the instance I3 to which “0” is input is larger than the error detection information (expected propagation time) obtained in the step 116 of FIG. Because of the slowness, the display on the output terminal D indicates an expected value collation error. That is, the display of the output terminal D is flickering (blinking).

As described above, according to the present embodiment, the logic state can be dynamically displayed on the logic circuit diagram of the target logic circuit. It can be grasped more easily. Furthermore, since the expected value comparison error and the timing error can be displayed together with the error detection information acquired in advance,
It is possible to more effectively find a timing error such as a conflict or a hazard or a problem location such as a skew.

Hereinafter, a dynamic logical state display device according to a second embodiment of the present invention will be described. The dynamic logic state display device according to the second embodiment displays a dynamic logic state on an integrated circuit layout diagram of a target logic circuit while displaying it. The processing performed in the second embodiment is as follows.
The same processing as the processing shown in FIGS. 1 to 3 is performed. The processing of the second embodiment is partially different from the processing of the first embodiment in the processing in each step in the flowcharts of FIGS.

The target logic circuit is, for example, as shown in FIG. Also, what is displayed when the dynamic logical state is displayed in the second embodiment is shown in FIGS.
17 is an integrated circuit layout diagram as shown in FIG.
The integrated circuit layout diagrams of FIGS. 12 to 16 correspond to the logic circuit shown in the logic circuit diagram of FIG.

In FIG. 12, the hatched portions are the instances I1 to I5 shown in FIG. 5, respectively. Symbols A to G shown on the left side and lower side of FIG. 12 are the input terminals or output terminals shown in FIG. 5, respectively. In each of the small nets connecting the input / output terminals A to G and the instances I1 to I5, a first aluminum wiring layer is used for the horizontal wiring. On the other hand, the vertical wiring uses a second aluminum wiring layer. In addition, contacts are used as necessary to establish connections between the layers. In the integrated circuit shown in FIG. 12 of the second embodiment, the signal propagation speed VN on the actual device (on the virtual wiring) is as follows.

(1) In the first aluminum wiring layer,
Signal propagation speed on actual device = VNx (unit: μm /
ns) (2) Signal propagation speed on the actual device in the second aluminum wiring layer = VNy (unit: μm / ns) (3) Signal propagation speed on the actual device in the contact = VNz (unit: μm / ns)

Further, the signal propagation speed VN (V
Nx, VNy, VNz), the display change propagation speed V on the display at the time of dynamic logic state display is the ratio of the actual wiring length LN to the display wiring length L, that is, the display magnification R
Can be determined according to This is because the second embodiment displays a dynamic logic state on an integrated circuit layout diagram corresponding to a layout on an actual integrated circuit. For example, for a certain signal propagation velocity VN, the display change propagation velocity V can be obtained by the display magnification R and the following equation.

V = R × VN (5)

Here, assuming that the display magnification in the horizontal direction is Rx, the display magnification in the vertical direction is Ry, and the constant relating to the contact is Rz, the display change propagation speed Vx and the second The display change propagation speed Vy related to the aluminum wiring layer and the display change propagation speed Vz related to the contact can be expressed by the following equations.

Vx = Rx × VNx (first aluminum wiring layer) (5a) Vy = Ry × VNy (second aluminum wiring layer) (5b) Vz = Rz × VNz (contact) (5c)

Incidentally, assuming that the length of each contact is constant, the delay time associated therewith is as follows:
It is a constant as shown in the following equation.

Tz (constant) = Lz × Vz (delay time constant at contact) (6)

Thus, step 1 in FIG.
12, the display change propagation velocities Vx and Vy.
, Vz (Tz), the overall flow of the subsequent processing is the same as in the first embodiment. For example, when obtaining the head position of the display change as in the step 140 in FIG. 2, in the second embodiment, it may be performed on an integrated circuit layout diagram for displaying a dynamic logic state.

[0098] In FIG. 13, which corresponds to the dynamic logical status at the time t ₂ shown in FIG. 7 is shown. In FIG. 14, those of the time t ₄ when corresponding to FIG 9 is shown. FIG. 1
In FIG. ₅ , the one at the time t5 corresponding to FIG. 10 is shown. In FIG. 16, FIG.
Those of the time t _6, corresponding is illustrated in.

Note that, in FIGS. 15 and 16, the instance I5 is indicated by a dashed diagonal line going down to the right. This is a display of the timing error detection result as in the first embodiment. In FIG. 16, the output terminal D is indicated by a dashed hatched line on the upper right. This corresponds to the display of the detection result of the expected value collation error in the first embodiment.

As described above, in particular, in the second embodiment, the dynamic logic state is displayed on the displayed integrated circuit layout diagram according to the elapsed time, as shown in FIGS. It is possible to more easily grasp the signal propagation in the logic circuit. Further, as shown in FIGS. 15 and 16, it is possible to display the detection result of the expected value collation error and the detection result of the timing error, and to easily identify a timing error such as a conflict or a hazard or a problem point such as a skew. It is possible to grasp. In the two embodiments described above,
The application of the claims according to the present invention is as follows. That is, first, claim 1 relates to the first embodiment and the second embodiment.
And are applied together. Claim 2 is based on the description of A1 to A5 and
Applied in the first embodiment as described with respect to the
I have. In the second embodiment, claim 2 is not applied. Claim 3 is a flowchart of FIG.
As described in the description of the first embodiment, it is applied in the first embodiment.
ing. As described above with reference to the oblique lines in FIGS.
In the same manner as in the first embodiment to which claim 3 is applied,
Display the detection result of waiting value collation error and timing error
Is displayed in the second embodiment.
You.

[0101]

As described above, according to the present invention, signal propagation in a logic circuit can be more easily grasped, and timing errors such as competition and hazard, and problems such as skew can be more effectively achieved. An excellent effect that can be dealt with.

[Brief description of the drawings]

FIG. 1 is a flowchart showing an operation of a dynamic logical state display device according to a first embodiment and a second embodiment to which the present invention is applied;

FIG. 2 is a flowchart showing a logical state display update process in the first embodiment and the second embodiment.

FIG. 3 is a flowchart showing a logic circuit error detection process in the first embodiment and the second embodiment.

FIG. 4 is a block diagram showing a hardware configuration of the first embodiment and the second embodiment.

FIG. 5 is an example of a logical circuit diagram displayed when displaying a dynamic logical state according to the first embodiment.

FIG. 6 shows a dynamic logic state display (time t) in the first embodiment.
₁ ) Diagram showing an example

FIG. 7 shows a dynamic logic state display (time t) in the first embodiment.
₂ ) Diagram showing an example

FIG. 8 shows a dynamic logic state display (time t) in the first embodiment.
₃ ) Diagram showing an example

FIG. 9 shows a dynamic logic state display (time t) in the first embodiment.
₄ ) Diagram showing an example

FIG. 10 shows a dynamic logical state display (time
diagram showing an example of a t ₅₎

FIG. 11 shows a dynamic logical state display (time
Diagram showing an example of t ₆ )

FIG. 12 is a diagram showing an example of a layout diagram of an integrated circuit displayed when displaying a dynamic logic state in the second embodiment.

FIG. 13 shows a dynamic logic state display (time
Diagram showing an example of t ₂ )

FIG. 14 shows a dynamic logical state display (time) in the second embodiment.
Diagram showing an example of t ₄ )

FIG. 15 shows a dynamic logical state display (time) in the second embodiment.
diagram showing an example of a t ₅₎

FIG. 16 shows a dynamic logic state display (time
Diagram showing an example of t ₆ )

[Explanation of symbols]

 50: CPU 52: Main storage device 54: Hard disk device 56: Optical disk device 58: Floppy disk device 60: Input / output device 62: Keyboard 64a: CRT control device 64b: CRT A to C: Input terminals D to G: Output terminals I1 ... I5 ... Logic gate instance N1-N7 ... Small net

Claims (3)

(57) [Claims] 1. Each net on a logic circuit diagram is divided and recognized as a small net by each input / output terminal and each branch point on the logic circuit diagram, and signal propagation of each small net on a wiring is performed. The speed is determined. Based on the signal propagation speed, the display change propagation speed on the display of each small net is determined. Using the display change propagation speed, a signal is propagated on each wiring on the logic circuit diagram. A dynamic logic state display method, wherein a state is dynamically displayed together with the logic circuit diagram. 2. The method according to claim 1, wherein when the signal propagation speed is obtained, the signal propagation speed is obtained as the signal propagation speed relating to a net including the corresponding small net. Determining the display change propagation speed of each small net based on the signal propagation speed of the included net and a wiring length from the most input end of the net to the small net. Method. 3. The method according to claim 1, wherein an expected signal propagation time and a normal timing relationship between a plurality of signals are previously grasped, and an observation obtained using the signal propagation speed is obtained. A signal propagation time is compared with the expected signal propagation time to detect an expected value matching error, and an observation timing relationship between a plurality of signals obtained using the signal propagation speed is compared with the normal timing relationship. And detecting a timing error, and displaying the detection result of the expected value collation error and the detection result of the timing error together with the dynamic display.