JP2829120B2 - Data transmission circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Purpose of the Invention] (Industrial application field) The present invention is, for example, a data transmission which is periodically used for broadcasting from each station of a local area network to reduce a load on a CPU. Circuit.

(Prior Art) A conventional data transmission circuit will be described with reference to FIG.

The CPU 33 sets a transmission cycle to a timer (not shown) and sets a block number to be transmitted to the memory 35. The block number is a number indicating the block obtained by dividing the common memory 37 into a plurality of blocks. When an interrupt is requested from the timer, the CPU 33 reads the block number to be transmitted from the memory 35 and calculates the real address of the block number on the common memory 37. The CPU 33 sets the calculated real address and the number of transmission data in the transmission circuit 39, and outputs a transmission request to the transmission circuit 39. When transmission becomes possible after the transmission request, the transmission circuit 39 reads the data for the number of pieces of transmission data indicated by the real address from the common memory 37 indicated by the real address, and transmits the data to the transmission line 41. After transmission is completed, CP
U33 reads the block number from memory 35 and
The above operation is repeated until there are no more blocks stored in.

As a transmission system including the data transmission circuit,
Block k of common memory 37 of station A shown in the figure
Is transmitted via the transmission line 41, the data of the block k of the common memory 37 of the stations B to Z is updated. In the above-described circuit, it was not easy to suppress an increase in the load on the CPU when the transmission cycle became faster.

(Problems to be Solved by the Invention) By the way, conventionally, the transmission process is executed every time there is an interrupt from the timer. Therefore, if an interrupt request from the timer occurs frequently, the CPU 33 makes the transmission cycle faster, Since the time spent for the processing increases, other processing, for example, data reading or writing, becomes impossible, and there is a possibility that the processing capacity of the apparatus may be reduced.

The present invention has been made in view of the above, and an object of the present invention is to provide a scan transmission method (each station has a common memory, each of which is divided into a plurality of blocks and assigned to each station. Each station writes the required data in the block assigned to the own station in the common memory of the own station and transmits the data, and the other stations receiving the transmission data transmit the contents of the corresponding block in the common memory of the own station. A data transmission circuit that automatically controls the transmission of the common memory of each station so that it can always be updated to the latest data without CPU intervention. To provide.

[Means for Solving the Problems] To achieve the above object, the present invention relates to a data transmission circuit arranged in each station of a scan transmission type local area network, wherein a plurality of storage spaces are provided. Is divided into blocks, and an actual address is assigned to each block, a common memory in which transmission data is stored for each block, a counter that counts the number of times the transmission data is transmitted in the block unit, Among a plurality of blocks of the common memory, a storage unit that stores a block number corresponding to each of the blocks in which the transmission data is stored in accordance with an instruction from a CPU provided in the station, Each block of the common memory corresponding to each block number Address generation means for generating a real address attached thereto, a timer for determining a period for transmitting data, and when the timer expires, the storage is performed until the count of the counter reaches a predetermined value. The transmission data stored in each block in the common memory corresponding to the real address generated by the real address generation means corresponding to each block number stored in the means is sequentially transmitted through the transmission line of the local area network. And transmission control means for transmitting to.

(Operation) In the data transmission circuit having the above configuration, the storage unit stores the block numbers corresponding to the real addresses of the blocks storing the transmission data among the plurality of blocks of the common memory. The real address of the common memory corresponding to the block number stored in the memory is generated by the address generation means, and when the timer for determining the data transmission cycle times out, the transmission control means counts the number of data transmissions. Until the count number of the counter reaches a predetermined value, the transmission data stored in the block in the common memory corresponding to the real address generated by the real address generation means corresponding to each of the block numbers stored in the storage means Are sequentially transmitted to the transmission path of the local area network. This allows the data transmission circuit to transmit data to other stations without the intervention of the CPU, thereby preventing an increase in the load on the CPU and improving the processing capability of the device.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing one embodiment according to the data transmission circuit of the present invention.

The data transmission circuit 1 includes a storage circuit 3, a real address generation circuit 5, and a timer 7.

In the storage circuit 3, a block number to be transmitted is set.
The port 7 is a port memory. The real address generation circuit 5 is a circuit that generates a real address of a common memory 19 of a corresponding block from a block number stored in the storage circuit 3, and a timer 7 determines a transmission cycle. Things.

The data transmission circuit 1 includes a transmission number counter 9, a control circuit 11, and an arbitration / switching circuit 13.

The transmission number counter 9 is a counter that counts the number of times data is transmitted, and the count value (output value) indicates an address of the storage circuit 3.

When the timer 7 times out, the control circuit 11 outputs the real address generated by the real address generation circuit 5 and the number of transmission data of the block to be transmitted to the transmission circuit 21 described later, and resets or counts up the transmission number counter 9. Run.

The arbitration / switching circuit 13 switches the access of the transmission circuit 21 to the control circuit 11 or a CPU 15 described later.

FIG. 2 is a block diagram showing a configuration of a station of, for example, a local area network provided with the data transmission circuit 1.

The above-mentioned station includes a CPU 15,
The memory 17 includes a memory 17, a common memory 19, and a transmission circuit 21.

The CPU 15 controls the entire station, the memory 17 is a memory for storing programs such as the operation of the CPU 15, and the common memory 19 is a memory having contents common to each station. It is divided into a plurality of blocks, and a real address is assigned to each block. The transmission circuit 21 is a circuit that transmits data such as a block number to the transmission path 23 in response to a transmission request from the control circuit 11 or the CPU 15 of the data transmission circuit 1.

FIG. 3 is a diagram showing the storage circuit 3, in which a block number (block No.) P is set at an address "0" of a head address, a block number Q is at an address "1", and a block number R is at an address "2". Are set, and thereafter, block numbers are sequentially set. After setting the block number in the storage circuit 3, the CPU 15 sets a period to be transmitted to the timer 7 and starts transmission. At this time, the initial value of the transmission number counter 9 is “0”, and the initial value “0” is stored in the storage circuit 3.
Of the block group to be transmitted.

FIG. 4 shows the block numbers of the storage circuit 3 and the common memory 19.
FIG.

At present, the counter value of the transmission number counter 9 points to the block No. P of the storage circuit 3 at the address “0”. The real address generation circuit 5 uses the block No. P as a common memory.
Generate the real address on 19. The area indicated by the real address is a block P of the common memory 19.

 Next, the operation of the present embodiment will be described.

First, after power is supplied to the circuit, the arbitration / switching circuit 13 switches to the control circuit 11 side, and then the CPU 15 sets a block number to be transmitted from the top address of the storage circuit 3.
The CUP 15 sets the number of transmission data of a block to be transmitted to the control circuit 11, and the control circuit 11 stores the number of transmission data in an internal register. Then, the CPU 15 sets a transmission cycle in the timer 7 and starts transmission.

At the start of transmission, the initial value of the transmission counter 9 is “0”, and the block No.
Point to. The real address generation circuit 5 generates a block No. P at a real address on the common memory 19 and outputs it to the control circuit 11. When the timer 7 times out, the control circuit 11 starts transmission control, and sends the real address input from the real address generation circuit 5 and the number of transmission data stored in an internal register (not shown) to the transmission circuit 21. Set and notify the transmission request. After notifying the transmission request, the transmission circuit 21
When 23 becomes available for transmission, the common memory indicated by the real address 19
The data of the upper block P is transmitted to the transmission path 23.

After transmitting the data in the block P, the control circuit 11 counts up the transmission number counter 9 and the count value of the transmission number counter 9 indicates the address “1” of the storage circuit 3.

The above operation is repeated until the block No. set in the storage circuit 3 is exhausted, or until the number reaches the predetermined number set in the system. Set block No.
When the transmission has disappeared or when the transmission has been completed the predetermined number of times, the control circuit 11 resets the transmission number counter 9 and resets the timer 7
Waits until counts up. Then, the transmission right is passed to the same data transmission circuit of the next station.

As a result, data control can be performed without the intervention of the CPU 15, and even if the transmission cycle becomes faster, the CPU 1
Since transmission becomes possible without increasing the load of 5, the processing capability of the device can be improved.

In this embodiment, when a pointer indicating a real address is set in the storage circuit 3, the real address generation circuit 5 can be omitted.

Next, another embodiment of the present invention will be described with reference to FIGS.

First, when the transmission cycle of the block set in the storage circuit 3 is given a priority for the high-speed cycle, the medium-speed cycle, and the low-speed cycle, as shown in FIG. It includes a counter 25a and the like. That is, the switching circuit 31 is provided with a transmission cycle counter 25a for a high-speed cycle and a timer 27a. The medium frequency cycle includes a transmission counter 25b, a timer 27b, and an address offset circuit 29b. The low frequency cycle includes a transmission counter 25c, a timer 27c, and an address offset circuit 29c, and is connected to the switching circuit 31. The above address offset circuit
29b and 29c have offsets 1 and 2 with respect to the output values from the transmission number counters 25b and 25c. As a result, the storage circuit 3 shown in FIG.
Set block No.Q to No.P and the next address, block No.S to the top address for middle speed cycle, and block to the next address
Set No.T and set block N at the start address for the low-speed cycle.
oU, block No.V is set to the next address.

The control circuit 11 detects the cycle of the block to be transmitted and outputs a control signal to the switching circuit 31 so that the control circuit 11 sends the control signal to the storage circuit 3 based on the address values input from the high-speed cycle, the medium-speed cycle, and the low-speed cycle. The address is switched. The block number read from the storage circuit 3 is generated at the real address by the real address generation circuit 5, and the transmission circuit 21
Is transmitted to the transmission path 23 via the.

As a result, even when there is a priority in the transmission cycle for each block, processing can be performed efficiently without imposing a load on the CPU.

[Effects of the Invention] As described above, according to the present invention, the CPU of each station firstly transmits data to the data transmission circuit of the present invention.
Writes its own processing result to the corresponding block of the common memory as transmission data, and at the same time stores the block number corresponding to each block of the common memory in the storage circuit, and indicates how much data to transmit Then, if the data transmission control of the present invention is left to the data transmission control side, the data transmission circuit of the present invention obtains an address on the common memory corresponding to the block number designated by the CPU in advance, and obtains the address block. Can sequentially transmit data stored in the transmission path to the transmission path, preventing an increase in the CPU load and improving the processing capacity of the device even when the data transmission cycle is fast. it can.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment of a data transmission circuit of the present invention, FIG. 2 is a block diagram showing an apparatus provided with the data transmission circuit of the present invention, FIG. FIG. 4 is a diagram showing the relationship between the block number of the storage circuit and the common memory, FIGS. 5 and 6 are diagrams showing another embodiment of the present invention, and FIGS. 7 and 8 are diagrams showing a conventional example. It is. 1 Data transmission circuit 3 Storage circuit 5 Real address generation circuit 7 Timer 9 Transmission counter 11 Control circuit

Claims (1)

(57) [Claims] 1. A data transmission circuit installed in each station of a scan transmission type local area network, wherein a storage space is divided into a plurality of blocks, a real address is assigned to each block, and A common memory in which transmission data is stored, a counter that counts the number of times the transmission data is transmitted in the block units, and a plurality of blocks of the common memory, each of which corresponds to a block in which the transmission data is stored. CPU number provided to each station
Storage means for storing in accordance with an instruction from the storage means, address generation means for generating a real address assigned to each block of the common memory corresponding to each of the block numbers stored in the storage means, and a cycle for transmitting data And when the timer times out, the real address generation means generates the real address generation means corresponding to each of the block numbers stored in the storage means until the count number of the counter reaches a predetermined value. A transmission control means for sequentially transmitting transmission data stored in each block in the common memory corresponding to a real address to be transmitted to a transmission path of the local area network.