JP2829907B2 - Jitter addition device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention can be used to artificially generate, for example, jitter generated in various types of reproducing devices or jitters generated in a transmission line and to test a jitter removing circuit or the like. The present invention relates to a jitter adding device that can be used.

[0002]

2. Description of the Related Art For example, when a signal is reproduced from a compact disk or a magnetic tape, or when a signal is transmitted and received through a transmission path, jitter occurs. These jitters are removed by a jitter removing circuit to be reproduced as high quality signals. For example, to measure the jitter removal rate of a jitter removal circuit, a signal containing a predetermined jitter is required. For such a purpose, a jitter adding device is used, a specified jitter is added to the pulse train by the jitter adding device, and various tests and measurements are performed using the pulse train to which the jitter is added.

FIG. 5 shows a configuration of a conventional jitter adding apparatus. In the figure, reference numeral 11 denotes a retiming flip-flop.
A pulse train PA (FIG. 6A) to which jitter is added is input to a data input terminal D of the retiming flip-flop 11, and a trigger signal TS generated from a clock PB (FIG. 6B) is input to a trigger input terminal. The delay time of the trigger signal TS is modulated in the variable delay circuit 12, and as a result, a pulse train with jitter added to the output terminal Q is output.

That is, the clock PB is a fixed delay element DL
Thus, the fall timing is set so as to be located at the center of the pulse train PA, and is provided to the variable delay circuit 12. As shown in FIG. 7, for example, the variable delay circuit 12 includes a resistance circuit 12A and a variable capacitance element 12B such as a varicap.
By applying a modulation signal such as a sine wave, sawtooth wave, or random wave from any one of the oscillators 15, 16, and 17 to the variable capacitance element 12B,
The delay time of the variable delay circuit 12 changes according to the waveforms of these modulation signals, and various patterns (waveforms) are included in the trigger signal TS.
Is given. Trigger signal T including this jitter
The pulse train PA is retimed by S, and jitter is added. Thus, the waveform of the jitter fluctuation, the width (amplitude) of the fluctuation, and the repetition frequency of the fluctuation are determined by the oscillator 15,
It is determined by the modulation signals provided from 16 and 17. For this purpose, a changeover switch SW is provided, and the modulation signal supplied to the variable delay circuit 12 can be selected by switching the changeover switch SW. 18 is each oscillator 1
A controller for setting and controlling oscillation frequencies, amplitudes, and the like of 5, 16, and 17 is shown.

[0005]

According to the jitter adding apparatus shown in FIG. 5, an oscillator is required for each type of waveform, and the efficiency is low. To control the oscillation frequency, amplitude, etc. of each of the oscillators 15, 16, 17
Switch elements such as resistors and capacitors used for
Since a configuration such as changing a constant is required, there is a disadvantage that the circuit scale is increased and the cost is increased.

An object of the present invention is to provide a jitter adding apparatus which can switch the waveform, amplitude and repetition frequency of jitter to be added with a simple configuration.

[0007]

According to the present invention, jitter is reduced.
The pulse train to be added is given to the data input terminal,
Trigger signal whose phase changes in the desired pattern
And retiming flip-flop issue is input, Pal
In synchronization with the pulse train, a clock with a frequency that is an integer multiple
The frequency multiplier that generates the lock and the frequency-multiplied clock
The lock is counted and the frequency is multiplied within the period of the pulse train.
Divide by the lock cycle, and place the
A counter that outputs count data indicating the
Numeric data in the form corresponding to the count data output by the printer
The counter changes the carry signal for each output and outputs
Phase data generating means and counting data output by the counter.
Value and the value of the numerical data output by the phase data generation means
Match is detected, and the match detection timing is reset.
Supply to trigger input terminal of imming flip-flop
And a coincidence detecting circuit .

According to the present invention, one cycle of a pulse train to which jitter is added is divided into N equal parts, and each of the divided parts is divided into N equal parts.
In each section , a trigger signal is generated in each section each time the phase data matches the phase data output from the phase data generating means. By properly setting the phase data output from the phase data generating means, the waveform, repetition frequency and amplitude of the jitter can be selected.

Therefore, according to the present invention, by preparing various types of phase data, the waveform of the jitter, the repetition frequency, and the amplitude can be freely selected. The added jitter can be added.

[0010]

FIG. 1 shows an embodiment of the present invention. In FIG. 1, reference numeral 10 denotes a retiming flip-flop, and DL denotes a fixed delay element. In this example, as shown in FIG. 2B, a case is shown in which the fixed delay element DL is provided to match the timing of each falling edge of the clock PB with the start timing of each half cycle of the pulse train PA.

According to the present invention, the fixed delay element DL
A clock having a frequency of 2 ^{N which} is an integral multiple of the frequency of the pulse train PA
Frequency multiplier 21A that generates the
Counts clocks and multiplies frequency within the period of pulse train PA
Divided by the period of the divided clock, and the position is set for each divided section.
And a counter 21B for outputting count data representing
You. In this example, a case where N = 3 is selected as the multiplier 2 ^N of the multiplier 21A will be described. By selecting N = 3, the clock PC having a frequency eight times the frequency of the clock PB
(FIG. 2C), and one cycle T of the clock PB is reduced to １ ／ by the clock PC having the frequency eight times the frequency.
Can be divided at a resolution of

The clock PC converted to an eight-fold frequency by the multiplier 21A is input to an N-bit binary counter 21B and counted by the N-bit binary counter 21B. The N-bit binary counter 21B has N = 3
If has three output terminals D ₀ to D _2, sequentially counted value to the output terminal D ₀ to D ₂ are output. At the same time, a carry output signal CY is output to the carry output terminal C.

This carry output signal is supplied to the phase data generating means 2.
2 given. The phase data generating means 22 can be constituted by an M-bit address counter 22A and a storage unit 22B accessed by an address signal output from the M-bit address counter 22A.
Here, assuming that selected in M = 3, the address counter 22A has three output terminals D ₀ to D _2, and outputs the count value to the three output terminals D ₀ to D _2.

FIG. 2D shows an N-bit binary counter 21B.
Shows the carry signal CY. Each time one carry signal CY is output, the address signal (FIG. 2E) output from the address counter 22A is 0, 1, 2, 3, 4,.
It changes to 2,3 ... FIG. 2F is stored in the storage device 22B.
Shows numerical data. Numerical values 4, 5, 4, 3, shown in FIG.
2, 1,... Are divided by the frequency-multiplied clock.
Corresponding to the position of each section was divided. That is, it corresponds to the count data output from the N-bit binary counter 21B.

[0015] Counting de indicating the numerical data that is read from the storage unit 22B, each section output from the counter 21B
Given the over data to the coincidence detecting circuit 23, the count value is the phase data of the coincidence detecting circuit 23 counter 21B generator 2
2 is output from the phase data generating means 22 by providing the coincidence detection output (FIG. 2H) to the trigger input terminal T of the retiming flip-flop 10 through the AND gate 24 when the numerical data coincides with the numerical data output from 2
The retiming flip-flop 10 can be triggered at a timing position defined by numerical data, and the output PJ (FIG. 2J) of the retiming flip-flop 10 can be inverted.

In the example shown in FIG. 2, the numerical data is 4,
5, 4, 3, 3, 2, 1, 2, 3, 4, 5,... Therefore, the coincidence detection circuit 23 calculates the position of the section 4, the position of the section 5, the position of the section 4, the section 3, the section 2,
Section 1, section 2, coincidence detection outputs at each section of the section 3 (Fig. 2
H). This match detection output is output to the AND gate 24.
And a part PI of the clock PC output from the multiplier 21A is taken out by the AND gate 24, and this signal P
I (FIG. 2I) to the trigger input terminal T of the retiming flip-flop 10, the signal P shown in FIG.
J can be obtained.

The signal PJ leading and trailing edge sections 1 and 2 are advanced phase around the section 3, section 4 and 5 can be a phase lag. FIG. 2K shows an equivalent waveform of the jitter added to the signal PJ. This example shows a case where the amplitude of the jitter fluctuation is 5-1 = 4 units, and a jitter whose phase changes like a triangular wave having a period of 8 clocks PB is added. In addition,
The amplitude of the jitter fluctuation is obtained by subtracting the minimum value from the maximum value of the phase data stored in the storage unit 22B. When the amplitude of jitter fluctuation is N = 3, one unit of amplitude = period of external clock PB ÷ 2 ³ , that is, if the period of external clock PB is 1 μs, one unit of amplitude is 125 ns in time conversion.

Storage device 2 constituting phase data generator 22
2B can be constituted by a RAM, for example.
The phase data can be rewritten by configuring the storage device 22B with a RAM. Reference numeral 25 denotes a controller (microcomputer) for rewriting the storage contents of the storage device 22B. An external memory 26 is connected to the controller 25, and numerical data having various patterns is prepared in the external memory 26, and the numerical data prepared in the external memory 26 is required. By writing to the storage device 22B according to
Jitter having various waveforms, amplitudes, and repetition frequencies can be generated.

In the following, various numerical data are stored in the storage 22B.
Here, an example in the case where the information is stored is shown. 3 stores the numerical data 0 in the first address 0 of the memory unit 22B, stores the numerical data 1 to the second address 1, stores the numerical de <br/> over data 2 to the third address 2, the 4 Numerical data 3 is stored at address 3, numerical data 4 is stored at fifth address 4, and numerical data 5, 6, 7 are similarly stored at addresses 5, 6 and 7.
Is stored. In this case, the match detection output output from the match detection circuit 23 is output as shown in FIG. 3B, and the trigger signal shown in FIG. 3C is output from the AND gate 24. As a result, the output PJ of the retiming flip-flop shown in FIG. 3D is obtained. The equivalent waveform of the jitter in this case has an amplitude of 7 units as shown in FIG.
The period becomes a sawtooth shape of 8 clocks PB.

As is apparent from these two cases, by preparing various types of phase data output from the phase data generating means 22, it is possible to easily change the jitter waveform, amplitude and repetition frequency. FIG. 4 shows various phase data and equivalent waveforms of jitter when N = 4 and M = 4. By setting N = 4, ^2N multiplier 21A (FIG. 1)
Multiplies the clock PB by 16. Therefore, in this case, the pulse train PA is subdivided into 1/16 of a half cycle. Further, the phase scanning means 21 has four output terminals, and the storage device 22 constituting the phase data generating means 22
B has 16 addresses and 4 output terminals.

FIG. 4A shows a data change point, and FIG. 4B shows addresses of a storage unit 22B constituting the phase data generating means 22. FIG. 4C shows 0, 2, 4, 6, 8, A (10), C (12), and C as phase data at each address of the storage 22B.
The case where E (14) is written is shown. When such phase data is written in the storage unit 22B, the equivalent waveform of the jitter has a sawtooth shape. At this time, the fluctuation width of the jitter (the amplitude of the sawtooth wave) is E-0 = 14 units and the period is 8 addresses.

FIG. 4D shows addresses 0 to 7 as numerical data.
Shows the case where 4, 5, 6, 7, 8, 9, A, and B are stored in FIG. In this case, the jitter has a sawtooth width of B-4 = 7 units and a period of 8 addresses. FIG. 4E shows numerical data at addresses 0 to F at 0, 1, 2, 3,.
This shows a case where F is stored. In this case, the fluctuation width of the jitter is F-0 = 15 units and the period is 16 addresses.

FIG. 4F shows a case where 1, 5, 9, and D are stored as numerical data at addresses 0 to 3. In the case of such a configuration, the fluctuation width of the jitter is 12 units and the cycle is 4 addresses. As described above, according to the present invention, the jitter fluctuation width, the waveform, and the repetition frequency can be defined according to the numerical data. In the above, N = 3, M = 3
The case where N = 4 and M = 4 has been described as an example, but it is practical to adopt N = 8 and M = 8 when practically used. At this time, the resolution is 1/128. By setting the resolution to this level, the jitter waveform becomes sinusoidal,
Alternatively, various waveforms such as a random waveform can be generated.

[0024]

As described above, according to the present invention, various types of numerical data are prepared in the external memory 26, and the numerical data is stored in the storage 22B constituting the phase data generating means 22 from the external memory 26. The waveform of the jitter, the period and the fluctuation width can be freely changed only by transferring.

Therefore, various types of jitter can be generated with a simple configuration. In this respect, it is possible to provide an inexpensive jitter adding apparatus capable of generating various kinds of jitters, and the effect is extremely large for practical use.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a waveform chart for explaining the operation of the present invention.

FIG. 3 is a waveform diagram similar to FIG. 2;

FIG. 4 is a waveform chart for explaining an operation when conditions are different from those in FIG. 2;

FIG. 5 is a block diagram for explaining a conventional technique.

FIG. 6 is a waveform chart for explaining the operation of the conventional technique.

FIG. 7 is a connection diagram showing an example of a variable delay circuit used in a conventional technique.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Retiming flip-flop 21 Phase scanning means 22 Phase data generation means 23 Match detection circuit 25 Controller 26 External memory

Claims (1)

(57) [Claims] 1. A. First Embodiment B. a retiming flip-flop in which a pulse train to which jitter is to be applied is given to a data input terminal and a trigger signal whose phase changes in a desired pattern is input to the trigger input terminal; The frequency of the pulse train is adjusted in synchronization with the pulse train.
B. a frequency multiplier for generating a clock having a frequency several times higher; The frequency-multiplied clock is counted, and the above pulse train
Divided by the cycle of the clock multiplied by the above frequency
Count data representing the position of each section for each of the divided sections
D. a counter for outputting the data; Form corresponding to the count data output by this counter
Every time the counter outputs a carry signal
E. phase data generating means for changing and outputting The value of the count data output by the counter
Numerical data values output by the phase data generation means match
Is detected, and the match detection timing is
Supply to the trigger input terminal of the switching flip-flop
A jitter adding device comprising: a detection circuit ;