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JP2834069B2 - Chip-in-glass type fluorescent display tube - Google Patents
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JP2834069B2 - Chip-in-glass type fluorescent display tube - Google Patents

Chip-in-glass type fluorescent display tube

Info

Publication number
JP2834069B2
JP2834069B2 JP10522196A JP10522196A JP2834069B2 JP 2834069 B2 JP2834069 B2 JP 2834069B2 JP 10522196 A JP10522196 A JP 10522196A JP 10522196 A JP10522196 A JP 10522196A JP 2834069 B2 JP2834069 B2 JP 2834069B2
Authority
JP
Japan
Prior art keywords
chip
insulating layer
mounting portion
fluorescent display
display tube
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP10522196A
Other languages
Japanese (ja)
Other versions
JPH09293471A (en
Inventor
幸士郎 福島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
KAGOSHIMA NIPPON DENKI KK
Original Assignee
KAGOSHIMA NIPPON DENKI KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by KAGOSHIMA NIPPON DENKI KK filed Critical KAGOSHIMA NIPPON DENKI KK
Priority to JP10522196A priority Critical patent/JP2834069B2/en
Publication of JPH09293471A publication Critical patent/JPH09293471A/en
Application granted granted Critical
Publication of JP2834069B2 publication Critical patent/JP2834069B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Cathode-Ray Tubes And Fluorescent Screens For Display (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、蛍光表示管に関
し、特に駆動用ICを真空外囲器内に内蔵するチップイ
ングラス型蛍光表示管に関する。
The present invention relates to a fluorescent display tube, and more particularly to a chip-in-glass type fluorescent display tube having a driving IC built in a vacuum envelope.

【0002】[0002]

【従来の技術】蛍光表示管は、自発光で視認性が優れて
いる表示装置としてオーディオ、VTR等の家電製品か
ら自動車電装品及び計測器等の産業機器に至る幅広い分
野で用いられている。その中でも、チップイングラス型
蛍光表示管は、駆動用ICを真空外囲器に内蔵している
ため、外部へ導出するリードを削減し、全体の小型化、
モジュール実装の容易化及び真空内にICチップを実装
することによる高信頼性が確保されるという特徴を有し
ている。
2. Description of the Related Art Fluorescent display tubes are used in a wide range of fields from home appliances such as audio and VTRs to industrial equipment such as automobile electric components and measuring instruments as display devices which are self-luminous and have excellent visibility. Among them, the chip-in-glass type fluorescent display tube has a driving IC built in the vacuum envelope, so the number of leads led out is reduced, and the overall size is reduced.
It has features that simplicity of module mounting and high reliability by mounting an IC chip in a vacuum are ensured.

【0003】チップイングラス型蛍光表示管の基本構造
は、図10に示すようにガラス基板1にスパッタ法によ
りAl薄膜の給電配線10が形成され、次に高耐圧の絶
縁性を確保するため、2層の絶縁層21,22を形成す
る。次に絶縁層21,22の開口部に導通用のグラファ
イトを充填し、その上の絶縁層上に表示画素の形状をし
た導通層5を形成し、さらに、蛍光体層6を塗布する。
一方、ICチップ搭載部は、絶縁層上に接着剤となるポ
リイミド樹脂4がスタンプされた後、その上にICチッ
プ9がマウントされ、一定時間加熱放置し、樹脂を硬化
させICチップ9を固着する。その後、ICチップの入
出力部のパッドと基板上のボンディングパッド7とが、
ボンディングワイヤ8によりボンディングされる。この
場合、ICチップの下の絶縁層は、他の部分の絶縁層2
1,22と分離されておらず一体になっている。この
後、グリッド11,フィラメント12等の電極部品やカ
バーガラス13と共に組み立てられ、フリットガラスの
溶融によって封止が行なわれ、最後に内部を真空に引き
封止して仕上げを行ない完成する。
The basic structure of a chip-in-glass type fluorescent display tube is as shown in FIG. 10, in which a power supply wiring 10 of an Al thin film is formed on a glass substrate 1 by a sputtering method. Two insulating layers 21 and 22 are formed. Next, the openings of the insulating layers 21 and 22 are filled with conductive graphite, a conductive layer 5 having a shape of a display pixel is formed on the insulating layer, and a phosphor layer 6 is applied.
On the other hand, in the IC chip mounting portion, after the polyimide resin 4 serving as an adhesive is stamped on the insulating layer, the IC chip 9 is mounted thereon, and then heated and left for a certain period of time to cure the resin and fix the IC chip 9 thereto. I do. After that, the pads of the input / output unit of the IC chip and the bonding pads 7 on the substrate are
Bonding is performed by a bonding wire 8. In this case, the insulating layer below the IC chip is the other part of the insulating layer 2
They are not separated from 1 and 22, but are integrated. Thereafter, it is assembled together with the electrode parts such as the grid 11 and the filament 12, and the cover glass 13, sealing is performed by melting the frit glass, and finally, the inside is evacuated and sealed to finish and complete.

【0004】ここで、ICチップ搭載部の絶縁層の形状
に関しては、次のような提案がなされている。例えば、
特開平5−74348には、図11に示すようにガラス
基板1上にAlの給電配線が形成され、絶縁層51がス
クリーン印刷によって2層塗布される。その際、スクリ
ーンを2種類用い第1層絶縁層のICチップ9搭載部の
第1の開口41を設け、第1層目絶縁層を被覆する第2
層目絶縁層に第2の開口42を設ける。第1層及び第2
層の絶縁層の厚みは、各々20μmとするので第1の開
口の深さは40μm、第2の開口の深さは20μmとな
る。また、第1の開口41の大きさは、少なくとも2辺
をICチップ9の対応する辺の大きさよりも小さくし、
第2の開口42は、短辺方向の長さがICチップ9の長
さよりも0.1μm程度大きくし、長辺方向はICチッ
プ9をマウントする際に振動を与えてICチップ9とポ
リイミド樹脂4とをなじませるので、その振幅の分だけ
大きくとる必要がある。ワイヤボンディングはICチッ
プ9をマウントしポリイミド樹脂4の粘着性と第2の開
口42による仮止めの状態で行なっている。
Here, the following proposal has been made regarding the shape of the insulating layer in the IC chip mounting portion. For example,
In Japanese Patent Application Laid-Open No. 5-74348, a power supply wiring of Al is formed on a glass substrate 1 as shown in FIG. 11, and two insulating layers 51 are applied by screen printing. At this time, two types of screens are used to provide a first opening 41 in the mounting portion of the IC chip 9 of the first insulating layer, and a second opening 41 for covering the first insulating layer.
The second opening 42 is provided in the layer insulating layer. First layer and second layer
Since the thickness of each of the insulating layers is 20 μm, the depth of the first opening is 40 μm, and the depth of the second opening is 20 μm. Also, the size of the first opening 41 is such that at least two sides are smaller than the corresponding sides of the IC chip 9,
The second opening 42 has a length in the short side direction larger than the length of the IC chip 9 by about 0.1 μm, and gives a vibration when the IC chip 9 is mounted in the long side direction so that the IC chip 9 and the polyimide resin In order to make 4 compatible, it is necessary to increase the amplitude by the amplitude. The wire bonding is performed with the IC chip 9 mounted and the adhesiveness of the polyimide resin 4 and the temporary fixing by the second opening 42.

【0005】また、特開平5−89805には、図12
(a),(b)に示すように絶縁層51の第2の溝32
には、ダイボンド材61が塗布され、その上にICチッ
プ9が第1の溝31に嵌合する形でマウントされてい
る。又、図12(c),(d)では、第2の溝32の2
辺はチップサイズより大きく、残りの2辺は、チップサ
イズより小さくなっており第1の溝もそれぞれに応じて
大きくなっている部分を有する構造になっている。
Japanese Unexamined Patent Application Publication No. 5-89805 discloses FIG.
As shown in (a) and (b), the second groove 32 of the insulating layer 51 is formed.
Is coated with a die bonding material 61, on which the IC chip 9 is mounted so as to fit in the first groove 31. Also, in FIGS. 12C and 12D, the second groove 32 2
The sides are larger than the chip size, and the remaining two sides are smaller than the chip size, and the first groove has a structure in which the first groove has a correspondingly larger portion.

【0006】これら2つの提案は、チップイングラス型
蛍光表示管のICチップ搭載部の下の2層化された絶縁
層において、基板側の第1層絶縁層には、ICチップ辺
の何れかに嵌合し、第2層絶縁層はそれより大き目の開
口を形成し、ダイボンド材を充填してICチップを固定
する構成である。以上の構成では、何れもICチップ搭
載部の下部には、その接着面に対応する絶縁層は全く残
されていない。
[0006] These two proposals are based on the fact that in a two-layer insulating layer below an IC chip mounting portion of a chip-in-glass type fluorescent display tube, the first insulating layer on the substrate side has one of the IC chip sides. , The second insulating layer forms a larger opening, and is filled with a die bonding material to fix the IC chip. In any of the above configurations, no insulating layer corresponding to the bonding surface is left below the IC chip mounting portion.

【0007】[0007]

【発明が解決しようとする課題】従来の技術では、IC
チップ搭載部の絶縁層とICチップの接着剤として用い
るポリイミド樹脂層との接合面に、ガラス基板まで至る
クラックが生じ絶縁層の下を通るAlの給電配線が断線
する。その理由は、製造工程における封止工程等の熱工
程及びチップグラス型蛍光表示管の動作時ICチップの
発熱により、ICチップ、ポリイミド樹脂、絶縁層及び
ガラス基板間の熱膨張率の差異により、歪を生じるから
である。
In the prior art, an IC
A crack reaching the glass substrate occurs on the joint surface between the insulating layer of the chip mounting portion and the polyimide resin layer used as the adhesive for the IC chip, and the Al power supply wiring passing under the insulating layer is broken. The reason is that due to the heat process such as the sealing process in the manufacturing process and the heat generated by the IC chip during the operation of the chip glass type fluorescent display tube, the difference in the thermal expansion coefficient between the IC chip, the polyimide resin, the insulating layer and the glass substrate causes This is because distortion occurs.

【0008】本発明は、チップイングラス型蛍光表示管
において、動作不良の原因の1つに、ICチップ搭載部
下を通るAlの給電配線まで至る基板クラックがあり、
これを解消することを目的としている。
According to the present invention, in the chip-in-glass type fluorescent display tube, one of the causes of the malfunction is a substrate crack reaching the power supply wiring of Al passing under the IC chip mounting portion.
The purpose is to eliminate this.

【0009】[0009]

【課題を解決するための手段】本発明は、ガラス基板上
に形成された給電配線と、この給電配線を被覆し、IC
チップ搭載部周辺のボンディングパッド部に開口を有す
るガラス基板側1層目絶縁層及びその上に形成される2
層目絶縁層と、この絶縁層にICチップを接合させる接
着剤層を形成し、この接着剤層上に駆動用のICチップ
を搭載した蛍光表示管において、ICチップ搭載部の2
層の絶縁層に貫通してICチップを包囲する溝を形成し
て、ICチップ搭載部の絶縁層を島状に他と分離した構
造を有することを特徴とする。なお、第2層目絶縁層に
対して第1層目絶縁層を厚くしてもよい。また、第2層
絶縁層に溝を形成してもある程度の効果が得られる。
According to the present invention, there is provided a power supply wiring formed on a glass substrate and an IC which covers the power supply wiring.
The first insulating layer on the glass substrate side having an opening in the bonding pad portion around the chip mounting portion and the second insulating layer formed thereon
In a fluorescent display tube in which a second insulating layer and an adhesive layer for bonding an IC chip to the insulating layer are formed, and a driving IC chip is mounted on the adhesive layer, a second IC chip mounting portion is provided.
It is characterized in that a groove is formed to penetrate the insulating layer of the layer and surround the IC chip, so that the insulating layer of the IC chip mounting portion is separated from the others in an island shape. Note that the first insulating layer may be thicker than the second insulating layer. Further, even if a groove is formed in the second insulating layer, a certain effect can be obtained.

【0010】IC搭載部直下の絶縁層を島状に他と分離
している。こうすることにより、製造工程における熱履
歴及びチップイングラスの動作時のICチップの発熱に
より、ICチップ、接着剤、絶縁層及びガラス基板間に
熱膨張率の差による応力により歪を生じるが、絶縁層を
島状に他と分離してあるためにICチップ下の絶縁層の
歪による変位量を軽減することができて、ガラス基板上
の絶縁層の下を通るAlの給電配線の断線を防ぐことが
できる。
The insulating layer immediately below the IC mounting portion is separated from the others in an island shape. By doing so, the heat history in the manufacturing process and the heat generated by the IC chip during the operation of the chip-in-glass cause distortion due to stress caused by the difference in the coefficient of thermal expansion between the IC chip, the adhesive, the insulating layer, and the glass substrate. Since the insulating layer is separated from the others in an island shape, the amount of displacement due to the distortion of the insulating layer below the IC chip can be reduced, and disconnection of the Al power supply wiring passing under the insulating layer on the glass substrate can be prevented. Can be prevented.

【0011】[0011]

【発明の実施の形態】本発明について図面を参照して詳
細に説明する。図1は、本発明の第1の実施の形態の一
部切り欠き平面図、図2は図1のICチップ搭載部の部
分拡大平面図、図3(a)は図2のA−A′線の断面
図、図3(b)は図2のB−B′線断面図、図4はIC
チップ搭載前の第1の実施の形態の絶縁層の開口部の斜
視図である。
DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail with reference to the drawings. FIG. 1 is a partially cutaway plan view of the first embodiment of the present invention, FIG. 2 is a partially enlarged plan view of the IC chip mounting portion of FIG. 1, and FIG. 3A is AA 'of FIG. 3 (b) is a sectional view taken along line BB 'of FIG. 2, and FIG.
It is a perspective view of an opening of an insulating layer of a 1st embodiment before chip mounting.

【0012】第1の実施の形態は、図1〜図4に示すよ
うに、スクリーン印刷によって表面にAlの給電配線が
形成されたガラス基板1上に、所定の厚みを得るため2
層化された絶縁層が塗布される。その際に、スクリーン
を2種類用い、ICチップ9搭載部直下のガラス基板1
に接する第1の溝31を作り、その上に第2の溝32を
段差をつけて作る。絶縁層の厚さは、各々約10μm×
2=20μmなので第1の溝31の深さは20μm、第
2の溝32の深さは10μmとなる。また、溝の幅は
0.8mm程度である。ICチップ9搭載部の島状の第
1層目絶縁層21の長さと幅は、ICチップ9よりも
0.2mm程大きく、また第2層目絶縁層22の長さと
幅は第1層目絶縁層よりも0.1mm程度小さい。
In the first embodiment, as shown in FIGS. 1 to 4, on a glass substrate 1 on the surface of which a power supply wiring of Al is formed by screen printing, a glass substrate 1 having a predetermined thickness is formed.
A layered insulating layer is applied. At this time, two types of screens were used, and the glass substrate 1 immediately below the IC chip 9 mounting portion was used.
Is formed, and a second groove 32 is formed thereon with a step. The thickness of each insulating layer is about 10 μm ×
Since 2 = 20 μm, the depth of the first groove 31 is 20 μm, and the depth of the second groove 32 is 10 μm. The width of the groove is about 0.8 mm. The length and width of the island-shaped first insulating layer 21 on the IC chip 9 mounting portion are larger than the IC chip 9 by about 0.2 mm, and the length and width of the second insulating layer 22 are the first layer. It is smaller than the insulating layer by about 0.1 mm.

【0013】この2層の絶縁層には、蛍光体層6とAl
の給電配線との導通をとるための貫通穴が設けられ、そ
の貫通穴には導通用の導通層5が塗布される。そして、
第2層目絶縁層22の上には、導通用の導通層5を介し
て表示画素の形状をしたグラファイト層が設けられ、そ
の上に蛍光体層6が形成される。また、ICチップ9搭
載部直下の島状の絶縁層の上部に接着剤として用いるポ
リイミド樹脂4を塗布し、その上にICチップ9をマウ
ントし、一定時間加熱し硬化させてICチップ9を固着
する。この状態で基板上のボンディングパッド7とIC
チップ9側の接続リードがワイヤボンダによってボンデ
ィングワイヤ8で結線される。その後、フィラメント等
の電極部品やカバーガラス等で共に組み合せて、フリッ
トガラスの溶融によって封止が行なわれる。そして、内
部を真空に引き封止し、仕上げそして完成する。このよ
うに本実施の形態では、ICチップ搭載部直下の絶縁層
を島状に他の部分と分離しているので、製造工程やIC
動作時の熱によるガラス基板と絶縁層間の熱ストレスに
よる歪量を軽減でき、クラックなどの発生を防止でき
る。
The two insulating layers include a phosphor layer 6 and an Al layer.
A through-hole for establishing conduction with the power supply wiring is provided, and a conduction layer 5 for conduction is applied to the through-hole. And
A graphite layer having the shape of a display pixel is provided on the second insulating layer 22 via a conductive layer 5 for conduction, and a phosphor layer 6 is formed thereon. Further, a polyimide resin 4 used as an adhesive is applied to the upper part of the island-shaped insulating layer immediately below the mounting portion of the IC chip 9, and the IC chip 9 is mounted thereon, and is heated and cured for a certain time to fix the IC chip 9. I do. In this state, the bonding pad 7 on the substrate and the IC
The connection leads on the chip 9 side are connected by bonding wires 8 by a wire bonder. Thereafter, they are combined together with an electrode component such as a filament, a cover glass or the like, and sealing is performed by melting the frit glass. Then, the inside is evacuated and sealed, finished and completed. As described above, in the present embodiment, since the insulating layer immediately below the IC chip mounting portion is separated from other portions in an island shape, the manufacturing process and the IC
The amount of distortion due to thermal stress between the glass substrate and the insulating layer due to heat during operation can be reduced, and generation of cracks and the like can be prevented.

【0014】図5は、本発明の第2の実施の形態を示す
断面図である。この第2の実施の形態の製造方法は、第
1の実施の形態とほぼ同じであるが、第1の溝31の深
さを約15μmとする。これは、第1層目の絶縁層21
の厚さを、第1の実施の形態より厚くし、熱容量を大き
くし、熱によるストレスを緩和する利点がある。
FIG. 5 is a sectional view showing a second embodiment of the present invention. The manufacturing method of the second embodiment is almost the same as that of the first embodiment, except that the depth of the first groove 31 is about 15 μm. This is because the first insulating layer 21
Has the advantages of increasing the thickness of the first embodiment compared to the first embodiment, increasing the heat capacity, and alleviating the stress due to heat.

【0015】図6は本発明の第3の実施の形態のICチ
ップ搭載部の部分拡大平面図、図7(a)は、図6のC
−C′線の断面図、図7(b)は、図6のD−D′線の
断面図、図8はICチップ搭載前の第3の実施の形態の
絶縁層の開口部の斜視図である。第3の実施の形態の製
造方法は、第1の実施の形態とほぼ同じであるが、IC
チップ9搭載部直下の絶縁層に関し、第2層目絶縁層2
2だけを島状に他と分離し、第2層目絶縁層22の開口
部にある第1層目絶縁層21にも放熱機能を持たせて、
熱膨張によるストレスを第2層目絶縁層22で吸収させ
る。
FIG. 6 is a partially enlarged plan view of an IC chip mounting portion according to a third embodiment of the present invention, and FIG.
FIG. 7B is a cross-sectional view taken along the line DD ′ of FIG. 6, and FIG. 8 is a perspective view of the opening of the insulating layer of the third embodiment before mounting the IC chip. It is. The manufacturing method of the third embodiment is almost the same as that of the first embodiment,
Regarding the insulating layer immediately below the chip 9 mounting portion, the second insulating layer 2
Only the second insulating layer 21 is separated from the others in an island shape, and the first insulating layer 21 in the opening of the second insulating layer 22 is also provided with a heat dissipation function.
The stress due to thermal expansion is absorbed by the second insulating layer 22.

【0016】図9は、本発明の第4の実施の形態を示す
断面図である。第4の実施の形態の製造方法は、第1の
実施の形態と同じで、第2及び第3の実施例の変形例と
して、図9に示すような、第1の溝の深さを約15μm
とし、第1層目絶縁層21を厚くすることで熱容量を大
きくし、加えてICチップ9搭載部直下の絶縁層に関
し、第2層目絶縁層22だけを、島状に他と分離するこ
とで第2層目絶縁層22の開口部に放熱機能を持たせ、
熱膨張によるストレスを吸収させる。
FIG. 9 is a sectional view showing a fourth embodiment of the present invention. The manufacturing method of the fourth embodiment is the same as that of the first embodiment. As a modification of the second and third embodiments, the depth of the first groove as shown in FIG. 15 μm
By increasing the thickness of the first insulating layer 21, the heat capacity is increased, and in addition, only the second insulating layer 22 is separated from the others with respect to the insulating layer immediately below the IC chip 9 mounting portion. To give the opening of the second insulating layer 22 a heat radiation function,
Absorb stress due to thermal expansion.

【0017】[0017]

【発明の効果】以上説明したように、本発明によれば、
ICチップ搭載部の絶縁層の下部のAlの給電配線の断
線を防ぐことができるようになる。その理由は、ICチ
ップ搭載部の絶縁層を島状に他と分離することで製造工
程における熱履歴及びチップイングラス型蛍光表示管の
動作時のICの発熱によるガラス基板の絶縁層間での熱
ストレスによる歪量を軽減できるからである。
As described above, according to the present invention,
Breakage of the power supply wiring of Al under the insulating layer of the IC chip mounting portion can be prevented. The reason is that the insulating layer of the IC chip mounting portion is separated from the others in an island shape, so that the heat history in the manufacturing process and the heat between the insulating layers of the glass substrate due to the heat generated by the IC during the operation of the chip-in-glass type fluorescent display tube. This is because the amount of distortion due to stress can be reduced.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の第1の実施の形態の一部切り欠き平面
図である。
FIG. 1 is a partially cutaway plan view of a first embodiment of the present invention.

【図2】図1のICチップ搭載部の部分拡大平面図であ
る。
FIG. 2 is a partially enlarged plan view of an IC chip mounting section of FIG. 1;

【図3】(a)は、図2のA−A′線の断面図、(b)
は、図2のB−B′線の断面図である。
FIG. 3A is a sectional view taken along line AA ′ of FIG. 2;
FIG. 3 is a sectional view taken along line BB ′ of FIG. 2.

【図4】ICチップ搭載前の第1の実施の形態の絶縁層
の開口部の斜視図である。
FIG. 4 is a perspective view of an opening of an insulating layer according to the first embodiment before mounting an IC chip.

【図5】本発明の第2の実施の形態の断面図である。FIG. 5 is a sectional view of a second embodiment of the present invention.

【図6】本発明の第3の実施の形態のICチップ搭載部
の部分拡大図である。
FIG. 6 is a partially enlarged view of an IC chip mounting portion according to a third embodiment of the present invention.

【図7】(a)は図6のC−C′線の断面図、(b)は
図6のD−D′線の断面図である。
7A is a cross-sectional view taken along line CC ′ of FIG. 6, and FIG. 7B is a cross-sectional view taken along line DD ′ of FIG.

【図8】ICチップ搭載前の第3の実施の形態の絶縁層
の開口部の斜視図である。
FIG. 8 is a perspective view of an opening of an insulating layer according to the third embodiment before mounting an IC chip.

【図9】本発明の第4の実施の形態の断面図である。FIG. 9 is a sectional view of a fourth embodiment of the present invention.

【図10】従来のチップイングラス型蛍光表示管全体構
成図である。
FIG. 10 is an overall configuration diagram of a conventional chip-in-glass type fluorescent display tube.

【図11】特開平5−74348に示された従来例の断
面図である。
FIG. 11 is a cross-sectional view of a conventional example shown in Japanese Patent Application Laid-Open No. 5-74348.

【図12】(a)〜(d)は、特開平5−89805に
開示された従来例を示す図である。
FIGS. 12A to 12D are views showing a conventional example disclosed in JP-A-5-89805.

【符号の説明】 1 ガラス基板 4 ポリイミド樹脂 5 導通層 6 蛍光体層 7 ボンディングパッド 8 ボンディングワイヤ 9 ICチップ 21 第1層目絶縁層 22 第2層目絶縁層 31 第1の溝 32 第2の溝DESCRIPTION OF SYMBOLS 1 Glass substrate 4 Polyimide resin 5 Conductive layer 6 Phosphor layer 7 Bonding pad 8 Bonding wire 9 IC chip 21 First layer insulating layer 22 Second layer insulating layer 31 First groove 32 Second groove

Claims (3)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 ガラス基板上に形成された給電配線と、
この給電配線を被覆し、ICチップ搭載部周辺のボンデ
ィングパッド部に開口を有するガラス基板側1層目絶縁
層及びその上に形成される2層目絶縁層と、この絶縁層
にICチップを接合させる接着剤層を形成し、この接着
剤層上に駆動用のICチップを搭載したチップイングラ
ス型蛍光表示管において、前記ボンディングパッド部の
開口を含むようにICチップ搭載部の2層の絶縁層に貫
通してICチップを包囲する溝を形成して、ICチップ
搭載部の絶縁層を島状に他と分離した構造を有すること
を特徴とするチップイングラス型蛍光表示管。
A power supply wiring formed on a glass substrate;
A first insulating layer on the glass substrate side having an opening in a bonding pad portion around the IC chip mounting portion and a second insulating layer formed thereon, which covers the power supply wiring, and an IC chip is bonded to the insulating layer. An adhesive layer to be formed is formed, and a chip implanter on which a driving IC chip is mounted is formed on the adhesive layer.
In the display type fluorescent display tube, the bonding pad
A groove is formed to penetrate through the two insulating layers of the IC chip mounting portion so as to include the opening and surround the IC chip, so that the insulating layer of the IC chip mounting portion is separated from the others in an island shape. Characteristic chip-in-glass type fluorescent display tube.
【請求項2】 第2層目絶縁層に対して第1層目絶縁層
を厚くした構造を有することを特徴とする請求項1記載
のチップイングラス型蛍光表示管。
2. The chip-in-glass type fluorescent display tube according to claim 1, wherein the first insulating layer has a thickness greater than that of the second insulating layer.
【請求項3】 ガラス基板上に形成された給電配線と、
この給電配線を被覆し、ICチップ搭載部周辺のボンデ
ィングパッド部に開口を有するガラス基板側1層目絶縁
層及びその上に形成される2層目絶縁層と、この絶縁層
にICチップを接合させる接着剤層を形成し、この接着
剤層上に駆動用のICチップを搭載したチップイングラ
ス型蛍光表示管において、前記ボンディングパッド部の
開口を含むようにICチップ搭載部の2層目の絶縁層に
のみICチップを包囲する溝を形成して、ICチップ搭
載部の2層目絶縁層を島状に他と分離した構造を有する
ことを特徴とするチップイングラス型蛍光表示管。
3. A power supply wiring formed on a glass substrate,
A first insulating layer on the glass substrate side having an opening in a bonding pad portion around the IC chip mounting portion and a second insulating layer formed thereon, which covers the power supply wiring, and an IC chip is bonded to the insulating layer. An adhesive layer to be formed is formed, and a chip implanter on which a driving IC chip is mounted is formed on the adhesive layer.
In the display type fluorescent display tube, the bonding pad
A groove surrounding the IC chip is formed only in the second insulating layer of the IC chip mounting portion so as to include the opening, and the second insulating layer of the IC chip mounting portion is separated from the others in an island shape. A chip-in-glass type fluorescent display tube characterized by the above-mentioned.
JP10522196A 1996-04-25 1996-04-25 Chip-in-glass type fluorescent display tube Expired - Fee Related JP2834069B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10522196A JP2834069B2 (en) 1996-04-25 1996-04-25 Chip-in-glass type fluorescent display tube

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10522196A JP2834069B2 (en) 1996-04-25 1996-04-25 Chip-in-glass type fluorescent display tube

Publications (2)

Publication Number Publication Date
JPH09293471A JPH09293471A (en) 1997-11-11
JP2834069B2 true JP2834069B2 (en) 1998-12-09

Family

ID=14401619

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10522196A Expired - Fee Related JP2834069B2 (en) 1996-04-25 1996-04-25 Chip-in-glass type fluorescent display tube

Country Status (1)

Country Link
JP (1) JP2834069B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3914654B2 (en) 1999-03-17 2007-05-16 株式会社ルネサステクノロジ Semiconductor device

Also Published As

Publication number Publication date
JPH09293471A (en) 1997-11-11

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