JP2834289B2 - Microprocessor - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprocessor capable of processing a variable length instruction set and performing parallel decoding of a plurality of instructions.

[Conventional technology]

In a conventional microprocessor capable of processing a variable-length instruction set, parallel decoding of instructions is not performed.

As a known example closest to the present invention, a document "Cache and Branch Prediction Mechanism" on pages 195 to 206 of Nikkei Electronics Books "New Generation Microprocessor RISC, CISC, TRON" published on September 11, 1989 is given. The instruction decoding method described in "32-bit Microprocessor V80, which has improved performance by suppressing pipeline turbulence with the built-in CPU".

The known microprocessor does not decode a plurality of instructions in parallel, but decodes the instructions in two stages to improve the throughput of decoding capability. The first-stage decode circuit of this known microprocessor is called a predecode unit, and has a function of dividing a variable-length instruction into fixed-length elements. The instructions thus decomposed into fixed length elements are temporarily stored in a buffer (register) in the predecode unit, and the fixed length from the predecode unit to the instruction decode unit is requested according to the instruction decode unit request. The transfer of the instruction decomposed into the elements is performed.

[Problems to be solved by the invention]

However, according to the studies made by the present inventors, it has been clarified that the above-described conventional technique has two problems when the processing speed of the microprocessor is further increased.

The first problem is that branch processing becomes slower because instruction decoding uses two stages of the pipeline.

That is, when the fetch and predecode of the branch destination instruction proceed after the start of the branch process, the time required for the branch is increased by one stage compared to a microprocessor that requires only one stage for the decode process.

A second problem is that in a microprocessor that executes a plurality of instructions in parallel, if a decoding method of decoding the instructions in two stages as in the above-described conventional technique is adopted, the predecode unit can reduce the performance of the entire microprocessor. It is rate-limiting. This is because the instruction to be processed has a variable length, so that the predecode unit cannot predecode the following instruction unless it predecodes the preceding instruction. That is, the predecode unit can only predecode one instruction at a time.

The present inventor and others have also clarified that there are three solutions to this second problem.

A first solution is to connect a plurality of predecode circuits for predecoding a plurality of instructions in series. That is, the succeeding predecode circuit refers to the output of the preceding predecode circuit. This problem can be solved by designing the plurality of predecode circuits so that they can operate within one cycle. However, in this case, the delay time of the pre-decoding circuit connected in series becomes a problem.

A second solution is a method in which the performance of the pre-decoding unit is made pre-decodable for one instruction in one cycle, and the performance difference is absorbed by a buffer. However, in this method,
Since the maximum throughput is one instruction / cycle, a plurality of instructions can be executed in other stages, but the performance is not significantly improved.

A third solution is to decode the subsequent instruction with some assumptions on the format of the preceding instruction as in the present invention.

The present invention has been made to realize the third solution specifically, and an object of the present invention is to provide a microprocessor which can decode a plurality of instructions at high speed and in parallel when processing a variable length instruction set. To provide.

[Means for solving the problem]

In order to achieve the above object, of the instructions to be decoded simultaneously, the subsequent instruction is decoded on the assumption of the instruction length of the preceding instruction.

If the assumption is found correct by the decoding of the preceding instruction, the decoding result of the following instruction is also determined to be correct. Conversely, if the assumption is determined to be incorrect, the decoding result of the subsequent instruction is determined to be incorrect. Invalidate the result.

Further, it is desirable that the assumed instruction length is the length of the shortest instruction format in the instruction set. because,
The shortest instruction format in the variable length instruction set is
This is because it corresponds to a frequently used instruction, and therefore the probability that the assumption is satisfied is high.

In order to decode a plurality of instructions in parallel, the instruction prefetch unit transfers an instruction code having at least twice the length of the shortest instruction format to the instruction decode unit.

The instruction decode unit inputs the instruction code to separate instruction decodes for each length of the shortest instruction format. Each instruction decode has the ability to decode at least the instruction with the shortest instruction format, and at least one instruction decoder has the ability to decode all instructions in the instruction set. The output of each instruction decoder can be held in a different output latch.

Among the inventions disclosed in the present application, an outline of a microprocessor according to a typical embodiment is as follows.

That is, (1) First and second instructions having an instruction length of a predetermined bit width (16 bits) are fetched from outside the microprocessor, and a bit width (32 bits) of at least twice the predetermined bit width is fetched. A fetch unit (IU) that outputs the first and second instructions in parallel to an output line of the fetch unit (IU); and (2) the first instruction of the output line of the fetch unit (IU) is supplied to its input. (3) a second instruction decoder (ID1) whose input is supplied with the second instruction of the output line of the fetch unit (IU); Decoding result of the first instruction decoder (id0_ou
t) and the decoding result of the second instruction decoder (id1_ou
and (5) an instruction execution unit (EU) that responds to an output from the control unit (PCNT), the number of bits being twice the predetermined bit width. Under the condition that the first instruction having the predetermined instruction length is output from the output line having at least the width, the control unit (PCNT) determines the condition in the decoding result (id0_out) of the first instruction decoder (ID0). In response to the establishment information, the second instruction decoder (ID
The decoding result (id1_out) of (1) is made valid, and as a result, the instruction execution unit (EU) decodes the decoding results (id0_out, id0_out,
id1_out), the first instruction and the second instruction are executed in parallel, and an instruction having an instruction length different from the predetermined bit width is output from the output line of the fetch unit (IU). Under other conditions, the control unit (PCNT) operates in the first decoder (ID
In response to the information on the satisfaction of the other condition in the decoding result (id0_out) of (0), the decoding result (id1_out) of the second decoder (ID1) is invalidated. As a result, the instruction execution unit (EU) The decoding result (id0_o) of the first instruction decoder (ID0) transmitted to the output of the control unit (PCNT)
ut), the first instruction is executed in response to the first instruction.

[Action]

It is determined whether the instruction coder processed by each instruction decoder is an instruction that can be decoded by each instruction decoder (that is, an instruction having the shortest instruction format).
If the result of the determination is that the instruction decoder has decoded an instruction having an instruction format that is not otherwise, the decoding result of the instruction code following the instruction is all invalidated. Invalidation can be easily realized using a control circuit. Conversely, if the result of the determination is that all instruction decoders have decoded instructions having the shortest instruction format, all decoded results are valid. At this time, the throughput of instruction decoding is maximum, and the number of instructions equal to the number of instruction decoders is processed in one cycle.

By doing so, although it is limited to the case where the assumption is correct, the maximum throughput of instruction decoding can be made 2 instructions / cycle or more, and the second problem can be solved. Further, since the instruction length of the preceding instruction is assumed, it is not necessary to decompose the variable length instruction into fixed length elements by the predecode circuit, and the first problem can be solved.

The instruction decoding method according to the present invention may be different from the conventionally known pre-decoding method in that an instruction may be decoded under an incorrect assumption. In that case, as described above, the decoding result is invalidated, and the throughput in that case is one instruction / cycle. As described above, in the present method, the dependence of the processing performance on the instruction format is higher than in the predecode method. This point can be dealt with by using an instruction having a format that satisfies the above assumption as much as possible in the program.

Other objects and features of the present invention will become apparent from the following description of the embodiments.

〔Example〕

FIG. 1 is a block diagram of a microprocessor to which the present invention is applied. The present invention enables parallel decoding of multiple instructions. Here, the simplest internal structure of a microprocessor that decodes two instructions in parallel and its operation will be described.

First, the internal structure of the microprocessor will be described with reference to FIG. The microprocessor shown in FIG. 1 basically includes an interface unit IOU, an instruction prefetch unit IU, an instruction decode unit DU, and an arithmetic unit EU. These units can operate in parallel,
Pipeline processing is performed under the control of the instruction decode unit DU.

Interface unit IOU The microprocessor is
This interface unit IOU connected to external devices (for example, main memory) through U
Performs transfers between the microprocessor and main memory for both instructions and data.

That is, the instruction read from the main memory is
The data is transferred from the interface unit IOU to the instruction prefetch unit IU via a 64-bit width signal line.

On the other hand, the data calculated by the arithmetic unit EU through two sets of 32-bit signal lines is transmitted to the arithmetic unit EU.
Is transferred to the interface unit IOU or data read from the main memory is transferred from the interface unit IOU to the instruction decode unit DU.

Instruction prefetch unit IU Instruction prefetch unit IU is a prefetch queue PF
Have a Q. The instruction transferred from the interface unit IOU is once latched in the prefetch queue PFQ, and
After being aligned in bit units, it is output to the instruction decode unit DU. Prefetch queue PFQ is FIF
This is an O (First-In First-Out) queue.

The aligned instruction is transferred from the instruction prefetch unit IU to the instruction decode unit UD via six sets of 16-bit signal lines i0 to i5. Here, the signal line i0 is a head code of an instruction to be decoded in the next machine cycle, and the signal lines i1 to i5 are a sequence of instructions following the instruction of the line i0. The signal line i0 is input to the first instruction decoder ID0. Similarly, the signal line i1 is input to the second instruction decoder ID1. The feature of the embodiment of the present invention is that the input of the second instruction decoder ID1 is uniquely determined to the signal line i1 and is not selected from the signal lines i1 to i5. The first instruction decoder ID0 has a function of decoding all instructions that can be processed by the microprocessor. On the other hand, the second instruction decoder ID1
Of instructions that can be executed by this microprocessor
Only instructions having an instruction format of length 32 or 32 bits can be decoded. First instruction decoder ID
The decoding results of the instructions 0 and the instruction of the second instruction decoder ID1 are output to signal lines id0_out and id1_out, respectively, and sent to the pipeline control unit PCNT.

Pipeline control unit PCNT The pipeline control unit PCNT has signal lines id0_out and id1_ou
A control signal is generated for each unit IOU, IU, EU based on t and a signal indicating the state of each unit I0U, IU, EU (omitted in the figure).

Extension generating circuit EG The instruction decoding unit DU includes an extension generating circuit EG.
The extension part generation circuit EG expands immediate data or displacement data in the instruction to 32 bits and outputs the result. The position and the length of the immediate data or displacement data in the instruction are specified in the operation code of the instruction, and can be obtained by decoding the operation code. The extension part generation circuit EG processes the data based on the designation and outputs the data to the bus d0 or d1. The reason why there are two sets of 32-bit output lines of the extension part generating circuit EG is to transfer data independently under the control of the first instruction decoder ID0 and the second instruction decoder ID1.

Arithmetic unit EU Similarly, the first instruction decoder ID0 and the second instruction decoder ID1 for the integer logical operation path ALU in the arithmetic unit EU.
There are two sets corresponding to each of.

Register File RF The register file RF in the instruction decode unit DU is composed of 16 32-bit registers R0 to R15, and each register has a total of six ports, four read ports and two write ports. Half of the ports (two read ports and one write port) correspond to the first instruction decoder ID0, and are connected to the first logical operation unit ALU0. Similarly, the other half of the ports correspond to the second instruction decoder ID1, and are connected to the second logical operation unit ALU1.

32-bit signal line Instruction decode unit DU and arithmetic unit EU
They are connected by signal salts d0, d1, d2, d3, e0, e1 having a 32-bit width.
Four of them (d0, d1, d2, d3) are instruction decode units DU
And the other two sets (e0, e1) are used to transfer data from the arithmetic unit EU to the instruction decode unit UD.

For example, when the first logical operation unit ALU0 processes an instruction to add the values of the register R0 and the register R1 and set the result in the register R1, first, the registers R0 and R1 are read from the register file RF.
Are read and output to the 32-bit signal lines d0 and d1, respectively. Instruction decode unit in pipeline
In the next execution stage of the DU, that is, the operation unit EU, the first logical operation unit ALU0 inputs values from the signal lines d0 and d1, and adds them. And the addition result is signal salt e0
Is output to In the register store stage, which is the next process, the process returns to the process in the instruction decode unit DU again, and the value on the signal line e0 is changed to the register in the register file RF.
Set to R1. The above is the operation using the first instruction decoder ID0 side. When the second instruction decoder ID1 is used, the signal lines d2, d3, e1 and the second logical operator
ALU1 is used. That is, the values of the registers R0 and R1 are output to the signal lines d2 and d3, respectively, and the second logical operation unit ALU1
After the addition is performed, the addition result is transferred to the register R1 using the signal line e1.

When data is transferred between the microprocessor and the memory, two sets of 32-bit wide signal lines between the signal lines e0 and e1 and the IOU are used. The operation of this part is not so related to the present invention, and the description is omitted.

An advantage of the present invention is that a plurality of instructions can be decoded in parallel. In this embodiment, a microprocessor having an instruction set of a variable-length instruction will be described as an example. First, a brief description of what a variable length instruction is like will be given.

Variable-length instruction A variable-length instruction is an instruction that has a plurality of instruction formats and changes in length when a different instruction format is used. That is, it can be said that an instruction set having at least one instruction having a different length has a variable-length instruction.

Fixed Length Instructions On the other hand, when the length of all instructions is constant, it is generally called a fixed length instruction set.

Instruction Set of the Present Embodiment In this embodiment, as shown in FIG. 2, an instruction set having six lengths from 16 bits to 96 bits is assumed in units of 16 bits. These instructions are in memory
It is placed on the 16-bit boundary. That is, each 16-bit unit of the instruction is all located at an even byte address. FIG. 3 shows this state.

Next, the operation of parallel decoding of instructions in the present embodiment will be described.

FIG. 3 shows one example of a sequence of instructions on the memory. Each instruction is shown as, for example, inst0, tnst1. Instructions with a length of more than 16 bits are further indicated by a hyphen and a number, such as inst2_0 and inst2_1. That is, an instruction having a length exceeding 16 bits is divided into a plurality of instructions. It is also assumed that the code that must be decoded in each instruction is limited to the code at the head of the instruction. That is, it is assumed that codes other than the head of the instruction are immediate data or displacement data. For example, in the case of inst2, the first code inst2_0 needs to be decoded, but the subsequent code inst2_1 does not need to be decoded.

Based on the above premise, the state of the 16-bit signal line i0-5, which is a transfer path from the instruction prefetch unit IU to the instruction decode unit DU, at two points in time is shown in FIG. FIG. 4A shows a state in which the instruction sequence of FIG. 3 has already been taken into the prefetch queue PFQ of the instruction prefetch unit IU, and the first instruction inst0 is about to be decoded. In the first half of the next machine cycle, the first instruction inst0 is decoded by the first instruction decoder ID0, and the subsequent instruction inst1 is decoded by the second decoder ID1. As a result of this decoding, two instructions inst0 and ins
It is found that both t1 are the instruction formats having the shortest length, and the instruction is issued from the instruction decode unit DU to the instruction prefetch unit IU to advance the instruction pointer by 32 bits. As a result, the state of the signal line i0-5 between the instruction prefetch unit IU and the instruction decode unit DU after a further half machine cycle becomes two instructions inst0,
Inst1 is removed, and instructions inst5 and inst6 are added instead, as shown in FIG. 4 (b). At this time, the instruction code inst2_0 is decoded by the first decoder ID0,
The second decoding of the instruction code inst2_1 is performed with ID1.
As a result of decoding the instruction code inst2_0 by the first decoder ID0, it is found that the instruction inst2 is not an instruction format having the shortest length.

When the shortest instruction is input to the first instruction decoder ID0, the first operation code of the next instruction is input to the second instruction decoder ID1. The second instruction decoder ID1 performs instruction decoding on the assumption that such a head instruction code of the next instruction is input. Therefore, if the instruction decoded by the first instruction decoder ID0 is a non-shortest instruction, it is determined that the instruction decoding performed by the second instruction decoder ID1 is erroneous, and the result of the error determination is the first instruction. This is reflected in the output id0_out of the decoder ID0, and in response to this determination result, invalidation processing is performed by the pipeline control unit.
Performed in PCNT. As shown in FIG. 1, the first and second instruction decoders ID0 and ID1
The decoding result, that is, the output of id0_out and id1_out is sent to NT. The output id0_out includes information indicating whether or not the instruction decoded by the first decoder ID0 has the shortest instruction format. Also output
id1_out may include information indicating that an instruction that cannot be decoded by the second decoder ID1 has been input. However, in the case of this embodiment, it is assumed that such information is not included in the output id1_out.

Depending on the information included in the output id0_out that the length of the instruction input to the first instruction decoder ID0 is shortest, that is, not 16 bits, the decoding result of the second instruction decoder ID1 must be invalidated. The invalidation process is
This is performed by the pipeline control unit PCNT as described above.

Detailed Block Diagram of Pipeline Control Unit PCNT FIG. 5 shows a detailed block diagram of the pipeline control unit PCNT.

The pipeline control unit PCNT is composed of a pipeline stage control unit Pipe_CNTL, a selector SEL, and a no-operation instruction unit NOP, based on the status of id0_out, id1_out and each unit (IU, DU, EU, IOU). , And controls the pipeline operation of the entire microprocessor. The control of each processing stage in this pipeline processing is performed by the pipeline stage control unit Pi in the pipe control unit PCNT in FIG.
Performed in pe_CNTL. Also, the second instruction decoder I
The process of invalidating the output information of D1 is performed before this pipeline stage control unit Pipe_CNTL.

That is, the invalidation of the output id1_out of the second instruction decoder ID1 is performed as follows. First, the second instruction decoder
The output id1_out of ID1 is supplied to one input of the selector SEL. Although one of the other inputs of the selector SEL is not particularly limited, in the present embodiment, a fixed value NOP is supplied. This fixed value NOP has exactly the same fields as id1_out,
Instructs a non-execution instruction instruction called a so-called no operation. The NOP may be the same as or different from the decode information of a nop instruction generally used as an instruction for instructing no operation. All you need is NO operator no oper
The designation of the size of the data to be handled may be in any place. The selection of NOP and id1_out in the selector SEL is based on whether or not the entire length of the instruction decoded by the first instruction decoder ID0 included in id0_out which is the decoding result of the first instruction decoder ID0 is 16 bits. This is performed according to the information id1_valid. Id1_out if the instruction length is 16 bits
Is selected. Conversely, if the instruction length exceeds 16 bits, NOP is selected. Thus, pipeline control signals pcnt0 and pcnt1 are obtained.

Assume again the execution of the instruction sequence shown in FIG. FIG. 6A shows changes in the pipeline control signals pcnt0 and pcnt1 at this time. Note that FIG. 6 (a) differs from FIG. 3 in that the vertical axis represents time. For example, when shifting from the state shown in FIG. 4A to the state shown in FIG.
0, inst1 is decoded. This is indicated by the top line in FIG. Then, in the next machine cycle, inst2_0 and inst2_1 are decoded and pcnt0, pcnt
In 1 the decoding result of inst2_0 and the NOP are output. Similarly, the decoding process is performed in four machine cycles from inst0 to inst6.

FIG. 6B shows a change in pcnt0 in the case of the conventional processing in which the same processing is performed using only the first instruction decoder ID0. In this conventional case, the decoding of the instructions from inst0 to inst6 is performed as shown in FIG.
It takes 7 machine cycles.

As described above, in the present embodiment, the instruction decoding performance is doubled at the peak, and at the worst case, the same performance as when a single instruction decoder is used can be obtained.

Next, the processing of the instructions inst0, inst1, inst2_0, and inst2_1 will be described using a more specific example. For example, the instruction inst
0 adds the values of register R0 and register R1 to register R1
The instruction inst1 is a fixed-length instruction that adds the values of the registers R2 and R3 and sets the result in the register R3, and the instruction inst2 stores the displacement data in the value of the register R4. It is assumed that the instruction is a variable-length instruction that adds the data to an address, fetches the data at the address from the main memory, and sets the data in the register R5. Where the instruction inst2_0 is the opcode, i
nst2_1 is a displacement.

 First, the processing of the instructions inst0 and inst1 will be described.

The two instructions inst0 and inst1 are output to the 96-bit signal line from the prefetch queue PFQ as shown in FIG. Then, inst0 is decoded by the first instruction decoder ID0, and inst1 is decoded by the second instruction decoder ID1.

In this case, the result of decoding of inst0 indicates that instruction inst0 is the shortest instruction, and the determination result is
It is indicated by asserting the signal id1_valid in id0_out. id0_out and id1_out are the pipeline control unit PCNT described above.
Are output as control signals pcnt0 and pcnt1. The following operations are performed according to the instructions of these control signals.

First, according to the instruction of the control signal pcnt0, the value of the register R is output to the signal line d0, and the value of the register R1 is output to the signal line d1. At the same time, according to the instruction of the control signal pcnt1, the value of the register R2 is output to the signal line d2, and the value of the register R3 is output to the signal line d3. Then, in the logical operation unit ALU0, the signal line
The values of d0 and d1 are added and output to the signal line e0, and the logical operation unit AL
U1 adds the values of the signal lines d2 and d3 and outputs the result to the signal line e1. In the subsequent register store stage, the value of the signal line e0 is set in the register R1, and the value of the signal line e1 is set in the register R3.

 Next, the processing operation of the instruction inst2 will be described.

The instruction inst2 is output to the 96-bit signal line from the prefetch queue PFQ as shown in FIG. 4 (b).
In the first instruction decoder ID0, inst2_0 is decoded, and in the second instruction decoder ID1, inst2_1 is decoded on the assumption that inst2_1 is the head code of the next instruction.

In this case, as a result of decoding of inst2_0, the instruction inst2_0
Is a non-shortest instruction, and the determination result is indicated by negating the signal id1_valid in id0_out of the decoding result. id0_out is the pipeline control unit PCNT described above
Is output as a control signal pcnt0. At the same time, i
Since d1_valid is negated, NOP, which is a no operation instruction, is selected in the selector SEL in the pipeline control unit PCNT, and is output as pcnt1. The following operations are performed according to the instructions of these control signals.

First, according to the instruction of the control signal pcnt0, the value of the register R4 is output to the signal line d0, and the 16-bit displacement inst2_1 is expanded to 32 bits by the expansion unit generation unit EG and output to the signal line d1.

Since the instruction of the control signal pcnt1 is NOP, the signal line
No particular output is specified for d2 and signal line d3. Subsequently, the integer logical operation unit ALU0 adds (address calculation) the values of the signal lines d0 and d1 and outputs the result to the signal line e0. The instruction to the logical operation unit ALU1 is also NOP, and the output to the signal line e1 is not particularly instructed.

In the subsequent stages, operands are fetched by accessing the main memory using the value of the signal line e0 as an address in accordance with the instruction of the control signal pcnt0, and the fetch data is set in the register R5. The instruction to the interface unit IOU and the instruction decode unit DU (register store) in the control signal pcnt1 is
Since this is a NOP, the main memory access and the transmission and setting of the value from the signal line e1 to the register are not performed.

According to this embodiment, the processing throughput of the entire microprocessor is improved, and the CPI (the number of machine cycles required for execution per instruction) can be made 1 or less.

Further, among the plurality of instruction decoders, only one instruction decoder can decode all instruction formats. Since the remaining instruction decoders only need to have the function of decoding the shortest instruction format, decoding of a plurality of instructions can be realized with a small amount of hardware. This also reduces the amount of processing and time required for microprocessor testing and diagnostics.

The instruction code input to the plurality of instruction decoders is as follows:
It is uniquely divided by the length of the shortest instruction format and input to each instruction decoder. That is, it is easy to select the inputs of all the instruction decoders. This is useful for suppressing the amount of hardware and realizing high speed.

Further, the embodiments of the present invention can be applied to a microprocessor having a fixed-length instruction set. That is, by making it possible to decode the majority of the instruction decoders and only the frequent instructions, an instruction decoder that processes a plurality of instructions in parallel with a small amount of hardware can be realized.

Further, regardless of the fixed-length instruction set and the variable-length instruction set, it is possible to determine the instructions that can be decoded by each instruction decoder in accordance with the circuit controlled by the instruction decoder. For example, an instruction decoder that controls a logical operation unit
Only the logical operation instruction can be decoded, and other instructions output a result indicating that the decoding could not be performed.
This has the effect of reducing the number of signal lines from the instruction decoder to the controlled circuit.

〔The invention's effect〕

According to the present invention, a plurality of fixed-length instructions can be decoded in parallel in a variable-length instruction set. Therefore, the maximum instruction decoding performance is improved as compared with the conventional method.

[Brief description of the drawings]

FIG. 1 is a block diagram of a microprocessor according to an embodiment of the present invention, FIG. 2 is a diagram showing six types of instruction lengths of a variable-length instruction set of the microprocessor of the embodiment, and FIG. FIG. 4 shows an example of a sequence of instructions on a memory in the example instruction set. FIG. 4 shows signal lines i0-5 when the microprocessor shown in FIG. 1 executes the instruction sequence shown in FIG.
FIG. 5 shows the values of the control circuit which is one of the components of the microprocessor of FIG.
FIG. 6 (a) shows a detailed configuration diagram of the PCNT, and FIG. 6 (a) shows a change in a control signal generated by instruction decoding when the instruction sequence of FIG. 3 is executed in the microprocessor of FIG. (B) shows a change in the control signal when the microprocessor of FIG. 1 has a configuration having only one instruction decoder.

────────────────────────────────────────────────── ─── of the front page continued (72) inventor Kunio Uchiyama Tokyo Kokubunji Higashikoigakubo 1-chome 280 address Hitachi, Ltd. center within the Institute (58) investigated the field (Int.Cl. ^6, DB name) G06F 9/38 G06F 9/30 G06F 9/32

Claims (3)

(57) [Claims] 1. A first and a second instruction having an instruction length of a predetermined bit width are fetched from outside a microprocessor, and the first and second instructions are output to an output line having a bit width at least twice the predetermined bit width. A fetch unit that outputs a second instruction in parallel; a first instruction decoder whose input is supplied with the first instruction of the output line of the fetch unit; and an output line of the fetch unit that has an input. A second instruction decoder to which the second instruction is supplied; a control unit to which a first decoding result of the first instruction decoder and a second decoding result of the second instruction decoding are supplied; An instruction execution unit responsive to an output from the control unit, wherein the control unit includes a selector, and one input of the selector includes a second decoding result of the second instruction decoder and an error. In order to select and output one of the second decoding result and the non-executable command instruction, the control input of the selector includes information indicating a predetermined instruction length of the first instruction. In a valid condition provided and the information indicates that the predetermined instruction length is a predetermined bit length, the selector selects the second decoding result,
The control unit transmits a first decoding result of the first instruction decoder and a second decoding result of the second instruction decoder to an output of the control unit, and as a result, invalidates the second decoding result. A microprocessor configured to transmit a first decoding result of the first instruction decoder and the non-executable instruction instruction to an output of the control unit. 2. The microprocessor according to claim 1, wherein when the control unit invalidates a second decoding result of the second decoder, the invalidated second decoder is invalidated. A microprocessor for determining an address of an operand in response to bit information of the output line of the fetch unit corresponding to a bit position of the second decoded result of the above. 3. The microprocessor according to claim 1, wherein said predetermined bit width is a shortest instruction length.