JPH0760383B2 - Processor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a processor capable of shortening instruction decoding time.

(Prior Art) With the increase in performance of microprocessors in the micro program control system, the instruction length of machine language instructions for causing the microprocessor to perform a predetermined operation tends to be long,
An increasing number of microprocessors process variable-length machine language instructions.

In such a microprocessor, a variable-length machine language instruction generally has a meaning for each unit instruction length (for example, 8 bits = 1 byte). Instructions were sequentially decoded for each unit instruction length. However, the displacement (Di
When a plurality of "splacement" and immediate values (Immediate) exist in a machine language instruction, the decoding may be performed regardless of the unit instruction length, not limited to the above.

As a method for decoding a variable-length machine language instruction, a variable-length machine language instruction is given to a decoder for each unit instruction length, and this unit instruction is decoded before the unit instruction is decoded. It is decoded according to the information required to decode the next unit instruction that is part of the result. The decoding result includes information that can be interpreted and executed by the microprogram and information necessary for decoding the next unit instruction. Then, the next unit instruction is decoded according to the information necessary for the next decoding which is a part of the information of the decoding result, and the variable length machine language instruction is sequentially decoded for each unit instruction.

In such a variable-length machine language instruction decoding method, decoding of a unit instruction generally requires one machine cycle. Therefore, in order to decode a variable-length machine language instruction, a machine cycle time corresponding to the unit instruction is required.

(Problems to be Solved by the Invention) As described above, in the method of sequentially decoding a variable-length machine language instruction for each unit instruction, the variable-length machine language instruction is decoded for the unit instruction. It takes a long machine cycle, and a large number of unit instructions requires a considerable amount of time.

Therefore, in most fields where microprocessors are used, high-speed processing is required. In the decoding method as described above, the performance of the microprocessor increases the decoding time of machine language instructions. There was a problem of deterioration.

Therefore, the present invention has been made in view of the above, and an object of the present invention is to provide a processor capable of reducing the decoding time of a machine language instruction and performing processing by the processor at high speed. is there.

[Structure of the Invention] (Means for Solving Problems) In order to achieve the above object, according to the present invention, a unit instruction requiring decoding of a machine language instruction including a plurality of unit instructions is executed in parallel for each unit instruction. After decoding, a plurality of decoding results are obtained for each unit instruction, and each decoding result is a plurality of decoded instructions executable by the microprogram and a decoding result of the upper unit instruction accompanying this decoded instruction. Decoding information obtained from the decoding result of the lower unit instruction or the decoding result obtained from the highest-order decoding result of the preceding machine language instruction One decoding result is selected from a plurality of decoding results obtained by the corresponding decoding means according to the obtained decoding information. A plurality of selecting means and a decoding result selected by each of the selecting means, and the decoding information of the decoding result selected by the highest selecting means is the lowest of the held decoding results. The decoding information of the decoding result given to the means and selected by the lower selection means is provided to the upper selection means.

(Operation) In the above configuration, according to the present invention, a plurality of unit instructions of machine language instructions are decoded in parallel, a plurality of decoding results are obtained for each unit instruction, and the decoding information of the decoding result on the lower side is obtained. Therefore, one decoding result is selected from the decoding results on the upper side.

Embodiment An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a processor according to an embodiment of the present invention. The processor shown in the figure is configured such that a variable-length machine language instruction having a unit instruction length of 1 byte (8 bits) is decoded in 2 bytes, that is, 2 unit instructions in parallel by using two decoders. It is a thing. This embodiment shows an example of decoding a machine language instruction handled by a 32-bit microprocessor (i APX80386) manufactured by Intel Corporation of the United States.

Here, before explaining the configuration of FIG. 1, an outline of machine language instructions of the processor will be described.

FIG. 2 is a diagram showing a part of the machine language instruction processed by the processor. In addition to this, various instructions are prepared for performing desired processing.

Various machine language instructions processed by the processor are formatted according to their instructions as shown in FIG. 2 and have a variable length instruction system of 1 byte to 15 bytes.

Machine language instructions having such an instruction system are classified into 13 types, as shown in FIG.

In FIG. 3, “OP1” and “OP2” are information indicating the processing content, “OP2” is an extended instruction, and “OP1” is
It occurs only when OF (H).

"Mod r / m" is information that specifies a general-purpose register or memory, "sib" is information that specifies a general-purpose register with 32 bits when calculating an execution address, and "mod r / m" is a specific value. It is information that exists only when it is taken.

"T" of "T / P" is information for interrupting by an instruction, and "P" is information for specifying an input / output device.
"Offset" and "selector" are information used to calculate the effective address in the segment method, and "level"
Is information used only in a specific instruction. “DISP” is information that indicates the displacement used to calculate the effective address.
"IMM" is an immediate value. Where “T / P”, “offset”, “sel
ector "," level "," DISP ", and" IMM "are all numerical information." Prefix "is added to the beginning of the instruction, and only the instruction with this" Prefix "added in the series of addresses This is information for changing the size or the data size.

By classifying machine language instructions in this way, instructions having similar functions and properties are decoded by the same hardware to improve decoding efficiency.

In the machine language instructions classified as shown in FIG. 3,
The combination of instructions when selecting any 2 bytes is
As shown in FIG. 4, there are 43 combinations. Fourth
The "invalid" shown in the figure occurs when a branch is made to a higher address of the selected two bytes.

Although invalid is described in FIG. 4, invalid means not a unit instruction, but means that the value of the lower field of the machine language instruction is not referenced and has no meaning, and is treated as invalid. And is shown in FIGS. 4 and 5 for convenience. In this embodiment, two machine language instructions are used.
Since the lower byte is set to an even address and the upper byte is set to an odd address, the instruction is executed in parallel and the machine instruction Is supplied to the upper second decoder 2, the lower first decoder 1 is treated as invalid.

Here, the information of the unit instruction lengths that compose the machine language instructions classified as shown in FIG. 4 has information that can be commonly handled, and "T / P" and "offset" are set to " DIS
P "is treated," Selector "and" level "are treated as" IMM ", and" Prefix "and" OP1 "are treated as" head ". By doing this, the 2 shown in FIG. The combination of bytes is simplified as shown in FIG.

In the combination as shown in FIG. 5, the unit instruction length information to be decoded is "invalid", "start", "OP2", "mod".
r / m "," sib "," DISP "," IMM "are enough. Therefore, as a result of decoding a certain 1-byte information, the 1-byte information at the higher address of this information is shown above. It is one of the seven information items.

Here, "DISP" is "start", "OP2", "mod r / m", "sib"
“IMM” is obtained as the decoding result of any of “head,“ OP2 ”, and“ mod r / m ”, and“ DISP ”and“ IMM ”are numerical information. Decoding is not necessary because it is not encoded, and “invalid” indicates that the next byte is the beginning of the machine language instruction, and since it has no meaning in itself, decoding is unnecessary. In the decoding process, among the above-mentioned seven information, “head”, “OP2”, “mod r / m”, “si
All you have to do is four of b ".

Next, returning to FIG. 1, the configuration and operation of this embodiment will be described in order.

The microprocessor shown in the figure includes a first decoder 1 and a second decoder 2.
Decoder 2, first selector 3, second selector 4 and register
It has 5,6.

The first decoder 1 decodes information of a unit instruction length of a small address (first byte) of a machine language instruction 7 given from the outside in units of 2 bytes into information of an instruction format that can be interpreted and executed by a microprogram. Is. That is, the coded and given information is decoded in four ways as "head", "OP2", "mod r / m""sib", as described above, and the decoding result of each is the first. It is supplied to the selector 3.

The second decoder 2 decodes the unit instruction length information of the larger address (2nd byte) of the 2-byte machine language instruction 7 in the same manner as the first decoder 1 described above. It is supplied to the second selector 4. Here, the 2-byte machine language instruction 7 is simultaneously applied to each decoder.

The first selector 3 selects one of the four decoding results of the first decoder according to the information temporarily stored in the register 6.
The selected decoding result is composed of the decoding result 8 of the information of the first byte and the decoding information 9 indicating the information of the higher address, that is, the information of the second byte. Of these, the decoding result 8 of the information of the first byte is supplied to the register 5, and the decoding information 9 of the second byte is supplied to the second selector 4.

Like the first selector 3, the second selector 4 selects one decoding result from the four decoding results of the second decoder 2, but this selection is different from the first decoder 1. This is performed according to the second byte of decode information 9 output from the first selector 3.

The selected decoding result is the decoding result 10 of the information of the second byte and what information is at a small address of the 2-byte machine language instruction given next to this 2-byte machine language instruction. It is composed of decoding information 11 indicating whether or not. Of these, the decoding result 10 of the information of the second byte is supplied to the register 5, and the decoding information 11 is supplied to the register 6.

The decoding information 9 of the decoding results selected by the first selector 3 is selected and the second selector 4
Therefore, it is held and output by a through latch circuit or the like. On the other hand, the decode information 11 of the decode results selected by the second selector 4 is held as the decode information 9 in order to select the lower decode result of the next machine language instruction. It is not necessary to output to the first selector 3 within the period, and it is sufficient to output to the register 6 in the next instruction cycle, so that it is held by the flip-flop circuit or the like.

Therefore, the decode information 9 is asynchronously selected by the first selector 3 within one instruction cycle, held in the through latch circuit or the like, and supplied to the second selector 4.

Even when the number of decoders and selectors is increased, each piece of decode information obtained as a decoding result is asynchronously transmitted from the lower side to the upper side within one instruction cycle except for the highest-order decode information. As described above, the decoder, selector, and through latch circuit may be designed.

The register 5 stores and holds the decoding result 8 of the first byte selected by the first selector 3 and the decoding result 10 of the second byte selected by the second selector 4 in predetermined areas. The information is interpreted and executed by the microprogram.

The register 6 stores and holds the decoding information 11 of the decoding result selected by the second selector 4,
The stored and held decode information 11 is supplied to the first selector 3.

As described above, this embodiment is constructed. Next, the operation of this embodiment will be described.

Here, in a 2-byte machine language instruction given from the outside, for example, the information of a small address (first byte) is set as the "head" and the information of a large address (second byte) is set as "mo".
The case of "dr / m" will be described.

When a 2-byte machine language instruction 7 is simultaneously applied from the outside, information of a small address is given to the first decoder 1 and information of a large address is given to the second decoder 2.

When the information of a small address is given to the first decoder 1, this information is "first", "OP" by the first decoder 1.
2 "," mod r / m "," sib "are decoded in four ways. The" leading "decoding result of these decoding results is the machine language instruction given before the above machine language instruction 7. Is selected by the first selector 3 in accordance with the decode information (information indicating that the information of the first byte is the "head") held in the register 6 among the decoded results of the larger address.

Of the selected decoding results, the information 8 which the microprogram interprets and executes as the "head" is given to the register 8 and stored and held, and the decoding information of the large address (the information of the large address is "mod r / m" Information 9 indicating that there is) is given to the second selector 4.

On the other hand, of the machine language instructions 7 given simultaneously for 2 bytes,
The information of the large address is transferred to the "head", "OP2",
It is decoded in 4 ways: "mod r / m" and "sib". Of these decoding results, “mod r / m” is selected by the second selector 4 in accordance with the decoding information 9 given from the first selector 3.

Of the selected decoding results, the information 10 that the microprogram interprets and executes as "mod r / m" is stored and held in the register 5, the decoding information 11 is given to the register 6 and temporarily held, and then It is used when selecting the decoding result of information of a small address of a given 2-byte machine language instruction. Of the 2-byte machine language instructions,
Information that does not need to be decoded, such as "DISP", "IMM",
It is directly applied to and stored in the register 5 without going through each decoder.

In this way, by decoding the 2-byte machine language instruction in parallel, the 2-byte machine instruction can be decoded in one machine cycle as shown in FIG. Therefore, a 1-byte machine language instruction is
Machine language instructions that are decoded in 1/2 machine cycle and consist of many unit instructions can be decoded in 1/2 time compared with the conventional method.

Although one embodiment of the present invention shows an example of decoding a machine language instruction used in a 32-bit microprocessor (i APX80386) manufactured by Intel Corporation of the United States, the invention is not limited to this, and a similar variable-length machine may be used. Of course, it may be a word instruction. The machine language instruction to be decoded in parallel is not limited to 2 bytes, and may be increased according to the number of decoders used. Further, every time a predetermined number of machine language instructions given to the microprocessor shown in FIG. 1 are decoded, a predetermined number of machine language instructions are stored and held from an external memory in a buffer in the microprocessor. The buffer may be supplied to the microprocessor. Furthermore, the first and second
The selectors may be provided on the input sides of the corresponding decoders, and the information of the machine language instruction to be decoded may be selected in advance and given to each decoder. However, in this case, the decoding time of, for example, a 2-byte machine language instruction that is decoded in parallel is short, and the decoding is required in one machine cycle.

[Effects of the Invention] As described above, according to the present invention, a predetermined number of unit instructions of machine language instructions are decoded in parallel, so that the decoding time of variable length machine language instructions is shortened and the processor It is possible to provide a processor that performs the processing according to the above.

[Brief description of drawings]

1 is a block diagram showing a configuration of a processor according to an embodiment of the present invention, FIGS. 2 to 5 are diagrams showing instructions processed by the processor of FIG. 1, and FIG. 6 is a diagram showing FIG. FIG. 9 is a timing diagram of a processor. (Explanation of symbols representing main parts of the drawing) 1 ... First decoder, 2 ... Second decoder 3 ... First selector, 4 ... Second selector 5, 6 ... Register

Claims (1)

[Claims] 1. A unit instruction that requires decoding of a machine language instruction composed of a plurality of unit instructions is decoded in parallel for each unit instruction, and a plurality of decoding results are obtained for each unit instruction. Corresponding to each of the plurality of decoding means, which is composed of a plurality of decoded instructions executable by the microprogram and decode information for specifying the decoded result of the upper unit instruction accompanying the decoded instructions, From among the plurality of decoding results obtained by the corresponding decoding means according to the decoding information obtained from the decoding result of the lower unit instruction or the decoding information obtained from the highest decoding result of the previous machine language instruction A plurality of selection means for selecting one decoding result and the respective decoding means selected by the plurality of selection means. The decoding information of the decoding result holding the result, of which the decoding result of the decoding result selected by the uppermost selecting means is given to the lowermost selecting means, and the decoding information of the decoding result selected by the lower selecting means. And a holding means provided to a higher-order selection means.