JP2836613B2 - Semiconductor nonvolatile memory element, semiconductor nonvolatile memory circuit, and method of operating the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor nonvolatile memory element, a semiconductor nonvolatile memory circuit, and an operation method thereof, and more particularly, to a semiconductor nonvolatile memory element and a semiconductor nonvolatile memory circuit capable of low power consumption and high integration. And its operation method.

[0002]

2. Description of the Related Art An MNOS memory element has been known as a conventional semiconductor memory element. This MNOS storage element is a nonvolatile storage element in which a silicon nitride film is provided between an oxide film layer and a gate electrode of a MOS transistor, and a capture center existing in the silicon nitride film is used as a storage medium. The silicon nitride film layer has a large number of electron capture centers. When the thickness of the oxide film layer is set to 100 ° or less, electrons can be exchanged between the semiconductor and the nitride film by the Fowler-Nordheim tunnel mechanism through the oxide film. The captured electrons remain in place unless an electric field is applied, and have a hysteresis effect. Further, the electrons trapped in the nitride film change the surface state at the interface between the semiconductor and the oxide film, so that the threshold voltage of the field effect transistor changes. The stored content can be read by the change in the threshold voltage.

As another known semiconductor memory element, there is a nonvolatile memory element using a single electron transistor in a read circuit. This single-electron transistor is a highly sensitive charge meter that can detect a slight change in electric charge, that is, a change of 10 ⁻⁴ in terms of the number of electrons. Therefore, the amount of electric charge stored in the storage medium is small. Good. Therefore, a low power consumption memory element can be formed. Non-volatile memory elements using a single-electron transistor for a read circuit, which have been reported, have been manufactured using metal as a material. For example, the element reported by Dresselhaus et al. In a literature (Physical Review Letter, Vol. 72, p. 904 (1994)) is a typical example.

[0004]

Among the above-mentioned two conventional semiconductor nonvolatile memory elements, the former MNOS memory element in which the gate insulating film has two layers of an oxide film and a nitride film is:
Requires hundreds to thousands of electrons for programming.
This is because a change in the threshold voltage of the reading field-effect transistor requires several hundreds of electrons. Therefore, it is necessary to apply a high electric field to the insulating film at the time of programming, and thus there are problems such as shortening of the life of the insulating film and increasing power consumption. Also, when trying to miniaturize the field effect transistor used for reading,
There is a problem that a current flows at the time of off due to a short channel effect and power consumption increases at the time of standby.

On the other hand, in the latter nonvolatile memory element using a single-electron transistor for the read circuit, since the single-electron transistor is used for the read circuit, the power consumption during programming and reading is small. On the other hand, since the readout circuit, the storage medium, and the wiring are arranged in the same plane, the area per one storage element is larger than that of the MNOS storage element having a stacked structure.

In order to miniaturize a storage element, it is necessary to arrange wiring and a storage medium in an upper layer with respect to a plane on which a readout circuit is formed, like an MNOS storage element. However, when the material of the single-electron transistor is a metal, there is no thermal resistance to a high-temperature atmosphere when forming the insulating film.
Therefore, it is difficult to form a large-scale integrated circuit (LSI) by miniaturization with the latter nonvolatile memory element. Further, although a tunnel junction array is used as a storage medium, the manufacturing method is complicated, and it is difficult to obtain uniform characteristics.

[0007] The present invention has been made in view of the above points,
A semiconductor non-volatile memory element and semiconductor of low power consumption type that can be miniaturized and integrated on a large scale using a single-electron transistor for a readout circuit using a semiconductor LSI process that is advantageous in terms of manufacturing cost and mass productivity. An object is to provide a nonvolatile memory circuit and an operation method thereof.

[0008]

In order to achieve the above object, a semiconductor non-volatile memory device according to the present invention comprises a single-electron transistor formed on a first insulating film covering a semiconductor substrate; A second insulating film, a third insulating film having an electron trapping center, and a fourth insulating film are sequentially stacked on the transistor, and a control gate electrode is formed on the fourth insulating film to store the electron trapping center. It is configured as a medium.

Here, the third insulating film having an electron capture center is a silicon nitride film, the second insulating film and the fourth insulating film are each a silicon oxide film, and the second insulating film is a fourth insulating film. The thickness of the fourth insulating film is smaller than that of the second insulating film, or the thickness of the fourth insulating film is smaller than that of the second insulating film.

According to another aspect of the present invention, there is provided a semiconductor nonvolatile memory circuit comprising: a memory array in which a plurality of semiconductor nonvolatile memory elements are arranged in a matrix; A row address decoding circuit for simultaneously applying a gate voltage to the control gates of two or more semiconductor nonvolatile memory elements arranged in the same row via the same row address line, and the plurality of semiconductor nonvolatile memory elements Among them, a plurality of detection amplifiers connected to the drains of two or more semiconductor nonvolatile memory elements arranged in the same column via the same column address line, and a column address signal is input to each of the plurality of detection amplifiers A semiconductor nonvolatile memory circuit having a column address decoding circuit
A single-electron transistor is formed on a first insulating film covering a semiconductor substrate, and a second insulating film and an electron are formed on the single-electron transistor. A third insulating film having a trapping center and a fourth insulating film are sequentially laminated, a control gate electrode is formed on the fourth insulating film, and the electron trapping center is used as a storage medium. The drain of the electronic transistor is connected to a column address line, the source is grounded, and the control gate electrode is connected to a row address line.

Further, in the method of operating a semiconductor nonvolatile memory circuit according to the present invention, a first column address line selected from a plurality of column address lines and a first row address line selected from a plurality of row address lines are provided. Specified by each combination with
A column address decoding circuit for applying a first positive potential to the first column address line via a detection amplifier connected to the first column address line to read the first semiconductor nonvolatile memory element; A second positive potential is applied from a row address decoding circuit to a control gate electrode of a first semiconductor nonvolatile memory element via a first row address line, and a second row other than the first row address line is applied. The control gate electrodes of the plurality of second semiconductor nonvolatile memory elements connected to the address lines are each set to the ground potential to turn off the single-electron transistor of the second semiconductor nonvolatile memory element, and the first semiconductor nonvolatile memory element is turned off. When the second positive potential is applied to the control gate electrode of the storage element and the first semiconductor nonvolatile storage element is in the erased state, the output of the single electron transistor is a Coulomb blockade. It is off, if the first semiconductor nonvolatile memory device is in the programming state, and performing read by utilizing the fact that the single-electron transistor is turned on.

In the present invention, it has been found that a trapping center for trapping a large number of electrons exists in the third insulating film which is a nitride film layer. By using this capture center as a storage medium and performing reading with a single-electron transistor, a storage circuit with high integration and high reliability can be configured.

[0013]

Next, embodiments of the present invention will be described with reference to the drawings. 1A and 1B are a cross-sectional view and a top view of a first embodiment of a semiconductor nonvolatile memory element according to the present invention.

1A and 1B, a semiconductor nonvolatile memory element 10 is manufactured on a semiconductor substrate 12 such as silicon by a manufacturing method described later in detail. A first insulating film 13 is coated on the semiconductor substrate 12. The first insulating film 13 may be, for example, a silicon oxide film. First
The single electron transistor 14 is manufactured on the insulating film 13 of FIG.

The single-electron transistor 14 comprises two tunnel barriers 32, 34 and an island 33 electrically isolated from the drain 31 and the source 35 by the tunnel barriers 32, 34. Drain 31, source 3
5 and the island 33 are made of, for example, a degenerated silicon layer having a high impurity concentration. The highly degenerated impurity concentration is from 1 × 10 ¹⁹ / cm ³ to 1 × 1
0 ²¹ / cm ³ , and the thickness of the silicon layer may be about 50 ° to 500 °. The width and depth of the island 33 are each 200 ° or less. Tunnel barrier 32, 3
Reference numeral 4 is a barrier for conduction electrons or holes, and the height of the barrier is desirably 1 eV or more.

The single-electron transistor 14 is covered with a second insulating film 15a. On the second insulating film 15a, the first portion 21a overlying a portion of the drain 31, the single-electron transistor 14, the second portion overlying a portion of the drain 31 and a portion of the source 35
And a third portion 23a overlying a portion of the source 35. The second portion 22a of the second insulating film 15a may be a silicon oxide film, but preferably has a thickness of about 10 ° to 50 °. First portion 21a and third portion 23 of second insulating film 15a
a may be a silicon oxide film, and is 200 to 2000 mm.
A certain thickness is desirable.

On the second insulating film 15a, a third insulating film 16a having an electron capture center 20 is coated. The third insulating film 16a having the electron capture center 20 has
First portion 24a overlying first portion 21a of second insulating film 15a, second portion 2 of second insulating film 15a.
A second portion 25a is provided over the second portion 25a, and a third portion 26a is provided over the third portion 23a of the second insulating film 15a. The third insulating film 16a having the electron trapping center 20 may be made of silicon nitride or silicon oxynitride, and preferably has a thickness of about 200 to 1000 degrees.

Third insulating film 1 having electron trapping center 20
A fourth insulating film 17a is coated on 6a.
The fourth insulating film 17a may be made of silicon oxide,
A thickness of about Å to 500Å is desirable. Fourth insulating film 1
A control gate 18 is coated on 7a. In this embodiment, the thickness of the second portion 22a of the second insulating film 15a is formed smaller than that of the fourth insulating film 17a.

FIGS. 2A and 2B are a sectional view and a top view, respectively, of a second embodiment of the semiconductor nonvolatile memory element according to the present invention. The semiconductor non-volatile memory element 10 of this embodiment is also manufactured on a semiconductor substrate 12 such as silicon by a manufacturing method described later, as in the first embodiment.
A first insulating film 13 is coated on the semiconductor substrate 12. The first insulating film 13 is, for example, a silicon oxide film, on which a single-electron transistor 14 is manufactured.

The single-electron transistor 14 includes two tunnel barriers 32 and 34 and an island 33 electrically isolated from the drain 31 and the source 35 by the tunnel barriers 32 and 34. Drain 31, source 3
5 and the island 33, as in FIG. 1, a highly degenerated silicon layer having an impurity concentration of about 1 × 10 ¹⁹ / cm ³ to 1 × 10 ²¹ / cm ³ is formed in a thickness of about 50 ° to 500 °. Structure. The width and depth of the island 33 are each 200 ° or less. Tunnel barrier 32,
Numeral 34 is a barrier for conduction electrons or holes, and the height of the barrier is desirably 1 eV or more.

The single insulating transistor 14 is covered with a second insulating film 15b. On the second insulating film 15b, the first portion 21b overlying a portion of the drain 31, the single-electron transistor 14, the second portion overlying a portion of the drain 31 and a portion of the source 35
And a third portion 23b overlying a portion of the source 35. The second portion 22b of the second insulating film 15b may be a silicon oxide film, and preferably has a thickness of about 100 ° to 500 °. Second
Part 21b and third part 2 of the insulating film 15b of FIG.
3b may be a silicon oxide film, from 200 to 2000
A thickness of about Å is desirable.

On the second insulating film 15b, a third insulating film 16b having an electron capture center 20 is coated. The third insulating film 16b having the electron capture center 20 has
First portion 24b overlying first portion 21b of second insulating film 15b, second portion 2 of second insulating film 15b
The second portion 25b is provided on the second portion 25b, and the third portion 26b is provided on the third portion 23b of the second insulating film 15b. The third insulating film 16b having an electron capture center may be made of silicon nitride or silicon oxynitride, and has a thickness of about 50 ° to 500 °.

Third insulating film 1 having electron capture center 20
A fourth insulating film 17b is coated on 6b.
The fourth insulating film 17b may be made of silicon oxide and may have a thickness of 10 °.
And a thickness of about 50 ° is desirable. Fourth insulating film 17b
Above is covered a control gate 18. That is,
This embodiment is characterized in that, contrary to the first embodiment, the fourth insulating film 17b is thinner than the second portion 22b of the second insulating film 15b.

Next, the semiconductor nonvolatile memory circuit of the present invention will be described. FIG. 3 shows a configuration diagram of an embodiment of the semiconductor nonvolatile memory circuit according to the present invention. In the figure,
The semiconductor nonvolatile storage circuit 40 includes a storage array 5 in which a plurality of semiconductor nonvolatile storage elements 10 are arranged in a matrix.
There is 0. In the semiconductor nonvolatile memory circuit 40, a column address decoding circuit 4 is provided as a peripheral circuit of the memory array 50.
1, row address decoding circuit 43, plural detection amplifiers 54a
To 54z.

The connections between the drain (D) 31, the source (S) 35, and the control gate 18 of each of the semiconductor nonvolatile memory elements 10 are as follows. The control gates 18 of the semiconductor nonvolatile memory elements 10 in the same row are connected to the same row address line. Row address line is 5 from 53a
Up to 3z, the control gates of the semiconductor nonvolatile memory elements 10 in the same row are commonly connected, and one end is connected to the row address decoding circuit 43.

The drains 31 of the semiconductor nonvolatile memory elements 10 in the same column in the memory array 50 are commonly connected by a column address line. There are a plurality of column address lines 51a to 51z. The drains of the semiconductor nonvolatile memory elements 10 in the same column are commonly connected to each other, and one end is column address decoded via the corresponding one of the detection amplifiers 54a to 54z. It is connected to a circuit 41. Further, the source 35 of each of the plurality of semiconductor nonvolatile memory elements 10 in the memory array 50 is grounded.

FIG. 4A shows an arbitrary one of the column address lines 51a to 51z shown in FIG.
And the semiconductor nonvolatile memory element 10 connected to an arbitrary one of the row address lines 53a to 53z, and the one connected to the column address line 51n.
5 shows an equivalent circuit of one detection amplifier 54n. The semiconductor nonvolatile memory element 10 may be any of the semiconductor nonvolatile memory elements 10 shown in FIGS. Therefore, as described above, the semiconductor non-volatile memory element 10 includes the single-electron transistor 1
4 and a capture center 20.

The single electron transistor 14 has a drain 3
1. An island 33 electrically isolated from the drain 31 and the source 35 by a source 35 and two tunnel barriers 32 and 34. The capture center 20 is connected to the control gate 18 via a capacitor having a capacitance C ₁ ,
And the island 3 via the capacitor of the capacitance C ₂
3 is connected. Each of the tunnel barriers 32 and 34 can be replaced with a circuit in which a capacitor having a capacitance C and a resistance having a resistance value R are connected in parallel, as shown in FIG.

The third nitride film layer shown in FIGS.
It is known that the trapping centers 20 for trapping a large number of electrons exist in the insulating layers 25a and 25b. This trap center 20 is used as a storage medium, and the single electron transistor 1
By performing reading in step 4, a storage circuit having high integration and high reliability can be configured as described below. Compared with the conventional semiconductor nonvolatile memory circuit using the MNOS memory element, the number of electrons programmed in the storage medium can be reduced from several hundreds to several tens. Power consumption can be reduced in proportion to the decrease in the power consumption.

Next, the operation of the embodiment of the semiconductor nonvolatile memory circuit of the present invention will be described. [Erase Operation] First, an erase operation of the electrically variable semiconductor nonvolatile memory element having the structure shown in FIG. 1 will be described.
When erasing the storage contents of a desired semiconductor nonvolatile storage element 10 among the plurality of semiconductor nonvolatile storage elements 10 having the structure of FIG. 1 that constitute the storage array 50 of FIG. 3, a specific row address line, for example a negative voltage of -V _G is applied to the row address line 53m, the remaining row address lines as well as to the ground potential, a particular column address lines, for example, applies a positive voltage + V _D to the column address line 51n. As a result, the positive voltage + is applied to the drain 31 of the selected semiconductor nonvolatile memory element 10.
V _D is applied and the selected semiconductor nonvolatile memory element 1
Negative voltage -V _G to the control gate 18 of 0 is applied.

The electrons trapped by the trapping centers 20 in the third insulating film 16a, which is a nitride film layer, by the electric field generated between the drain 31 and the control gate 18 are converted into the second oxide film layer.
Is injected into the drain 31 by the Fowler-Nordheim tunnel mechanism passing through the insulating film 15a. As a result, there is no electron at the capture center 20 in the third insulating film 16a, which is a nitride film layer. At this time, the fourth insulating film 17a prevents electrons from being injected from the control gate 18 side, and allows electrons to be efficiently extracted from the capture center 20. The effectiveness of the fourth insulating film 17a is described in a known document (Frank R. Libsch and Marvin H. White, Solid State El.
ectronics, Vol. 33, No. 1, pp. 105-126).

[0032] When the delete the storage contents of the nonvolatile semiconductor memory element 10 in the selected row of memory array 50, a particular row address line, e.g., the row address line 53m negative voltage -V _G is applied, the remaining row address lines as well as to the ground potential, applying a positive voltage V _D to all of a plurality of column address lines 51a to 51z. In this way, the storage array 5
Only the storage contents of the semiconductor nonvolatile memory elements 10 in the same row connected to the row address line 53m of 0 are erased.

[0033] When erasing the storage contents of all the semiconductor nonvolatile memory device 10 of the storage array 50, to all of a plurality of row address lines 53a to 53z, by applying a negative voltage of -V _G, and, A plurality of column address lines 51a to 51
A positive voltage of V _D is applied to everything up to z. In this manner, the storage contents of all the nonvolatile semiconductor memory elements 10 having the structure shown in FIG.

Next, an erasing operation of the semiconductor nonvolatile memory element 10 having the structure shown in FIG. 2 will be described. When erasing the storage content of a desired semiconductor nonvolatile storage element from the plurality of semiconductor nonvolatile storage elements 10 having the structure shown in FIG. 2 that constitute the storage array 50 of FIG. Line, for example, a row address line 53m with a positive voltage + V _G
, The rest of the row address lines are set to the ground potential, and a negative voltage −V _D is applied to a specific column address line, for example, the column address line 51n. As a result, a negative voltage − is applied to the drain 31 of the selected semiconductor nonvolatile memory element 10.
V _D is applied and the selected semiconductor nonvolatile memory element 1
The positive voltage + V _G is applied to the 0 of the control gate 18.

Thus, the drain 31 and the control gate 1
Electrons trapped by the trapping centers 20 in the third insulating film 16b, which is a nitride film layer, by an electric field generated between the Fowler 8 and the Fowler-Nordheim tunnel mechanism through the fourth insulating film 17b, which is an oxide film layer. Is injected into the control gate 18. Thereby, the third insulating film 1 which is a nitride film layer
There is no electron at the capture center 20 in 6b. At this time, the fourth insulating film 17b prevents electrons from being injected from the control gate 18 side, so that the electrons can be efficiently extracted from the capture center 20.

[0036] When the delete the storage contents of the nonvolatile semiconductor memory element 10 in the selected row of memory array 50, a particular row address line, e.g., the row address line 53m negative voltage -V _G is applied, the remaining row address lines as well as to the ground potential, applying a positive voltage V _D to all of a plurality of column address lines 51a to 51z. In this way, the storage array 5
Only the storage contents of the semiconductor nonvolatile memory elements 10 in the same row connected to the row address line 53m of 0 are erased.

When erasing the storage contents of all the semiconductor nonvolatile storage elements 10 of the storage array 50, the positive voltage + V _{G is} applied to all of the plurality of row address lines 53a to 53z.
And a plurality of column address lines 51a to 51
A negative voltage -V _D is applied to everything up to z. In this manner, all of the semiconductor nonvolatile storage elements 10 in the storage array 50 are erased. [Programming Operation] Next, the programming operation of the electrically variable semiconductor nonvolatile memory circuit of FIG. 3 will be described. When programming a desired semiconductor nonvolatile memory element 10 of the plurality of semiconductor nonvolatile memory elements 10 having the structure of FIG.
Particular row address line, for example, a positive voltage + V _G is applied to the row address line 53m, with the remainder of the row address lines to the ground potential, a particular column address lines, for example, the column address lines 5
Applying a negative voltage -V _D to 1n. Thus, the negative voltage -V _D is applied to the drain 31 of the nonvolatile semiconductor memory element 10 is selected, a positive voltage + V _G is applied to the control gate 18 of a semiconductor nonvolatile memory device 10 selected.

Due to the electric field generated between the drain 31 and the control gate 18, the electrons in the drain 31 are nitrided by the Fowler-Nordheim tunnel mechanism through the second insulating film 15a shown in FIG. It is implanted into the third insulating film 16a. The injected electrons are induced in the conduction band of the third insulating film 16a, and some of the electrons are captured by the capture center 20. The programming operation is performed by the capture center 20 being negatively charged. At this time, the fourth insulating film 17a prevents electrons from penetrating to the gate electrode side, allows electrons to be efficiently captured by the capture center 20, and
Since injection of holes from the gate electrode side can be prevented, captured electrons are prevented from being neutralized.

Next, the programming operation of the electrically variable semiconductor nonvolatile memory circuit shown in FIG. 3 having the semiconductor nonvolatile memory element having the structure shown in FIG. 2 will be described. FIG.
When programming a desired semiconductor nonvolatile memory element 10 among a plurality of semiconductor nonvolatile memory elements 10 having the structure of FIG. 2 constituting the storage array 50, a specific row address line, for example, a row address line 53m applying a negative voltage -V _G, the remaining row address lines as well as to the ground potential, a particular column address line, a positive voltage + V _D for example the column address line 51n. Thus, the positive voltage + V _D is applied to the drain 31 of the nonvolatile semiconductor memory element 10 is selected, a negative voltage -V _G is applied to the control gate 18 of a semiconductor nonvolatile memory device 10 selected.

Due to the electric field generated between the drain 31 and the control gate 18, electrons in the control gate 18 are injected into the third insulating film 16b by the Fowler-Nordheim tunnel mechanism through the fourth insulating film 17b. The injected electrons are induced in the conduction band of the third insulating film 16b,
Some of the electrons are captured by the capture center 20. The programming operation is performed by the capture center 20 being negatively charged. At this time, the second insulating film 15b prevents electrons from penetrating to the source 35 and the drain 31 side, and allows the trapping center 20 to efficiently trap electrons. Further, injection of holes from the source 35 and the drain 31 side can be prevented, so that the captured electrons are prevented from being neutralized.

[Read Operation] Next, a read operation will be described. In this read operation, the single electron transistor 14 is used.

The operating principle of the single-electron transistor 14 is known, and is described, for example, in the literature (IEE Transaction on Magnetics, Vol. MAG).
-23, No. 2,1142 (1986), KKLi
kharev). The operation of the single-electron transistor 14 in the semiconductor nonvolatile memory element 10 will be described.

In FIG. 4, when a voltage V _W is applied to the control gate 18 via the row address line 53m and a voltage V _D is applied to the drain 31 of the single electron transistor 14, the current I flowing through the drain 31 is: As shown in FIG. However, when V _W = 0 V, it is assumed that the charge amount Q _T stored in the capture center 20 is 0 and the charge amount Q ₀ stored in the island 33 is 0. The voltage V _W is applied to the control gate 18.
Is applied, a charge is induced in the capacitor between the island 33 and the capture center 20. The charge amount Q ₂ is expressed as Q ₂ = C ₀ V _W (1). However,

[0044]

(Equation 1) It is. When Q ₂ is equal to a half integral multiple of the elementary charge e of the electron, ie,

[0045]

(Equation 2) At this time, the current I becomes maximum and the single electron transistor is turned on. Except for the vicinity of the gate voltage at which the current I is maximized, the current is in an off state in which the current is completely suppressed. This suppression of current is known as the Coulomb blockade effect,
The periodic current oscillation is called Coulomb blockade oscillation.

The following conditions are required in order for the Cron blockade effect to be exhibited.

[0047]

(Equation 3) The sum of the capacitances associated with the islands 33, 2C + C ₀
Equally, it is the sum of the two sums 2C of the capacitance of the tunnel barrier and the capacitance C ₀ of the control gate. K _B T is the Boltzmann constant, and T is the operating temperature of the element. In order to satisfy the condition of equation (4) in a room temperature environment (T = 300K),

[0048]

(Equation 4) For that purpose, the diameter of the island 33 needs to be 10 nm or less.

The case where a finite charge (Q _T ≠ 0) exists in the trapping center 20 in the initial state before the application of the voltage V _W will be discussed. Assuming that the charge Q _T is stored in the capture center 20, the charge Q ₂ on the capacitor between the island 33 and the capture center 20 becomes

[0050]

(Equation 5) Becomes When Q ₂ is considered in the same manner as equation (2), when Q ₂ is a half integral multiple of the elementary charge e of the electron, ie,

[0051]

(Equation 6) At this time, the current I becomes maximum. The value V _W of the control gate when the current is maximized is: ΔC ₂ /
It can be seen that it becomes smaller by (C ₁ + C ₂ ) 小 さ く × Q _T.

Next, a reading method will be described with reference to FIG. When the charge Q _T is accumulated in the trapping center 20, the current I flowing through the source 35 of the single electron transistor 14 becomes maximum when the value V _{W of the} control gate satisfies the condition of the expression (6). It is. Accumulated charge Q
_The read operation is performed by utilizing the fact that the value of V _W at which the current I becomes maximum changes depending on _T.

During the programming operation, the charge amount that changes the Coulomb blockade oscillation by １ ／ cycle is accumulated in the capture center 20. The condition at this time is that the second term on the right side of the equation (6) is equal to 1 / (4e). That is,

[0054]

(Equation 7) And Q _{T at} this time is (e / 4) × (C ₁ + C ₂ )
/ C ₂ only need to accumulate.

By the programming operation, (e / 4)
The current I with respect to the control gate voltage V _W when the electric charge of × (C ₁ + C ₂ ) / C ₂ is accumulated is shown by a broken line in FIG. The current when the charge is erased by the erase operation is shown by a solid line in FIG.

When the control gate voltage V _W is at the ground potential, the current I is 0 when the charge is programmed and erased, and the single-electron transistor 14 is off. On the other hand, V _W is _calculated as V _W = V _W1 = e / (4
If set to C _0), when the current I when the charge is written flows as indicated by a broken line in FIG. 6, the single-electron transistor 14 is turned on, charges are erased, Single-electron transistor 14 remains off.

When the single-electron transistor 14 is turned on, a potential drop occurs in the load resistor 61 in the detection amplifier 54n shown in FIG. Occur. This potential difference is amplified and output by the differential amplifier circuit 62. When the single-electron transistor 14 is off, no potential drop occurs in the load resistor 61 and no potential difference occurs between the two inputs of the differential amplifier circuit 62.

In order to read the selected semiconductor nonvolatile memory element 10, the selected row address line 53
The voltage V _W = V _W1 is applied to the control gate connected to m, and the other row address lines are kept at the ground potential. Further, V _D is applied to the selected column address line 51n, and the other column address lines are set to the ground potential. Selected column address line 51n
Among a plurality of single electron transistors 14 connected to
Other than the single electron transistor 14 connected to the selected row address line 53m, the transistor is always off. Because the control gate 18 is grounded, the capture center 2
This is because the single-electron transistor 14 is in the off state regardless of the presence or absence of the electric charge accumulated in 0.

The single-electron transistor 14 connected to the selected row address line 53m and the selected column address line 51n is off when no charge is stored, and the charge is stored. In this case, it is turned on. Because the voltage V _W1 is applied to the control gate voltage of the selected single electron transistor 14,
This is because the current I flows as shown by the broken line in FIG.
Therefore, the contents of the selected semiconductor nonvolatile memory element 10 can be read.

[0060]

【Example】

(First Embodiment) Next, an embodiment of the semiconductor nonvolatile memory element of the present invention will be described. As shown in the cross-sectional view of FIG. 7A-1 and the top view of FIG.
2 having a thickness of several nm to several hundreds of n through an insulating film 12.
m, boron concentration from 10 ¹⁴ to 10 ¹⁸ cm ^-3 , plane orientation (1
00) with an upper silicon layer 71a (Silicon
onInsulator) Prepare a substrate. A negative photoresist is applied to the SOI substrate, and the source and drain regions and rough regions where single electron transistors are to be fabricated are exposed and developed using a conventional ultraviolet exposure method. Using this negative photoresist as a mask, the upper silicon layer 71
Etching a is performed to leave a source 35a and a drain region 31a, which will be described later, and a rough region where the single-electron transistor 14 is formed. In the etching, an etchant used in a conventional semiconductor manufacturing process, for example, a p-etch solution is used. FIG. 7B is a schematic view of the device after etching.
1B) and a top view of FIG. 2B-2.

Next, after a negative resist for electron beam is applied on the upper silicon layer 71a, an electron beam is irradiated to form a resist pattern having a width of several nm to several 100 nm and a length of several nm to several μm. I do. The negative resist for electron beam used at this time is a solution in which calixarene or polystyrene is dissolved in an organic solvent represented by monochlorobenzene. Next, using the resist pattern as a mask, the upper silicon layer 71a was processed by a reactive ion etching (RIE) circuit, and two narrow regions adjacent to each other were formed at the center of the narrow line. C
A thin silicon wire having the shape shown in the cross-sectional view of -1) and the top view of FIG.

In FIGS. 7 (C-1) and 7 (C-2), the regions where the fine line width is narrow are the tunnel barriers 32a and 34a.
The region surrounded by this region becomes the island 33a, and forms the single electron transistor 14. Fine line width is 10nm
To 20 nm, the length is 100 nm, and the minimum line width in the region where the fine line width is narrow is about 5 nm to 10 nm. The length of the island region 33a is about 10 nm. A 10-nm resist pattern is a well-known document which is a conventional fine processing technology (Fujita et al., Applied Physics Lett.)
er, Vol. 68, pp. 1297, (1996)). Reactive ion etching can be performed by using a time-modulated reactive ion etching technique, which is a conventional technique. A thin region may be provided in place of the narrow region at the center of the thin line.

Subsequently, as shown in the cross-sectional view of FIG. 7D-1 and the top view of FIG. 7D-2, a silicon thin wire having a thickness of 20 mm Number 200n
An m-th silicon oxide film 72a is formed. Next, a positive photoresist is applied on the upper silicon oxide film 72a,
A portion of the source 35a and the drain region 31a and a region where the single electron transistor 14 is to be formed are exposed and developed using a conventional ultraviolet exposure circuit, and then a silicon oxide film is formed using a positive photoresist as a mask. The etching of 72a is performed. In the etching, an etchant used in a conventional semiconductor manufacturing process, for example, hydrofluoric acid is used. FIG. 7E-1 is a schematic view of the device after the etching.
Are shown in the cross-sectional view of FIG.
A part of the source 35a and the drain region 31a and the single electron transistor 14 are exposed.

Next, as shown in the cross-sectional view of FIG. 8F-1 and the top view of FIG. 8F-2, a silicon oxide film 22a having a thickness of about 1 nm to about 5 nm is formed by a thermal oxidation method. I do. 7 (E-1), (E-2) by chemical vapor deposition
The silicon oxide film 72a formed in FIG.
Thick silicon oxide film layers 21a and 23a are formed with the thermal oxide film 22a in (F-2), and a part of the source 35a and the drain region 31a and a part where the single electron transistor 14 is exposed are thermally oxidized thereon. Only the film 22a is formed.

Further, as shown in the cross-sectional view of FIG. 8 (G-1) and the top view of FIG. 8 (G-2), a silicon nitride film 16 Grow. Subsequently, as shown in the cross-sectional view of FIG. 8 (H-1) and the top view of FIG. 8 (H-2), a silicon oxide film having a thickness of several tens nm to several 50 nm is formed thereon by using a chemical vapor deposition method. 17a is formed.

Next, contact holes are opened in the silicon oxide film 17a, the silicon nitride film 16 and the silicon oxide film layer 21a above the drain region 31a by photolithography and RIE etching, and then aluminum is deposited to a thickness of about 300 nm. I do. After that, the aluminum is processed by the photolithography technique and the RIE etching technique, and the sectional view of FIG.
2) As shown in the top view of FIG.
And the formation of the control gate 18 are performed simultaneously to obtain a desired structure.

The semiconductor non-volatile memory element manufactured according to this example had an element area of 50 × 50 nm, and it was confirmed that miniaturization was possible. In addition, clear Coulomb blockade oscillation was observed at a temperature of 100 K in the manufactured single-electron transistor, and it was confirmed that high-temperature operation was possible. In the characteristics of the nitride film, a desired hysteresis phenomenon was confirmed, and it was confirmed that the nitride film could be used as a storage medium.

(Second Embodiment) Next, a description will be given of a second embodiment of the semiconductor nonvolatile memory element according to the present invention. First,
As shown in the cross-sectional view of FIG. 9A-1 and the top view of FIG. 9A-2, the thickness is several nm to several hundreds nm and the boron concentration is 10 ¹⁴ From 1
0 ¹⁸ cm ^-3 , upper silicon layer 71b with plane orientation (100)
An SOI (Silicon on Insulator) substrate having the following is prepared. Next, a negative photoresist is applied to the SOI substrate, and the source and drain regions and a rough region where a single-electron transistor is to be formed are exposed to light using a conventional ultraviolet exposure method, and are developed. Subsequently, using the negative photoresist as a mask, the upper silicon layer 71b is etched to form a source 35b and a drain region 3 described later.
1b and leave a rough area where the single-electron transistor 14 is fabricated. In the etching, an etchant used in a conventional semiconductor manufacturing process, for example, a p-etch solution is used. A schematic view of the element after etching is shown in the cross-sectional view of FIG. 9B-1 and the top view of FIG. 9B-2.

Next, after a negative resist for electron beam is applied on the upper silicon layer 71b, a resist pattern having a width of several nm to several hundred nm and a length of several nm to several μm is formed by irradiating an electron beam. I do. As the electron beam resist used at this time, a solution obtained by dissolving calixarene or polystyrene in an organic solvent represented by monochlorobenzene is used. Next, using this resist pattern as a mask, the upper silicon layer 71b is processed by an RIE circuit, and has a cross-sectional view of FIG. A silicon fine wire as shown in the top view of C-2) is formed.

Of the silicon thin wires described above, the narrow areas of the thin lines are the tunnel barriers 32b and 34b, and the area surrounded by the tunnel barriers 32b and 34b is the island 33.
b, and these constitute the single electron transistor 14. Fine line width is 10nm to 20nm, length is 100
nm, and the minimum line width in a region where the thin line width is narrow is about 5 nm to 10 nm. The length of the island region 33b is about 10 nm. A 10 nm resist pattern can be formed by using the same conventional fine processing technology as in the first embodiment, and the reactive ion etching can be performed by using the time modulation type reactive ion etching technology, which is the conventional technology. It is possible.

Next, the sectional view of FIG.
As shown in the top view of 2), a silicon oxide film 72b having a thickness of several 20 nm to several 200 nm is formed on the fine silicon wires by using a chemical vapor deposition method. Next, a positive photoresist is applied on the upper silicon oxide film 72b, and a part of the source 35a and the drain region 31a and a region where the single electron transistor 14 is to be formed are exposed using a conventional ultraviolet exposure circuit. After the development, the silicon oxide film 72b is etched using the positive photoresist as a mask. In the etching, an etchant used in a conventional semiconductor manufacturing process, for example, hydrofluoric acid is used. A schematic view of the element after this etching is shown in the cross-sectional view of FIG. 9E-1 and the top view of FIG. 9E-2, showing a part of the source 35a and the drain region 31a and a single electron transistor. 14 is exposed.

Next, as shown in the sectional view of FIG. 10 (F-1) and the top view of FIG. 10 (F-2), a silicon oxide film having a thickness of several tens nm to several 50 nm is formed by a thermal oxidation method. .
The silicon oxide film 72 formed by a chemical vapor deposition method
b and the silicon oxide film formed by the thermal oxidation method, thick silicon oxide film layers 21b and 23b are formed, and the silicon oxide film 22b by the thermal oxidation method is formed in the region of the silicon oxide film 72b which has been etched away. .

Next, FIG. 10 (G-
As shown in the cross-sectional view of 1) and the top view of FIG.
Is grown. Subsequently, FIG.
As shown in the cross-sectional view of -1) and the top view of FIG. 2H, a silicon oxide film 17b having a thickness of several nm to several 5 nm is formed thereon by using a thermal oxidation method.

Next, contact holes are opened in the silicon oxide film 17b, silicon nitride film 16 and silicon oxide film layer 21b above the drain region 31a by photolithography and RIE etching, and then aluminum is deposited to a thickness of about 300 nm. I do. After that, the aluminum is processed by the photolithography technology and the RIE etching technology, and the sectional view of FIG.
-2) As shown in the top view, the electrode 7 is connected to the drain 31b.
3 and the control gate 18 are simultaneously formed to obtain a desired structure.

The semiconductor nonvolatile memory element manufactured according to this example has an element area of 50 × 50 nm, and it can be confirmed that the semiconductor nonvolatile memory element can be miniaturized. In addition, clear Coulomb blockade oscillation was observed at a temperature of 100 K in the manufactured single-electron transistor, and it was confirmed that high-temperature operation was possible. In the characteristics of the nitride film, a desired hysteresis phenomenon was confirmed, and it was confirmed that the nitride film could be used as a storage medium.

(Third Embodiment) Next, a third embodiment of the present invention will be described. FIG. 3 shows an embodiment of the semiconductor memory circuit. The semiconductor nonvolatile memory circuit includes an array 50 of the semiconductor nonvolatile memory elements 10. Peripheral circuits related to the semiconductor nonvolatile memory circuit include a row address decoding circuit 43, a column address decoding circuit 41, and a plurality of detection amplifiers 5.
4a to 54z are included.

The semiconductor nonvolatile memory circuit was constructed using the semiconductor nonvolatile memory device described in the first embodiment. When a row address and a column address were selected and programmed, erased, and read, normal operation was confirmed.

Here, the first embodiment is used as the semiconductor nonvolatile memory element 10, but it is apparent that the semiconductor nonvolatile memory element of the second embodiment may be used.

[0079]

As described above, according to the present invention,
As a semiconductor non-volatile memory element, a single electron transistor capable of reading a change in single electron charge is used as a storage medium using a trapping center of a silicon nitride film as a storage medium. A circuit can be configured.

In a conventional semiconductor nonvolatile memory circuit using an MNOS memory element, a high electric field had to be applied to an insulating film because thousands of electrons were required for programming. According to the report, since a single-electron transistor that can read a change in the charge of a single electron is used, the number of electrons to be programmed in the storage medium can be reduced from several hundred to several tens. The life of the film is significantly extended, and the power consumption can be reduced in proportion to the decrease in the number of electrons.

The single-electron transistor used in the present invention can be miniaturized without the obstacle to miniaturization of the conventional MNOS memory element, that is, without the short channel effect. Further, by using a stacked structure and using a single-electron transistor capable of miniaturizing a readout circuit, a miniaturized large-scale integrated circuit which has not been achieved in the past can be obtained.

[Brief description of the drawings]

FIG. 1 is a sectional structural view and a top structural view of a first embodiment of a semiconductor nonvolatile memory element of the present invention.

FIG. 2 is a sectional structural view and a top structural view of a second embodiment of the semiconductor nonvolatile memory element of the present invention.

FIG. 3 is a configuration diagram of an embodiment of a semiconductor nonvolatile memory circuit according to the present invention.

4 is an equivalent circuit diagram of a semiconductor nonvolatile memory element and a detection amplifier of the semiconductor nonvolatile memory circuit in FIG. 3, a symbol of a tunnel barrier used therein, and an equivalent circuit thereof.

FIG. 5 is a diagram showing a relationship between a voltage applied to a control gate and a current flowing through a drain of the single-electron transistor in FIGS. 4A and 4B.

FIG. 6 is a diagram showing a relationship between a voltage applied to a control gate and a current flowing through a drain in the programmed state and the erased state of the single-electron transistor of FIG. 4A.

FIGS. 7A and 7B are a cross-sectional view and a top view for explaining the method for manufacturing the semiconductor nonvolatile memory element according to the first embodiment of the present invention (part 1); FIGS.
It is.

FIG. 8 is a cross-sectional view and a top view (part 2) illustrating the method for manufacturing the semiconductor nonvolatile memory element according to the first embodiment of the present invention;
It is.

FIG. 9 is a cross-sectional view and a top view (part 1) illustrating a method for manufacturing a semiconductor nonvolatile memory element according to a second embodiment of the present invention.
It is.

10A and 10B are a cross-sectional view and a top view (part 2) illustrating a method for manufacturing a semiconductor nonvolatile memory element according to a second embodiment of the present invention.

[Explanation of symbols]

Reference Signs List 10 semiconductor nonvolatile memory element 12 semiconductor substrate 13 first insulating film 14 single electron transistor 15a, 21a, 22a, 23a, 15b, 21b, 2
2b, 23b Second insulating film 16a, 24a, 25a, 26a, 16b, 24b, 2
5b, 26b Third insulating film 17a, 17b Fourth insulating film 18 Control gate 20 Capture center 31 Drain 32, 34 Tunnel barrier 33 Island 35 Source 41 Column address decoding circuit 43 Row address decoding circuit 50 Storage array 51a, 51b, 51n, 51z Column address line 52 Ground line 53a, 53b, 53m, 53z Row address line 54a, 54b, 54n, 54z Detection amplifier 61 Load resistance 62 Amplifier circuit 71a, 71b Silicon layer 72a, 72b Silicon oxide film

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H01L 21/8247 H01L 27/10 451 H01L 29/78 H01L 29/788 H01L 29/792

Claims (9)

(57) [Claims] A single-electron transistor is formed on a first insulating film covering a semiconductor substrate, a second insulating film, a third insulating film having an electron capture center, and a second insulating film on the single-electron transistor. A semiconductor non-volatile memory element, wherein four insulating films are sequentially stacked, a control gate electrode is formed on the fourth insulating film, and the electron capture center is used as a storage medium. 2. The third insulating film having an electron capture center is a silicon nitride film, the second insulating film and the fourth insulating film are silicon oxide films, respectively, and the second insulating film is 2. The semiconductor non-volatile memory element according to claim 1, wherein a thickness of the semiconductor non-volatile memory element is smaller than that of the fourth insulating film. 3. The third insulating film having the electron trapping center is a silicon nitride film, the second insulating film and the fourth insulating film are silicon oxide films, respectively, and the fourth insulating film is 2. The semiconductor non-volatile memory element according to claim 1, wherein the semiconductor non-volatile memory element is formed to be thinner than the second insulating film. 4. The single-electron transistor is a degenerated semiconductor layer having a high impurity concentration and processed into a thin line shape having a plurality of regions having a small width or thickness adjacent to a central portion. A region having a small width or thickness serves as a tunnel barrier, a region surrounded by the plurality of regions having a small width or thickness serves as an island, and includes a source and a drain which are electrically insulated by the island. 2. The nonvolatile semiconductor memory device according to claim 1, wherein: 5. A memory array in which a plurality of semiconductor nonvolatile memory elements are arranged in a matrix, and two or more of the plurality of semiconductor nonvolatile memory elements constituting the memory array, which are arranged in the same row. A row address decoding circuit for simultaneously applying a gate voltage to the control gate of the semiconductor nonvolatile memory element via the same row address line; and a same column among the plurality of semiconductor nonvolatile memory elements forming the storage array. A plurality of sense amplifiers connected to the drains of two or more semiconductor nonvolatile memory elements disposed at the same time via the same column address line; and a column address decoder for inputting a column address signal to each of the plurality of sense amplifiers. And a plurality of semiconductor nonvolatile memory elements constituting the memory array, each of which has a single electron on a first insulating film covering a semiconductor substrate. A transistor is formed, a second insulating film, a third insulating film having an electron capture center, and a fourth insulating film are sequentially stacked on the single-electron transistor, and a control gate is formed on the fourth insulating film. An electrode is formed, the electron capture center is used as a storage medium, a drain of the single electron transistor is connected to the column address line, a source is grounded, and the control gate electrode is connected to the row address line. A semiconductor nonvolatile memory circuit, which is connected. 6. The semiconductor nonvolatile memory circuit according to claim 5, wherein a first column address line selected from the plurality of column address lines and a first column address line selected from the plurality of row address lines.
In order to read the first semiconductor nonvolatile memory element specified by each combination with the row address line, a column address decoding circuit is connected to the first column address line via the detection amplifier. Is applied to a first column address line, and a second positive potential is applied from the row address decoding circuit to the control gate electrode of the first semiconductor nonvolatile memory element via the first row address line. And the control gate electrodes of a plurality of second semiconductor nonvolatile memory elements connected to a second row address line other than the first row address line are each set to a ground potential, and the second semiconductor When the single electron transistor of the nonvolatile memory element is turned off and the second positive potential is applied to the control gate electrode of the first semiconductor nonvolatile memory element, the first semiconductor nonvolatile memory element is turned off. State, the output of the single-electron transistor is off due to Coulomb blockade, and when the first semiconductor non-volatile storage element is in the programming state, the single-electron transistor is turned on. A method for operating a semiconductor nonvolatile memory circuit, characterized in that reading is performed by utilizing the following. 7. The semiconductor nonvolatile memory circuit according to claim 5, wherein a first column address line selected from the plurality of column address lines and a first column address line selected from the plurality of row address lines.
At the time of erasing the first semiconductor nonvolatile memory element specified by each combination with the row address line, a positive or negative potential is applied to the first column address line, and a negative or positive potential is applied. Is applied to the first row address line to move the electric charge accumulated at the capture center of the single electron transistor constituting the first semiconductor nonvolatile memory element through a Fowler-Nordheim tunnel mechanism. When programming the erased first semiconductor nonvolatile memory element, a negative or positive potential is applied to the first semiconductor nonvolatile memory element.
By applying a positive or negative potential to the first row address line, thereby causing a charge to be applied to the capture center of the single electron transistor constituting the first semiconductor nonvolatile memory element. An operation method of a semiconductor nonvolatile memory circuit, wherein the semiconductor nonvolatile memory circuit is moved through a Fowler-Nordheim tunnel mechanism. 8. The first semiconductor nonvolatile memory element,
The third insulating film having the electron trapping center is a silicon nitride film, the second insulating film and the fourth insulating film are each a silicon oxide film, and the second insulating film is the fourth insulating film.
In the structure having a thickness smaller than that of the insulating film, a positive potential is applied to the first column address line during erasing, and a negative potential is applied to the first row address line. 8. A nonvolatile semiconductor memory according to claim 7, wherein a negative potential is applied to said first column address line during programming, and a positive potential is applied to said first row address line. How the storage circuit operates. 9. The first semiconductor nonvolatile memory element,
The third insulating film having the electron capture center is a silicon nitride film, the second insulating film and the fourth insulating film are each a silicon oxide film, and the fourth insulating film is the second insulating film.
In the structure having a thickness smaller than that of the insulating film, a negative potential is applied to the first column address line during erasing, and a positive potential is applied to the first row address line. 8. A nonvolatile semiconductor memory according to claim 7, wherein during programming, a positive potential is applied to said first column address line, and a negative potential is applied to said first row address line. How the storage circuit operates.