JP2840618B2 - Method for manufacturing semiconductor device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming an interlayer insulating film formed between a lower electrode or a wiring and an upper wiring. .

(Prior art) Conventionally, a PSG film (phosphorus glass film) has been used as an interlayer insulating film.
However, recently, BPSG film (boron-phosphorus glass film) has been used instead of PSG film because heat treatment temperature for smoothing the surface of interlayer insulating film can be lowered and moisture resistance is good. Are widely used as interlayer insulating films.

FIG. 3 is a process sectional view showing a method for manufacturing a conventional semiconductor device using a BPSG film as an interlayer insulating film. Moreover,
In this method, a polycrystalline silicon embedding method is used as a method for forming a contact portion.

The method of manufacturing this conventional semiconductor device will be described. First, as shown in FIG.
A field oxide film 2 is formed by using the LOCOS method, and the substrate 1 is divided into an element formation region 3 and an element isolation region 4.

Next, as shown in FIG.
An n-channel MOS transistor 5 having an LDD structure is formed, and at the same time, an electrode wiring layer 6 is formed in the element isolation region 4. Next, a silicon oxide film 7 is formed on the entire surface by a normal pressure CVD method to a thickness of about 1000. Subsequently, the BPSG film 8 was deposited for 500
It is formed to a thickness of 0 to 7000 mm.

Next, heat treatment is performed at a temperature of 900 to 950 ° C. in an N ₂ gas atmosphere for 15 to 30 minutes to flatten the surface of the BPSG film 8 as shown in FIG.

Next, as shown in FIG. 3C, the BPSG film 8 and the silicon oxide film 7 are formed on the electrode wiring layer 6 and the MOS transistor 5 by the ordinary photolithographic etching technique.
Contact holes 9a, 9b, and 9c are formed on gate electrode 5a and n ⁺ diffusion layer 5b, respectively. At this time, the contact holes 9a, 9b,
9c has an outer diameter in the range of 0.6 μm ^□ to 0.8 μm ^□ .

Next, a polycrystalline silicon film of 1 μm is deposited on the entire surface by a low pressure CVD method.
about m. After that, the polycrystalline silicon film is etched back using anisotropic etching technology by RIE method,
As shown in FIG. 3 (c), the polycrystalline silicon film is formed only in the contact holes 9a, 9b, 9c by the polycrystalline silicon films 10a, 10b, 10c.
Leave as.

Next, the polycrystalline silicon film 10 in the contact holes 9a, 9b, 9c
An n-type impurity (for example, phosphorus (P) or arsenic (As)) is introduced into a, 10b, and 10c by ion implantation. The ion implantation conditions at this time are as follows: the acceleration energy is 40 KeV, and the dose is 1 × 10 ¹⁶
cm- ² . Next, at a temperature of 950 ゜ to 1000 ° C for 30 minutes N
Heat treatment is performed in a ₂ gas atmosphere, and the polycrystalline silicon films 10a, 1
The impurities in 0b and 10c are activated.

Then, the polycrystalline silicon film in the contact holes 9a, 9b, 9c
The natural oxide films on the surfaces 10a, 10b, and 10c are removed by etching with about 1% hydrofluoric acid solution.

Thereafter, as shown in FIG. 3 (d), an Al-Si film or an Al-Si-Cu film 11 is deposited on the entire surface by sputtering at about 7000 °. Then, the Al-Si film or Al-Si-Cu
The metal wiring is formed by patterning the film 11 using a normal photolithography etching technique. Finally, sintering is performed at 400 ° C. for 20 minutes in an H ₂ gas atmosphere to improve the contact between the metal wiring and the polycrystalline silicon films 10a, 10b, 10c. As described above, the semiconductor device in which the BPSG film 8 is used as the interlayer insulating film and the buried contacts are formed by the polycrystalline silicon films 10a, 10b, and 10c as the contact portions is completed.

The silicon oxide film 7 is used for heat treatment for flattening the BPSG film 8 and heat treatment for activating impurities in the polycrystalline silicon films 10a, 10b, 10c. It is formed to prevent impurities from diffusing into the underlayer. This silicon oxide film 7 is also a part of the interlayer insulating film.

(Problems to be Solved by the Invention) However, in the above-described conventional manufacturing method, heat treatment for planarizing the surface of the BPSG film 8 is performed at a temperature of 900 to 950 ° C. for 15 minutes.
When carried out in 30 minutes N ₂ gas atmosphere, the crystallization phenomenon, as shown in FIG. 3 (c), hemispherical particles 12 there has been a problem that deposited on the surface of the BPSG film 8.

In the above manufacturing method, the same heat treatment exists to activate the impurities in the polycrystalline silicon films 10a, 10b, and 10c buried in the contact portions, so that the fine particles 12 also precipitate on the surface of the BPSG film 8 at this time. There is a problem to do. The fine particles 12 cause local short-circuiting and disconnection of the upper metal wiring, making it difficult to manufacture a highly reliable semiconductor device.

Further, in the above conventional manufacturing method, the polycrystalline silicon film 10
During the heat treatment for activating the impurities in a, 10b, and 10c, the solid-phase diffusion indicated by the arrow A in FIG. 3C and the auto-doping indicated by the arrow B (the impurity once diffused out again falls) Due to the phenomenon, impurities in the BPSG film 8, particularly p-type boron, are introduced into the n-type polycrystalline silicon films 10 a, 10 b, and 10 c, thereby causing a problem that contact resistance increases.

The present invention (first and second inventions) has been made in view of the above points, and prevents the deposition of fine particles on the surface of a BPSG film during a heat treatment for planarizing the surface of the BPSG film. The purpose is to:

Another object of the present invention is to prevent the generation of the same fine particles during the heat treatment for activating the impurities in the polycrystalline silicon film buried in the contact portion, in addition to the generation of the fine particles during the above-mentioned flattening. I do. Still another object of the present invention is to prevent impurity diffusion from the BPSG film into the buried polycrystalline silicon film during the heat treatment for activation.

(Means for Solving the Problems) In order to solve the above-described problems, the present invention provides an interlayer insulating film in which a silicon oxide film, a first polycrystalline silicon film, and a silicate glass film are sequentially stacked on a semiconductor substrate. Forming, performing a first heat treatment on the silicate glass film by a wet oxidation method to flatten the surface of the silicate glass film, and partially forming a portion of the first polycrystalline silicon film from a surface contacting the silicate glass film. The film is converted to a silicon oxide film by a thickness, and the contact hole opened in the interlayer insulating film is filled with a second polycrystalline silicon film, an impurity is introduced into the second polycrystalline silicon film, and the impurity is activated. Is performed in a mixed gas atmosphere of N ₂ and O ₂ to convert the remaining portion of the first polycrystalline silicon film into a silicon oxide film and to form the second polycrystalline silicon film. An oxide film is formed on the upper surface and side surfaces of the crystalline silicon film, and after removing the oxide film on the upper surface of the second polycrystalline silicon film, a wiring layer connected to the second polycrystalline silicon film is formed.

(Operation) In the first and second aspects of the present invention, the heat treatment for planarizing the surface of the BPSG film is performed by the wet oxidation method, which is a heat treatment in an H ₂ O gas atmosphere. According to this wet oxidation method, it is possible to prevent the generation of fine particles due to the crystal precipitation phenomenon on the surface of the BPSG film during the heat treatment for planarization. Why it could be prevented has not been analyzed. However, experiments have shown that the generation of fine particles can be prevented.

Further, according to the wet oxidation method, the surface of the BPSG film is flattened more favorably.

In the second of the present invention, including O _2, because heat treatment is performed for activating the impurity in the contact portion buried polycrystalline silicon film in a mixed gas atmosphere of N ₂ and O _2, also reasons However, as is confirmed by experiments, the generation of fine particles on the surface of the BPSG film during this heat treatment is prevented.

At the time of the heat treatment for activating the impurities and the heat treatment by the above-mentioned wet oxidation method, the polycrystalline silicon film of the interlayer insulating film intermediate layer is oxidized by O ₂ in the atmosphere penetrating through the BPSG film. And converted into a silicon oxide film. In other words this time the heat treatment, it means that the invading O ₂ was stopped at the polycrystalline silicon film of the interlayer insulating film intermediate layer, the O ₂ invading like base element is oxidized Adverse effects can be prevented. Also, since the adverse effects of intrusion O ₂ were removed in this way,
The wet oxidation method can be used for the heat treatment for planarization, and the heat treatment for activating impurities is performed using N ₂ and O _2.
This can be said to be performed in a mixed gas atmosphere. It can be said that the generation of fine particles can be prevented.

According to the second aspect of the present invention, at the time of the heat treatment for activating the impurities, the O ₂ gas in the atmosphere invading through the BPSG film is used.
The side and upper surfaces of the polycrystalline silicon film buried in the contact portion are oxidized by O _{2 that is in} direct contact with the contact portion, thereby forming an oxide film. Then, during the heat treatment for activating the impurities, the BP is formed by solid-phase diffusion or auto-doping.
Impurities in the SG film are prevented from being introduced into the buried polycrystalline silicon film.

Embodiment An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a process sectional view showing a first embodiment of the present invention. In this first embodiment, first, as shown in FIG. 1 (a), a field oxide film 22 is formed on a p-type silicon substrate 21 using a normal LOCOS method to a thickness of about 6000.degree. It is divided into a region 23 and an element isolation region 24.

Next, as shown in FIG.
An n-channel MOS transistor 25 having an LDD structure is formed, and at the same time, an electrode wiring layer 26 is formed in the element isolation region 24.

Next, as shown in FIG. 1C, a silicon oxide film 27 is formed on the entire surface of the substrate 21 by a normal pressure CVD method so as to have a thickness of about 500 °.
Further, a polycrystalline silicon film 26 is formed thereon using a low pressure CVD method.
Is formed to a thickness of about 500 mm. Then, As is introduced into this polycrystalline silicon film 28 by an ion implantation method. Subsequently, the BPSG film 2 is formed on the As-doped polycrystalline silicon film 28 by a normal pressure CVD method.
9 is formed to a thickness of about 5000 to 7000 mm.

Thereafter, heat treatment for planarizing the surface of the BPSG film 29 is performed by a wet oxidation method. Specifically, heat treatment is performed at a temperature of 850 ° C. to 950 ° C. in an H ₂ O gas atmosphere for 15 minutes to 30 minutes.
By this heat treatment, the BPSG film 29 is fluidized, and the surface becomes flat as shown in FIG. At this time, according to the wet oxidation method, no fine particles are generated on the surface of the BPSG film 29 due to a crystal precipitation phenomenon. Also, during this heat treatment, the BPSG film
The polycrystalline silicon film 28 is oxidized by O _{2 in} the atmosphere that has penetrated through 29 (and accelerated by doping with As), and becomes a complete silicon oxide film 30. This conversion to silicon oxide film, by consuming O ₂ which has penetrated, is no longer a problem, such as such as background element is oxidized by entering O _2.

Thereafter, contact holes are made in the interlayer insulating films of the BPSG film 29 and the silicon oxide films 30, 27, and metal wiring is formed.

FIG. 2 shows a second embodiment of the present invention. In the second embodiment, a polycrystalline silicon embedded contact is formed as a contact portion. In this second embodiment, as shown in FIGS. 2 (a), (b) and (c), the BPSG
Until the surface of the film 29 is flattened by the wet oxidation method, the same steps as those in the first embodiment shown in FIG. 1 are performed. However, As is not introduced into the polycrystalline silicon film 28 so that accelerated oxidation does not occur. As a result, at the time of heat treatment for surface flattening by the wet oxidation method, as shown in FIG. 2C, the polycrystalline silicon film 28 (500 mm thick) is converted from a 300-400 mm thick silicon oxide film 30 from the upper surface side. And the lower surface side of 100 to 200 mm remains as a polycrystalline silicon film. It is to leave the polycrystalline silicon film 28 of 100~200Å for the O ₂ blocking during the heat treatment of the impurity activation to be described later.

When the planarization of the surface of the BPSG film 29 is completed in the second embodiment, next, the normal photolithography is applied to the four-layer film of the BPSG film 29, the silicon oxide film 30, the polycrystalline silicon film 28 and the silicon oxide film 27. By the etching technique, as shown in FIG. 2D, the contact holes 31a, 31b are formed on the electrode wiring layer 26 and on the gate electrode 25a and the n ⁺ diffusion layer 25b of the MOS transistor 25, respectively.
31b and 31c are formed. At this time, the contact holes 31a, 31b, 31c
Has an outer diameter in the range of 0.6 μm ^□ to 0.8 μm ^□ . Also,
As an etching method, an anisotropic etching technique, specifically, an RIE method is used.

Next, a polycrystalline silicon film of 1 μm is deposited on the entire surface by a low pressure CVD method.
about m. After that, the polycrystalline silicon film is etched back using anisotropic etching technology by RIE method,
As shown in FIG. 2D, the contact holes 31a, 31b, 31
Polycrystalline silicon film 32a, 32b, 3
Leave as 2c.

Next, n-type impurities (for example, phosphorus (P) or arsenic (As)) are introduced into the polycrystalline silicon films 32a, 32b, 32c in the contact holes 31a, 31b, 31c by ion implantation. The ion implantation conditions at this time are as follows: the acceleration energy is 40 KeV, and the dose is 1 ×.
It is about 10 ^{16 to} 1.5 × 10 ¹⁶ cm ^-2 .

Next, heat treatment is performed at a temperature of 900 to 950 ° C. for 30 minutes in a mixed gas atmosphere of N ₂ and O ₂ , and the polycrystalline silicon films 32a, 32b, 32c
Activate impurities therein. At this time, according to this heat treatment method using a mixed gas atmosphere of N ₂ and O ₂ , generation of fine particles due to the crystal precipitation phenomenon on the surface of the BPSG film 29 can be prevented. At this time, the remaining polycrystalline silicon film 28 having a thickness of 100 to 200 mm is formed by O _{2 in} the atmosphere which has penetrated through the BPSG film 29.
Is oxidized. Thus, the polycrystalline silicon film 28 becomes a silicon oxide film 30 as shown in FIG. 2 (e). The conversion to the silicon oxide film, in other words, the consumption of the intrusion O ₂ prevents the underlying element and the like from being oxidized.
At the time of this heat treatment, O ₂ invading through the BPSG film 29 or O ₂ in an atmosphere in direct contact with
As shown in FIG. 2 (e), the polysilicon films 32a, 32b, 32
The side and top surfaces of c are oxidized, and an oxide film 33 is formed. Due to the formation of this oxide film 33, the BPSG film
Impurities are prevented from being introduced from 29 into the polycrystalline silicon films 32a, 32b, 32c by solid phase diffusion or auto doping.
The partial pressure of O _{2 in} the N ₂ and O ₂ mixed gas is about O ₂ / (N ₂ + O ₂ )
= 0.1. Under this condition, the polycrystalline silicon films 32a, 32
An oxide film 33 (silicon oxide film) of about 200 ° is formed on the side walls of b and 32c and about 500 ° is formed on the upper surface.

Thereafter, the contact portion buried polycrystalline silicon film 32a,
The oxide film 33 on the upper surfaces of 32b and 32c is removed with a hydrofluoric acid-based solvent.

Thereafter, the entire surface of the BPSG film 29 including the upper surfaces of the polycrystalline silicon films 32a, 32b, and 32c is formed by the second sputtering method.
As shown in FIG. 3F, the Al-Si film or the Al-Si-Cu film 34 is
Deposit about 7000mm.

After that, the Al-Si film or the Al-Si-Cu film 34 is patterned by using a normal photolithography etching technique to form a metal wiring. Finally, in an H ₂ gas atmosphere
Sintering is performed at 400 ° C. for 20 minutes to improve the contact between the metal wiring and the polycrystalline silicon films 32a, 32b, 32c.

(Effects of the Invention) As described in detail above, according to the manufacturing method of the description (first and second inventions), the heat treatment for planarizing the surface of the BPSG film as the interlayer insulating film is performed by wet oxidation. Since the heat treatment is performed by the method, it is possible to prevent the generation of fine particles due to the crystal precipitation phenomenon on the surface of the BPSG film during this heat treatment. Further, according to the wet oxidation method, the surface of the BPSG film can be flattened more favorably.

According to the second manufacturing method of the present invention, the heat treatment for activating the impurities in the polycrystalline silicon film buried in the contact portion is performed in a mixed gas atmosphere of N ₂ and O _2. The generation of fine particles on the surface of the BPSG film can also be prevented.

If the generation of fine particles can be prevented and flattening can be satisfactorily performed in this way, a local short circuit or disconnection of the upper wiring can be prevented, and a highly reliable semiconductor device can be manufactured.

Further, the silicon oxide film as the initial interlayer insulating film, a polycrystalline silicon film, and allowed to form a three-layered film of the BPSG film, during the heat treatment of polycrystalline silicon film, O ₂ in the atmosphere invading
Since the O ₂ was stopped at the polycrystalline silicon film portion by converting to a silicon oxide film,
Despite using a wet oxidation method and a heat treatment in a mixed gas atmosphere of N ₂ and O ₂ as the heat treatment method, problems such as oxidation of the underlayer by O ₂ can be solved.

Furthermore, according to the second aspect of the present invention, since the side and top surfaces of the polycrystalline silicon film buried in the contact portion are oxidized by O _{2 in} the atmosphere, solid-phase diffusion from the BPSG film or Impurities can be prevented from being introduced into the buried polycrystalline silicon film by the auto doping, and the contact resistance can be reduced.

[Brief description of the drawings]

FIG. 1 is a process sectional view showing a first embodiment of a method of manufacturing a semiconductor device according to the present invention, FIG. 2 is a process sectional view showing a second embodiment of the present invention, and FIG. FIG. 7 is a process sectional view illustrating the method of manufacturing the semiconductor device. 21 ... p-type silicon substrate, 27 ... silicon oxide film, 28 ...
... Polycrystalline silicon film, 29 ... BPSG film, 30 ... Silicon oxide film, 31a, 31b, 31c ... Contact hole, 32a, 32b, 32c ...
Polycrystalline silicon film, 33 ... oxide film, 34 ... Al-Si film or Al-Si-Cu film.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H01L 21/3205 H01L 21/3213 H01L 21/718

Claims (2)

(57) [Claims] A step of forming an interlayer insulating film in which a silicon oxide film, a first polycrystalline silicon film and a silicate glass film are sequentially laminated on a semiconductor substrate; and a wet oxidation method for the silicate glass film. Performing a first heat treatment to planarize the surface of the silicate glass film, and convert a part of the first polycrystalline silicon film to a silicon oxide film from a side of the first polycrystalline silicon film which is in contact with the silicate glass film; Filling a contact hole opened in the insulating film with a second polycrystalline silicon film and introducing an impurity into the second polycrystalline silicon film; and performing a second heat treatment for activating the impurity with N ₂ . O ₂
Converting the remaining portion of the first polycrystalline silicon film into a silicon oxide film by forming the first polycrystalline silicon film in a mixed gas atmosphere, and forming an oxide film on the upper surface and side surfaces of the second polycrystalline silicon film. After removing the oxide film on the upper surface of the polycrystalline silicon film,
Forming a wiring layer connected to the second polycrystalline silicon film. 2. A partial film thickness of said first polycrystalline silicon film converted into said silicon oxide film by said first heat treatment is 3/5 to 4/4 of a film thickness of said first polycrystalline silicon film. 5. The method for manufacturing a semiconductor device according to claim 1, wherein the method is 5.