JP2845604B2 - Color solid-state imaging device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a color solid-state imaging device using a single-plate color solid-state imaging device.

FIG. 8 shows an example of a color solid-state imaging device.

In FIG. 1, image light from a subject (not shown) is supplied via an imaging lens 1 to a single-chip CCD color solid-state imaging device 2 having a complementary color checkerboard type color filter.

FIG. 9 is a schematic diagram of the color coding of the image pickup device 2. As shown in the figure, field reading is performed. In the A field, charges are mixed in pairs such as A1 and A2, and in the B field, charges are mixed in pairs such as B1. And the horizontal shift register
From the Hreg, charges are output in the order of A1, A2,... In the A field, and in the order of B1,.

Here, as shown in FIG. 10, the order of the charges a, b,... Is (Cy + G), (Ye + Mg),.
・ ・ In the A2 line, (Cy + Mg), (Ye +
G),..., B1 line, (G + Cy), (Mg
+ Ye),.

The charges output from the image sensor 2 as described above are supplied to a CDS circuit (correlated double sampling circuit) 3 and
It is extracted from the S circuit 3 as an imaging signal. By using the CDS circuit 3, reset noise can be reduced as is well known.

Note that the timing pulse necessary for the above-described image sensor 2 and CDS circuit 3 is supplied from the timing generator 4.

Here, a process for obtaining a luminance signal Y and a chroma signal (color difference signal) from the imaging signal output from the CDS circuit 3 will be described.

The luminance signal Y is obtained by adding signals of adjacent competitors. . In FIG. 10, a + b, b + c, c + d,
.. are formed in order.

For example, the A1 line is approximated by the following equation. Here, Cy = B + G, Ye = R + G, Mg = B + R.

 Y = {(Cy + G) + (Ye + Mg)} × 1/2 = (2B + 3G + 2R) × 1/2 (1) Further, the A2 line is approximated by the following equation.

Y = {(Cy + Mg) + (Ye + G)} × 1/2 = (2B + 3G + 2R) × 1/2 (2) Other lines in the A field and lines in the B field are similarly approximated.

The chroma signal is obtained by subtracting the adjacent signal, and will be described in detail with reference to FIGS. 11 and 12.

A1 line is a = (Cy + G), b = (Ye + Mg), ...
(In FIG. 11A). A1 line signal is sampling pulse SHP1 (illustrated in Fig.E)
To form a continuous signal S1 of (Cy + G) (shown in FIG. B). Further, the signal of the A1 line is sampled by the sampling pulse SHP2 (shown in FIG. F) to form a continuous signal S2 of (Ye + Mg) (shown in FIG. C). Then, the signal S1 is subtracted from the signal S2 to obtain a red color difference signal RY (illustrated in FIG. D).
That is, it is approximated by the following equation.

RY = {(Ye + Mg)-(Cy + G)} = (2R-G) (3) The A2 line is a = (Cy + Mg), b = (Ye + G),.
(In FIG. 12A). A2 line signal is sampling pulse SHP1 (illustrated in Fig. E)
To form a continuous signal S1 of (Cy + Mg) (shown in FIG. B). Further, the signal of the A2 line is sampled by a sampling pulse SHP2 (shown in FIG. F) to form a continuous signal S2 of (Ye + G) (shown in FIG. C). Then, the signal S1 is subtracted from the signal S2 to obtain a blue difference signal-(BY) (illustrated in FIG. D). That is, it is approximated by the following equation.

− (B−Y) = {(Ye + G) − (Cy + Mg)} = − (2B−G) (4) The red difference signal R is similarly applied to the other lines in the A field and the lines in the B field. −Y and the blue difference signal − (B−Y) are obtained alternately in a line-sequential manner.

Returning to FIG. 8, the imaging signal output from the CDS circuit 3 is supplied to the gamma correction circuit 6 via the AGC circuit 5.

Then, the imaging signal output from the gamma correction circuit 6 is supplied to a low-pass filter 7 constituting a luminance processing unit. In this low-pass filter 7, the expression (1), the expression (2)
The averaging of adjacent signals as shown in the equation is performed.
Therefore, the low-pass filter 7 outputs the luminance signal Y
Is output.

The imaging signal output from the gamma correction circuit 6 is
The signals are supplied to sample and hold circuits 8 and 9 constituting a chroma processing unit. The sampling pulses SHP1 and SHP2 (see E and F in FIGS. 11 and 12) are supplied from the timing generator 4 to the sample and hold circuits 8 and 9, respectively.

From the sample and hold circuit 8, a continuous signal S1 of (Cy + G) or (Cy + Mg) is output and supplied to the subtracter 10 (shown in FIGS. 11B and 12B). From the sample-and-hold circuit 9, a continuous signal S2 of (Ye + Mg) or (Ye + G) is output and supplied to the subtracter 10 (the
11C and FIG. 12C).

The subtractor 10 subtracts S1 from the signal S2. for that reason,
The subtractor 10 alternately outputs the red difference signal RY and the blue difference signal-(BY) shown in the equations (3) and (4) line-sequentially (FIG. 11D and FIG. 11D). FIG. 12D).

Although not shown, the luminance signal Y and the color difference signal R-Y /
− (BY) is supplied to the encoder, and an NTSC video signal SV is formed, for example.

By the way, in the example of FIG. 8, the color difference signals RY and-(BY) are output line-sequentially from the subtractor 10 (see FIG. 13).

FIG. 14 shows an example in which a circuit for synchronizing the color difference signals output line-sequentially is added.

15, the output signal of the subtractor 10 (shown in FIG. 15A) is supplied to the H-side fixed terminal of the direct changeover switch 16 and the L-side fixed terminal of the changeover switch 17. The output signal of the subtracter 10 is supplied to a delay circuit 18 having a delay time of one horizontal period (1H). The output signal of the delay circuit 18 (shown in FIG. The terminal and the fixed terminal on the H side of the changeover switch 17 are supplied.

The changeover switches 16 and 17 are supplied with a changeover control signal SW1 from the timing generator 4. This switching control signal SW1 is
During the horizontal period in which the output signal of the subtractor 10 is the red color difference signal RY, it goes to the high level "H" and the blue color difference signal-(B-
The horizontal period Y) is at the low level (illustrated in FIG. C). The switches 16 and 17 are connected to the H side when the switch control signal SW1 is at the high level “H”, and are connected to the L side when the switch control signal SW1 is at the low level “L”.

Therefore, the changeover switch 16 outputs the red difference signal RY in each horizontal period (shown in FIG. D), and the changeover switch 17 outputs the blue difference signal-(BY) in each horizontal period. This is shown in FIG. E), thereby achieving synchronization.

[Problem to be Solved by the Invention] Here, as shown in FIG. 16A, a case is considered where the color of the captured image changes from red to blue at point P1 in the vertical direction. Focusing on the A field, it is assumed that the point P1 is located between the A3 line and the A4 line (shown in FIG. B).

In this case, the output signal of the subtracter 10 becomes as shown in FIG. 7B, the output signal of the delay circuit 18 becomes as shown in FIG. 9C, and the output signals of the changeover switches 16 and 17 become D and E in FIG. As shown. In the figure, the hatched portion is a signal for blue information, and the other portions are signals for red information.

Here, when observing the horizontal period in which the output signal of the subtracter 10 is the A4 line, the output signal of the changeover switch 16 becomes the red difference signal RY related to the red information and the changeover switch 17
Is a blue difference signal − (B−Y) related to blue information, resulting in color misregistration.

Therefore, conventionally, it has been proposed to suppress a color signal at a color edge portion so that a color shift is not conspicuous.

In this case, since the color signal is suppressed at the color edge portion, there is no color cast at the color edge portion. Further, since a circuit for detecting a color edge portion, a circuit for suppressing a color signal, and the like are required, the circuit configuration becomes complicated and expensive.

Accordingly, it is an object of the present invention to basically prevent a color shift from occurring at a color edge portion.

[Means for Solving the Problems] The present invention provides a single-plate type in which first and second signals that become first and second color difference signals for each line when subtracted from each other are sequentially output for each pixel period. Color solid-state imaging device and the position of an image captured by the solid-state imaging device
In the frame, a pixel shift driver that shifts by one line interval in the vertical direction with respect to the first frame, and first and second frame memories that store the first and second frame imaging signals output from the solid-state imaging device, respectively. From the first and second frame memories, and read the imaging signals of the first and second frames in parallel by shifting the read timing of the second frame memory with respect to the first frame memory by one horizontal period. A read control circuit;
And first and second signal processing circuits for processing image signals of the first and second frames read from the second frame memory to obtain first and second color difference signals in a line-sequential manner, respectively, and the first and second signal processing circuits. And a first and a second switch circuit for selecting the first and second color difference signals in a cycle of one horizontal period from an output signal of the second signal processing circuit.

[Operation] The imaging element 2 performs imaging in the first and second frames with the image position shifted in the vertical direction by one line interval.

From the first and second frame memories 14a and 14b, the readout timing is shifted by one horizontal period, and the image pickup signals of the first and second frames are read out in parallel.

Then, the first and second signal processing circuits output the first and second color difference signals, respectively, line-sequentially.

Then, the first and second switch circuits 16 and 17 respectively output the first and second color difference signals in a synchronized manner.

Therefore, the first and second lines existing for each line
Since the synchronization is performed using the color difference signal, the color shift at the color edge portion in the vertical direction is prevented, and the resolution is improved.

Embodiment An embodiment of the present invention will be described below with reference to FIG. This example is an example in which a still image is captured.

In FIG. 1, portions corresponding to those in FIG. 8 are denoted by the same reference numerals, and detailed description thereof will be omitted.

In the present example, the optical path of the image light supplied to the image pickup device 2 via the image pickup lens 1 is changed by the pixel shift driver 11 or the position of the image pickup device 2 is moved, and the image picked up by the image pickup device 2 is obtained. The position is sequentially shifted for each frame. That is, as shown in FIG. 2, the second frame is vertically shifted by two pixel pitches Pv with respect to the first frame.
(For one line).

The operation of the pixel shift driver 11 is controlled by the controller 12. The controller 12 is supplied with a horizontal synchronizing signal HD and a vertical synchronizing signal VD from the timing generator 4.

The imaging signal output from the gamma correction circuit 6 is
After being converted into a digital signal by the A / D converter 13, it is supplied to the frame memories 14a and 14b. The writing and reading of these frame memories 14a and 14b are controlled by the controller 12.

In other words, the frame memories 14a and 14b have the first image captured with the image position shifted as described above.
And the imaging signal of the second frame are sequentially written.

Then, the imaging signals are read from these frame memories 14a and 14b in parallel. In this case, the read timing of the image signal from each of the frame memories 14a and 14b is sequentially adjusted in accordance with the shift amount of the image position picked up by the image sensor 2. That is, based on the read timing of the frame memory 14b, the read timing of the frame memory 14a is delayed by one horizontal period (1H).

Note that the image signals of the same frame are repeatedly read from the frame memories 14a and 14b, and become image signals for a still image.

The imaging signal output from the frame memory 14a is converted into an analog signal by the D / A converter 15a, and then supplied to the sample and hold circuits 8a and 9a. The sampling pulses SHP1 and SHP2 are supplied from the timing generator 4 to the sample and hold circuits 8a and 9a, respectively. Then, the output signals of the sample and hold circuits 8a and 9a are respectively supplied to the subtractor 10a. The configurations of the sample and hold circuits 8a and 9a and the subtractor 10a are the same as the configurations of the sample and hold circuits 8, 9 and the subtractor 10 in the example of FIG. 8, so that the red difference signal RY, The blue difference signal-(BY) is output alternately and line-sequentially (shown in FIG. 4A).

The imaging signal output from the frame memory 14b is converted into an analog signal by the D / A converter 15b, and then supplied to the sample and hold circuits 8b and 9b. The sampling pulses SHP1 and SHP2 are supplied from the timing generator 4 to the sample and hold circuits 8b and 9b, respectively. Then, the output signals of the sample and hold circuits 8b and 9b are respectively supplied to the subtractor 10b. The configurations of the sample and hold circuits 8b and 9b and the subtractor 10b are the same as the configurations of the sample and hold circuits 8, 9 and the subtractor 10 in the example of FIG. 8, so that the red difference signal RY, The blue difference signal-(BY) is output alternately and line-sequentially (shown in FIG. 4B).

In this manner, the red difference signal RY and the blue difference signal-(BY) are alternately output line-sequentially from both the subtracters 10a and 10b, and the output signal of the subtractor 10a is It is delayed by one horizontal period from the output signal.

FIG. 3 shows a screen pattern of the image sensor 2 and a subtractor.
The relationship between the output signals of 10a and 10b is shown.

The output signal of the subtractor 10a is supplied to the fixed terminal on the H side of the changeover switch 16 and also supplied to the fixed terminal on the L side of the changeover switch 17. The output signal of the subtractor 10b is
While being supplied to the fixed terminal on the L side of the changeover switch 16,
It is supplied to the fixed terminal on the H side of the changeover switch 17.

The changeover switches 16 and 17 are supplied with a changeover control signal SW1 'from the timing generator 4. This switching control signal SW1 '
Is high during a horizontal period in which the output signal of the subtractor 10a is the red difference signal RY, and the blue difference signal
The horizontal period (BY) is at the low level “L” (shown in FIG. 4C). The switches 16 and 17 are connected to the H side when the switch control signal SW1 'is at the high level "H", and are connected to the L side when the switch control signal SW1' is at the low level "L".

Accordingly, the red color difference signal RY is output from the changeover switch 16 in each horizontal period (shown in FIG. 4D), and the blue color difference signal-(BY) is output from the changeover switch 17 in each horizontal period ( (Illustrated in FIG. E). Further, the imaging signal output from the frame memory 14b is supplied to the low-pass filter 7 via the D / A converter 15b, and the adjacent signals are averaged. Therefore, from the low-pass filter 7, the eighth
A luminance signal Y is obtained as in the example shown in FIG.

As described above, in this example, the subtractor
Either of the output signals 10a and 10b includes a red signal RY and a blue difference signal-(BY) (see FIG. 3). A changeover switch is provided based on the output signals of these subtracters 10a and 10b.
16 and 17, the red difference signal RY and the blue difference signal
The synchronization selected in (BY) is performed. That is,
According to this example, the red difference signal R-
Since the synchronization is performed using the Y and blue difference signals-(BY), it is possible to prevent the occurrence of a color shift at the color edge portion in the vertical direction.

Here, as shown in FIG. 5A, consider the case where the color of the captured image changes from red to blue in the vertical direction at point P1 as a boundary. Focusing on the A field, it is assumed that the point P1 is located between the A2 line and the A3 line of the first frame (see FIG. 3).

In this case, the output signals of the subtracters 10a and 10b are as shown in FIGS. B and C, and the output signals of the changeover switches 16 and 17 are as shown in FIGS. In the figure, the hatched portion is a signal for blue information, and the other portions are signals for red information.

As is clear from the figure, the red difference signal R-
When Y and the blue difference signal-(BY) are compared, it can be seen that they have the same color information in each horizontal period and no color shift occurs.

In addition, synchronization is performed using the red difference signal RY and the blue difference signal-(B-Y) existing for each line, and the color difference signals of the same line are repeated twice and synchronized. , And a higher resolution in the vertical direction can be achieved.

In addition, the color signal is not suppressed at the color edge portion, and there is no inconvenience that the color edge portion loses color or the circuit configuration is complicated.

Furthermore, since the color difference signals on the same line are not synchronized by repeating twice, there is an advantage that a 1H delay circuit is not required.

Although the above-described embodiment is an example in which a still image is captured, it may be configured to capture a moving image. FIG. 6 shows such an example, and portions corresponding to FIG. 1 are denoted by the same reference numerals.

In this example, the contents stored in the frame memories 14a and 14b are sequentially updated with new imaging signals. That is, write control signals WC1 and WC2 are supplied from the controller 12 to the frame memories 14a and 14b, respectively (shown in FIGS. 7B and 7C). Thereby, the A / D converter 13 as shown in FIG.
With respect to the output signal of (1), signals of odd frames are alternately written to the frame memory 14a and signals of even frames are alternately written to the frame memory 14b (shown in FIGS. D and E). The numbers 1, 2, 3,... Given in FIG. 7 indicate frame numbers.

Then, from the frame memories 14a and 14b, F and G in FIG.
A signal is output as shown in FIG. Thus, the changeover switches 16 and 17 output the red color difference signals RY and-(BY) based on the sequentially changed image pickup signals. It will be available for videos.

In this example, the output signals of the D / A converters 15a and 15b are supplied to the H and L sides of the changeover switch 19, respectively. The changeover switch 19 is supplied with a changeover control signal SW2 from the timing generator 4. Switching control signal SW2
Is a signal in which a low level “L” and a high level “H” are repeated for each frame (illustrated in FIG. H). The changeover switch 19 sets the changeover control signal SW2 to a high level “H”.
Is connected to the H side, while the low level is “L”.
Is connected to the L side.

An image pickup signal updated for each frame is output from the changeover switch 19 (shown in FIG. 1) and supplied to the low-pass filter 7. As a result, the luminance signal Y updated for each frame is output from the low-pass filter 7, and can be used for a moving image.

Further, in the above-described embodiment, the imaging device 2 has the color filter of the complementary color checker method, but is not limited thereto. In other words, the first and second color difference signals are obtained for each line when subtracted from each other.
The present invention can be similarly applied to an imaging device in which the signal of (1) is sequentially output every one screen period.

[Effects of the Invention] As described above, according to the present invention, the synchronization is performed using the first and second color difference signals existing for each line, so that the vertical color edge portions are The occurrence of color shift can be prevented, and the resolution can be increased in the vertical direction. In addition, the color signal is not suppressed at the color edge portion, and there is no inconvenience that the color edge portion loses color or the circuit configuration is complicated. Furthermore, since the color difference signals on the same line are not synchronized by repeating twice, there is an advantage that a 1H delay circuit is not required.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIGS. 2 to 5 are diagrams for explaining the embodiment, FIG. 6 is a block diagram showing another embodiment of the present invention, and FIG. FIG. 8 for the explanation
9 is a diagram for explaining the prior art, FIG. 9 to FIG. 13 are diagrams for explaining the same, FIG. 14 is a diagram showing a structure in which a synchronization circuit is added in the conventional example, and FIG. 15 and FIG. FIG. DESCRIPTION OF SYMBOLS 1 ... Imaging lens 2 ... CCD color solid-state imaging device 7 ... Low-pass filter 8a, 8b, 9a, 9b ... Sample hold circuit 10a, 10b ... Subtractor 11 ... Pixel shift driver 12 ... Controller 14a, 14b …… Frame memory 16,17,19 …… Switch

Claims (1)

(57) [Claims] 1. A single-chip color solid-state imaging device in which first and second signals that become first and second color difference signals for each line when subtracted from each other are sequentially output for each pixel period. A pixel shift driver that shifts the position of an image picked up by the solid-state image sensor in the second frame by one line interval in the vertical direction with respect to the first frame; and the first and second pixels output from the solid-state image sensor. A first and a second frame memory for respectively storing an image pickup signal of a frame; and a readout timing of the second frame memory from the first and the second frame memories by one horizontal with respect to the first frame memory. A read control circuit for reading out the image signals of the first and second frames in parallel with a shift by a period, and reading the image signals from the first and second frame memories First and second signal processing circuits for processing the imaging signals of the first and second frames to obtain the first and second color difference signals in a line-sequential manner, respectively, and the first and second signal processings A color solid-state imaging device including first and second switch circuits that respectively select the first and second color difference signals in a cycle of one horizontal period from an output signal of the circuit.