JP2847862B2 - Semiconductor static memory - Google Patents

Description

Description: FIELD OF THE INVENTION The present invention relates to a semiconductor static memory,
The present invention relates to a semiconductor static memory having a configuration suitable for high-speed operation.

[Related Art] In recent years, semiconductor memories have been required to have higher speeds as capacity and density have been increased. In order to realize high-speed access, it is necessary not only to improve the process technology that determines the transistor capacity etc.
High speed on the circuit is indispensable. However, in a conventional semiconductor static memory, there are not many parts requiring a timing margin in a direction of deteriorating the access speed in circuit design, and this has hindered an increase in the speed. In this regard, a conventional example will be described with reference to the drawings.

FIG. 4 is a block diagram showing a conventional semiconductor static memory. In the figure, 1a is a memory cell array, 1b is a digit equalizer for making a pair of digit lines equipotential prior to data reading, 2 is an address buffer and an address which receive an address input Add and output an address signal α and an address change detection signal φ. The change detection circuit, 3a is a data output buffer, and 4 is a word selector and a sense amplifier. Further, ω is a word line selection signal, δ is memory cell data, δo is a sense amplifier output, and Dout is output data.

FIG. 5 is an operation waveform diagram of the apparatus of FIG. As shown in FIG. 5, when the address input changes at the time point a, the address change detection signal φ is output from the address buffer and the address change detection circuit 2 at the time point b. This signal activates the digit equalizer, and the equalizing operation is completed at time point c. Next, the word line selection signal ω is switched. At this time, the word line selection signal for selecting the word line is selected after the digit line equalization is completed and by the previous address input. It is adjusted so that it becomes high level at the time point d after the selected signal becomes low level.

The reason for equalizing the digit line is to prevent the influence of the previous data, and to wait for the word line selected by the previous address to go to the low level, it is necessary to use multiple word lines. This is to prevent the data in the memory cell from being destroyed by the simultaneous selection.

[Problems to be Solved by the Invention] In the above-described conventional semiconductor static memory, there is a problem that it takes time to equalize digit lines and hinders speeding up. This is because the digit line is equalized after the address is changed, the equalizing takes a long time due to the large capacity of the digit line, and the equalizing signal width can be completely equalized when one address changes. Because of this setting, when all the addresses change, the equalized signal width becomes larger than necessary.

Further, in the conventional example, in order to prevent a plurality of word lines from being selected in the same drawing, the selection of a newly selected word line is delayed until the word line selected in the previous cycle becomes low level. There are also problems.

The delay time due to these adjustments accounts for about 15% of the entire delay time, that is, the access time of the semiconductor static memory.

Thus, in the conventional semiconductor static memory,
The need for internal timing adjustments has severely hindered higher speeds.

[Means for Solving the Problems] A semiconductor static memory according to the present invention includes a plurality of memory cells arranged in rows and columns, a first and a second word line provided for each memory cell row, First and second sets of digit lines provided for each memory cell column, a first word line selection circuit for selecting one word line from the plurality of first word lines, and a plurality of first and second word lines. A second word line selection circuit for selecting one word line from the two word lines, an address change detection circuit for receiving an address input and generating an address change detection signal when the address input changes, and an address change detection A port selector for switching the word line selection circuit to be activated from the first to the second or vice versa each time the signal is received, and the first set and the second set of digital selectors. And a data output buffer for selectively outputting one of the data of the bit line.

[Example] Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 (a) is a block diagram showing a first embodiment of the present invention, FIG. 1 (b) is a circuit diagram of a memory cell used therein, and FIG. FIG. 3 is a circuit diagram of the embodiment of FIG.

The memory cell used in this embodiment is shown in FIG.
As shown in FIG. 5, the circuit is composed of driver transistors Q1, Q2, resistors R, R, and transfer transistors Q3 to Q6. The memory cell data δA, δB is supplied to the transistor Q by the word line selection signal
3, to the digit line 8A via Q4, and to the transistor Q5, by the word line selection signal ωB for selecting the word line 7B.
The data is read out to the digit line 8B via Q6.

In FIG. 1 (a), 1 is a memory cell array in which the memory cells of FIG. 1 (b) are arranged in a matrix, 2 is an address buffer and an address change detection circuit, 3 is a data output buffer, and 4A and 4B are Ports A and B, 6 each having a word selector and a sense amplifier function (equivalent to the function 4 in FIG. 4) are provided with an address change detection signal φ.
Received, the port selection signals λ complementary to each other by a toggle operation
A and A are port selectors that generate λB. Here, the port selector 6 can be constituted by a T-flip-flop. Ports A4A and B5B are alternately activated by port selection signals λA and λB.

A and B are used to indicate the port A side and the port B side, respectively. However, in the following, if it is not particularly necessary to indicate any of the ports, A and B are appropriately used.
Shall be omitted.

FIG. 1C is a circuit diagram of the present embodiment including a write circuit. In the figure, 10 is a write data bus,
9A and 9B are write control buses for transmitting gate signals to transistors Q7 to Q10 connecting the write data bus 10 and the digit lines 8A and 8B, and 11 is a memory cell described in FIG. 1B.

As shown in FIG. 1C, the data output buffer 3 includes AND gates 31 to 33, OR gates 34 and 35, and an inverter 3
4, composed of transistors Q11 and Q12, and port 4
A and 4B each include a sense amplifier 41, an AND gate 42 for selecting a word line, and an AND gate 43 for selecting the sense amplifier 41.

In the present embodiment, the conventional timing adjustment is not performed for selecting a word line, and the timing delay is determined only by the operation delay of the address change detection circuit, the port selector 6, and the port. The selected port sets the word line of the memory cell to a high level by the word line selection signal ωA (or ωB). The read memory cell data δA (or δB) is amplified by the sense amplifier of each port to output the sense amplifier output δAo (or δB).
The data is transmitted to the data output buffer 3 as o). on the other hand,
The data output buffer is controlled so as to output only the output from the port selected by the port selection signal λ.

 FIG. 2 shows a logical waveform diagram of a main part in this embodiment.

When the address input Add changes at time point a, the port selection signal λ switches at time point c. Here, it is assumed that port A is selected at this time. In that case,
Since the digit line 8A on the port A side has been sufficiently equalized in the previous cycle, an equalizing margin becomes unnecessary, and the port A can raise the word line select signal ωA immediately after being activated by the port select signal λ. Yes (time d). In this case, since the memory cells of the port A and the port B are associated with separate digit lines, it is not necessary to wait for the falling of the word line selection signal ωB to cause the word line selection signal ωA to rise.

FIG. 3 (a) is a block diagram showing a second embodiment of the present invention, and FIG. 3 (b) is a circuit diagram thereof. In these figures, parts that are the same as the parts in FIG. 1 are given the same reference symbols.

In this embodiment, the port A5A and the port B5B are constituted by a sense amplifier 51 and AND gates 52 and 53, and the output of the sense amplifier 51 is also controlled by the port selection signal λ. Therefore, data to the data output buffer 3a is transferred via a data bus shared by both ports as shown in FIG. 3 (a).

In this embodiment, as in the previous embodiment, there is no need to adjust the equalization margin of the digit line or the timing with the word line selected in the previous cycle.

[Effects of the Invention] As described above, according to the present invention, circuit operations independent of each other by two ports are alternately performed for each cycle. This eliminates the need for waiting time for equalizing digit lines and waiting time for selecting a new word line to prevent a plurality of word lines from being selected at the same time. Therefore, according to the present invention, at the time of access, the time corresponding to these margins, that is, about 15% of the entire delay time
%, And a high-speed semiconductor static memory can be provided.

[Brief description of the drawings]

1 (a) and 1 (c) are a block diagram and a circuit diagram, respectively, showing a first embodiment of the present invention, and FIG.
FIG. 2 is a circuit diagram of a memory cell used in the first embodiment, FIG. 2 is an explanatory diagram of the operation of the first embodiment, and FIGS. 3 (a) and 3 (b) are diagrams of the present invention, respectively. FIG. 4 is a block diagram and a circuit diagram showing a second embodiment, FIG. 4 is a block diagram showing a conventional example,
FIG. 5 is an explanatory diagram of the operation. 1, 1a: Memory cell array, 1b: Digit equalizer, 2: Address buffer and address change detection circuit, 3, 3a: Data output buffer, 4: Word selector and sense amplifier, 4A, 5A: Port A , 4B, 5B…
Port B, 6 Port selector, 7A, 7B Word line, 8A, 8B Digit line, 9A, 9B Write control bus, 10 Write data bus, 11 Memory cell, Add ... Address input, α ... Address signal, φ ...
... Address change detection signals, λ, λA, λB... Port selection signals, ω, ωA, ωB... Word line selection signals, δ, δ
A, δB ... memory cell data, δo, δAo, δBo ...
Sense amplifier output, Dout ... output data, DOE ... output enable signal.

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G11C 11/41

Claims (2)

(57) [Claims] A plurality of memory cells arranged in a row and column direction; first and second word lines provided for each memory cell row; and a first set provided for each memory cell column. And a second set of digit lines, a first word line selection circuit for selecting one word line from the plurality of first word lines, and one word line from the plurality of second word lines. A second word line selection circuit for selecting an address, an address change detection circuit for receiving an address input and generating an address change detection signal when the address input changes, and an output being turned off each time the address change detection signal is received. In other words, a port selector that alternately switches the word line selection circuit to be activated from first to second or vice versa, and selectively selects one of the data of the first and second sets of digit lines. output And a data output buffer. 2. An output buffer for receiving an output of the port selector and alternately switching digit line data to be output from a first set to a second set or vice versa. The static memory according to claim 1.