JPS6236311B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to memory circuits, and more particularly to memory circuits comprising one transistor/bit memory cell.

Figure 1 is a block diagram of a conventional memory circuit, with a 64 x 64 bit memory array, 64 rows and 64
The case of a square arrangement of columns is shown. The memory cell array is divided into first and second row groups 30, 40, each group having 32 row lines or word lines 1.
7 and 17', respectively. 64 2 inputs 1, 2
A differential amplifier 12 is provided having two inputs connected to the column lines or bit lines 16, 16' belonging to the first and second row groups 30, 40, respectively. Also, the first row group 30
64.times.32 one-transistor memory cells 10 are provided at the intersections of the bit lines 16 and word lines 17. Similarly, bit line 1 of second row group 40
64.times.32 memory cells 10' are provided at the intersection of 6' and the error line 17'. 1st row group 3
A row address decoder 18 is connected to each 0 word line 17, and a row address decoder 18' is connected to each word line 17' of the second row group 40. Each bit line 16 connects each switching gate 20
It is connected to an input/output bus (I/O bus) 13 through. The switching gates 20 are switched on and off by 64 column address decoders 15, respectively. The output sense amplifier 14 is an I/O
1 input 4 connected to bus 13 and reference voltage (V _M
-ΔV) is supplied to the other input 3.
Write signal 1N is supplied to I/O bus 13 through write gate 19 which is opened by write timing signal W. Furthermore, 64 me cells 11 are provided at each intersection between the bit line 16 and the selection line 21.
Also, at each intersection of the bit line 16' and the selection line 21', 64
dummy cells 11' are provided. These dummy cells are used to generate a reference voltage for each differential amplifier 12.

Information on one memory cell 10 selected by row decoder 18 and column decoder 15 appears on bit line 16 to which the selected memory cell belongs. This bit line 16 is turned on by the decoder 15. I/through the switching gate 20
It is connected to the O bus 13. Therefore, the selected memory cell information is sent to one input of the output differential amplifier 14, which operates as a sense amplifier, to the I/O bus 1.
3. In this case, one of the row lines 17 belonging to the first row group 30 is connected to the row decoder 1
8, the dummy cell 1 belonging to the second row group 40 is selected by the selection signal 21'.
1' is selected at the same time. On the other hand, one of the row lines 17' belonging to the second row group 40 is connected to the row decoder 1.
8', the selection signal 21 selects the dummy cell 1 belonging to the first row group 30.
1 are selected at the same time. As described above, when one of the memory cells 10 belonging to the first row group 30 is selected, the potential of the selected bit line 16 supplied to 1 input 1 of the amplifier 12 is such that the cell information is at a low level. If it is at a high level, it will drop significantly, and if it is at a high level, it will drop very slightly. At the same time, amplifier 1
The potential of the bit line 16' supplied to the other input 2 of 2 is slightly lowered below the initial setting potential by the dummy cell 11' belonging to the second row group 40. Simultaneously with the activation of the amplifier 12, the potential difference between the bit lines 16 and 16' is amplified by the amplifier 12. The amplified output is routed to the I/O bus 13 through the selected bit line 16 and the conducting gate 20 connected to that bit line 16. Then, it is led to one input 4 of the sense amplifier 14, and this input signal is compared with the reference voltage of the other input 3. This voltage is amplified by an amplifier 14 and supplied to an output circuit (not shown).

In such conventional memory circuits, one of the row lines is always changed to a select level, and then one of the bit lines is connected to the I/O bus through a switching gate driven by a column decoder. As the storage capacity increases, the number of column decoders increases dramatically, and the number of input transistors that make up each column decoder also increases dramatically as the required address bits increase. do. Therefore, it has become impossible to miniaturize the peripheral circuits. Furthermore, as the storage capacity increases, the number of gates 20 connected to the input/output bus line 13 increases, and thus the capacity of the input/output bus line 13 increases.
3, the level change becomes slow, resulting in a disadvantage that the read speed decreases.

SUMMARY OF THE INVENTION An object of the present invention is to provide a memory circuit in which the peripheral circuitry is miniaturized and capable of high-speed reading, which solves these drawbacks.

A memory circuit according to the present invention has a plurality of column line pairs each provided with a sense amplifier and a transmission gate means for selectively connecting the sense amplifier and a bus line, wherein each column line pair is connected to a plurality of columns. divided into column line pair groups having line pairs,
An independent bus line and an output amplifier were provided for each group of column line pairs connected to the transmission gate means in the group, and an output was commonly supplied to each one of the transmission gate means of each group of column line pairs. The number of selection means equal to the number of column lines included in the column line pair group is provided,
The present invention is characterized in that the output of one of the output amplifiers is selected and extracted.

According to the present invention, since the selection means for column selection is provided commonly to each column line pair group,
The number of column line pairs as a whole can be reduced to the number of column line pairs included in approximately one column line pair group, and the number of address input transistors in each selection means can also be greatly reduced. Therefore, the selection means can be constituted by elements whose number of column line pairs is exponentially reduced as a whole.

Further, in the present invention, when connecting the sense amplifier to the bus line, one end of the bit line of each column is connected to the sense amplifier, and the other end of the bit line is connected to the bus line via a transmission gate. That is,
The sense amplifier and the transmission gate are connected to different ends of the bit line. Therefore, it is possible to place the transmission gate and the sense amplifier apart, and the sense amplifier can be made less susceptible to noise and coupling caused by the operation of the transmission gate, which is advantageous for increasing sensitivity. .

Furthermore, since the bus lines are provided independently for each column line pair group, the number of transmission gates connected to each bus line is greatly reduced, and thus the capacity of each bus line is reduced, resulting in high speed It becomes possible to drive the

An embodiment of the present invention will be described with reference to FIG.

In the figure, one decoder 15' is provided to select bit lines 16 and 16' in adjacent columns, and in a 64 x 64 bit array, one column decoder 15'
5', and four switching gates 20, 20' connected to bit lines of adjacent columns.
are simultaneously controlled by the output 22 of one column decoder 15'. In this way, since two column lines are selected by one column decoder, the I/O
bus 13 to I/O buses 13A, 13B and I/O
It is divided into buses 13A' and 13B'. That is, for example, the bit lines 16, 16' in odd-numbered columns
Gate 2 in the same column as I/O bus 13A, 13A'
The bit lines 16, 16' of even-numbered columns are connected to the I/O buses 13B, 13B' via gates 20, 20' of equal interest. And two output sense amplifiers 14,1
4', and a pair of I/O buses 13A, connected to the odd-numbered bit lines of the output sense amplifier 14.
13A' is applied as two inputs, while a pair of I/O buses 13B, 13B' connected to even-numbered bit lines are applied to the output sense amplifier 14' as two inputs.

Also, write gates 19A and 19A' are provided on I/O buses 13A and 13A' to apply inputs IN, respectively. On the other hand, write gates 19B and 19B' are provided on I/O buses 13B and 13B' to apply inputs IN, respectively.

With this configuration, in the conventional example shown in FIG. 1, 6 address signals are input to the column decoder 15, and 2 ⁶ = 64 column lines are selected, but in this embodiment, 5 address signals are input to the column decoder 15. By inputting the address signal into the column decoder 15' and selecting 2 ⁵ =32 column line pairs, and selecting the output of the sense amplifiers 14 and 14' using one other address signal (not shown), A high-speed memory circuit can be obtained. In the case of writing as well, the gates 19A, 19A' or 19B, 19 which write the complementary input IN by the other address signal mentioned above.
A stable memory circuit can be obtained by selecting one of the sets of B′.

According to the present invention, not only can the number of column decoders 15 be reduced by approximately half as described above, but also the number of address input transistors of each decoder 15 can be reduced from 6 to 5, while the selection of two output amplifiers can be performed by 1 bit. address, so in total about 200
address input transistors can be eliminated. Furthermore, since the number of gates connected to the bus lines 13A and 13B is halved, the bus lines 13
The capacities of A and 13B can also be approximately halved.
This is due to the fact that the main part of the capacitance of the bus line is dominated by the gate 20 (specifically to which the drain or source of the transfer gate transistor is connected) connected to the bus line. Therefore, the level changes on bus lines 13A, 13B are greatly speeded up by the present invention. Conventionally, the delay of signals on the bus line occupies a large weight in the access time of a memory, together with the amplification by the sense amplifier, and therefore, a high-speed memory can be obtained by the present invention.

[Brief explanation of the drawing]

Figure 1 is a block diagram showing a conventional memory circuit.
FIG. 2 is a block diagram showing a memory circuit according to one embodiment of the present invention. 10: Memory cell, 14: Sense amplifier.

Claims (1)

[Claims] 1 memory cells arranged in rows and columns;
It includes sense amplifiers belonging to each column and a plurality of predetermined number of bus lines, the sense amplifiers are grouped into groups according to the predetermined number, and the outputs of one set of the predetermined number of sense amplifiers are integrated into a single group. The bit line is configured to be supplied to the predetermined number of bus lines simultaneously by the column selection output of the bit line, and in each column, one end of the bit line is connected to the sense amplifier of the column, and the other end of the bit line is connected to the column selection output. A memory circuit, characterized in that it is connected to the bus line via means.